1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/sched/hotplug.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/mm.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <linux/cpu.h>
21 #include <linux/cpumask.h>
22 #include <linux/reboot.h>
23 #include <linux/io.h>
24 #include <linux/compiler.h>
25 #include <linux/linkage.h>
26 #include <linux/bug.h>
27 #include <linux/kernel.h>
28
29 #include <asm/time.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/bootinfo.h>
33 #include <asm/pmon.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mipsregs.h>
37 #include <asm/bmips.h>
38 #include <asm/traps.h>
39 #include <asm/barrier.h>
40 #include <asm/cpu-features.h>
41
42 static int __maybe_unused max_cpus = 1;
43
44 /* these may be configured by the platform code */
45 int bmips_smp_enabled = 1;
46 int bmips_cpu_offset;
47 cpumask_t bmips_booted_mask;
48 unsigned long bmips_tp1_irqs = IE_IRQ1;
49
50 #define RESET_FROM_KSEG0 0x80080800
51 #define RESET_FROM_KSEG1 0xa0080800
52
53 static void bmips_set_reset_vec(int cpu, u32 val);
54
55 #ifdef CONFIG_SMP
56
57 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
58 unsigned long bmips_smp_boot_sp;
59 unsigned long bmips_smp_boot_gp;
60
61 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
62 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
63 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
64 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
65
66 /* SW interrupts 0,1 are used for interprocessor signaling */
67 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
68 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
69
70 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
71 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
72 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
73 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
74
75 static void __init bmips_smp_setup(void)
76 {
77 int i, cpu = 1, boot_cpu = 0;
78 int cpu_hw_intr;
79
80 switch (current_cpu_type()) {
81 case CPU_BMIPS4350:
82 case CPU_BMIPS4380:
83 /* arbitration priority */
84 clear_c0_brcm_cmt_ctrl(0x30);
85
86 /* NBK and weak order flags */
87 set_c0_brcm_config_0(0x30000);
88
89 /* Find out if we are running on TP0 or TP1 */
90 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
91
92 /*
93 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
94 * thread
95 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
96 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
97 */
98 if (boot_cpu == 0)
99 cpu_hw_intr = 0x02;
100 else
101 cpu_hw_intr = 0x1d;
102
103 change_c0_brcm_cmt_intr(0xf8018000,
104 (cpu_hw_intr << 27) | (0x03 << 15));
105
106 /* single core, 2 threads (2 pipelines) */
107 max_cpus = 2;
108
109 break;
110 case CPU_BMIPS5000:
111 /* enable raceless SW interrupts */
112 set_c0_brcm_config(0x03 << 22);
113
114 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
115 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
116
117 /* N cores, 2 threads per core */
118 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
119
120 /* clear any pending SW interrupts */
121 for (i = 0; i < max_cpus; i++) {
122 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
123 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
124 }
125
126 break;
127 default:
128 max_cpus = 1;
129 }
130
131 if (!bmips_smp_enabled)
132 max_cpus = 1;
133
134 /* this can be overridden by the BSP */
135 if (!board_ebase_setup)
136 board_ebase_setup = &bmips_ebase_setup;
137
138 __cpu_number_map[boot_cpu] = 0;
139 __cpu_logical_map[0] = boot_cpu;
140
141 for (i = 0; i < max_cpus; i++) {
142 if (i != boot_cpu) {
143 __cpu_number_map[i] = cpu;
144 __cpu_logical_map[cpu] = i;
145 cpu++;
146 }
147 set_cpu_possible(i, 1);
148 set_cpu_present(i, 1);
149 }
150 }
151
152 /*
153 * IPI IRQ setup - runs on CPU0
154 */
155 static void bmips_prepare_cpus(unsigned int max_cpus)
156 {
157 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
158
159 switch (current_cpu_type()) {
160 case CPU_BMIPS4350:
161 case CPU_BMIPS4380:
162 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
163 break;
164 case CPU_BMIPS5000:
165 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
166 break;
167 default:
168 return;
169 }
170
171 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
172 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
173 panic("Can't request IPI0 interrupt");
174 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
175 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
176 panic("Can't request IPI1 interrupt");
177 }
178
179 /*
180 * Tell the hardware to boot CPUx - runs on CPU0
181 */
182 static int bmips_boot_secondary(int cpu, struct task_struct *idle)
183 {
184 bmips_smp_boot_sp = __KSTK_TOS(idle);
185 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
186 mb();
187
188 /*
189 * Initial boot sequence for secondary CPU:
190 * bmips_reset_nmi_vec @ a000_0000 ->
191 * bmips_smp_entry ->
192 * plat_wired_tlb_setup (cached function call; optional) ->
193 * start_secondary (cached jump)
194 *
195 * Warm restart sequence:
196 * play_dead WAIT loop ->
197 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
198 * eret to play_dead ->
199 * bmips_secondary_reentry ->
200 * start_secondary
201 */
202
203 pr_info("SMP: Booting CPU%d...\n", cpu);
204
205 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
206 /* kseg1 might not exist if this CPU enabled XKS01 */
207 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
208
209 switch (current_cpu_type()) {
210 case CPU_BMIPS4350:
211 case CPU_BMIPS4380:
212 bmips43xx_send_ipi_single(cpu, 0);
213 break;
214 case CPU_BMIPS5000:
215 bmips5000_send_ipi_single(cpu, 0);
216 break;
217 }
218 } else {
219 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
220
221 switch (current_cpu_type()) {
222 case CPU_BMIPS4350:
223 case CPU_BMIPS4380:
224 /* Reset slave TP1 if booting from TP0 */
225 if (cpu_logical_map(cpu) == 1)
226 set_c0_brcm_cmt_ctrl(0x01);
227 break;
228 case CPU_BMIPS5000:
229 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
230 break;
231 }
232 cpumask_set_cpu(cpu, &bmips_booted_mask);
233 }
234
235 return 0;
236 }
237
238 /*
239 * Early setup - runs on secondary CPU after cache probe
240 */
241 static void bmips_init_secondary(void)
242 {
243 switch (current_cpu_type()) {
244 case CPU_BMIPS4350:
245 case CPU_BMIPS4380:
246 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
247 break;
248 case CPU_BMIPS5000:
249 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
250 cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3);
251 break;
252 }
253 }
254
255 /*
256 * Late setup - runs on secondary CPU before entering the idle loop
257 */
258 static void bmips_smp_finish(void)
259 {
260 pr_info("SMP: CPU%d is running\n", smp_processor_id());
261
262 /* make sure there won't be a timer interrupt for a little while */
263 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
264
265 irq_enable_hazard();
266 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
267 irq_enable_hazard();
268 }
269
270 /*
271 * BMIPS5000 raceless IPIs
272 *
273 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
274 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
275 * IPI1 is used for SMP_CALL_FUNCTION
276 */
277
278 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
279 {
280 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
281 }
282
283 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
284 {
285 int action = irq - IPI0_IRQ;
286
287 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
288
289 if (action == 0)
290 scheduler_ipi();
291 else
292 generic_smp_call_function_interrupt();
293
294 return IRQ_HANDLED;
295 }
296
297 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
298 unsigned int action)
299 {
300 unsigned int i;
301
302 for_each_cpu(i, mask)
303 bmips5000_send_ipi_single(i, action);
304 }
305
306 /*
307 * BMIPS43xx racey IPIs
308 *
309 * We use one inbound SW IRQ for each CPU.
310 *
311 * A spinlock must be held in order to keep CPUx from accidentally clearing
312 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
313 * same spinlock is used to protect the action masks.
314 */
315
316 static DEFINE_SPINLOCK(ipi_lock);
317 static DEFINE_PER_CPU(int, ipi_action_mask);
318
319 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
320 {
321 unsigned long flags;
322
323 spin_lock_irqsave(&ipi_lock, flags);
324 set_c0_cause(cpu ? C_SW1 : C_SW0);
325 per_cpu(ipi_action_mask, cpu) |= action;
326 irq_enable_hazard();
327 spin_unlock_irqrestore(&ipi_lock, flags);
328 }
329
330 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
331 {
332 unsigned long flags;
333 int action, cpu = irq - IPI0_IRQ;
334
335 spin_lock_irqsave(&ipi_lock, flags);
336 action = __this_cpu_read(ipi_action_mask);
337 per_cpu(ipi_action_mask, cpu) = 0;
338 clear_c0_cause(cpu ? C_SW1 : C_SW0);
339 spin_unlock_irqrestore(&ipi_lock, flags);
340
341 if (action & SMP_RESCHEDULE_YOURSELF)
342 scheduler_ipi();
343 if (action & SMP_CALL_FUNCTION)
344 generic_smp_call_function_interrupt();
345
346 return IRQ_HANDLED;
347 }
348
349 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
350 unsigned int action)
351 {
352 unsigned int i;
353
354 for_each_cpu(i, mask)
355 bmips43xx_send_ipi_single(i, action);
356 }
357
358 #ifdef CONFIG_HOTPLUG_CPU
359
360 static int bmips_cpu_disable(void)
361 {
362 unsigned int cpu = smp_processor_id();
363
364 if (cpu == 0)
365 return -EBUSY;
366
367 pr_info("SMP: CPU%d is offline\n", cpu);
368
369 set_cpu_online(cpu, false);
370 calculate_cpu_foreign_map();
371 irq_cpu_offline();
372 clear_c0_status(IE_IRQ5);
373
374 local_flush_tlb_all();
375 local_flush_icache_range(0, ~0);
376
377 return 0;
378 }
379
380 static void bmips_cpu_die(unsigned int cpu)
381 {
382 }
383
384 void __ref play_dead(void)
385 {
386 idle_task_exit();
387
388 /* flush data cache */
389 _dma_cache_wback_inv(0, ~0);
390
391 /*
392 * Wakeup is on SW0 or SW1; disable everything else
393 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
394 * IRQ handlers; this clears ST0_IE and returns immediately.
395 */
396 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
397 change_c0_status(
398 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
399 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
400 irq_disable_hazard();
401
402 /*
403 * wait for SW interrupt from bmips_boot_secondary(), then jump
404 * back to start_secondary()
405 */
406 __asm__ __volatile__(
407 " wait\n"
408 " j bmips_secondary_reentry\n"
409 : : : "memory");
410 }
411
412 #endif /* CONFIG_HOTPLUG_CPU */
413
414 const struct plat_smp_ops bmips43xx_smp_ops = {
415 .smp_setup = bmips_smp_setup,
416 .prepare_cpus = bmips_prepare_cpus,
417 .boot_secondary = bmips_boot_secondary,
418 .smp_finish = bmips_smp_finish,
419 .init_secondary = bmips_init_secondary,
420 .send_ipi_single = bmips43xx_send_ipi_single,
421 .send_ipi_mask = bmips43xx_send_ipi_mask,
422 #ifdef CONFIG_HOTPLUG_CPU
423 .cpu_disable = bmips_cpu_disable,
424 .cpu_die = bmips_cpu_die,
425 #endif
426 };
427
428 const struct plat_smp_ops bmips5000_smp_ops = {
429 .smp_setup = bmips_smp_setup,
430 .prepare_cpus = bmips_prepare_cpus,
431 .boot_secondary = bmips_boot_secondary,
432 .smp_finish = bmips_smp_finish,
433 .init_secondary = bmips_init_secondary,
434 .send_ipi_single = bmips5000_send_ipi_single,
435 .send_ipi_mask = bmips5000_send_ipi_mask,
436 #ifdef CONFIG_HOTPLUG_CPU
437 .cpu_disable = bmips_cpu_disable,
438 .cpu_die = bmips_cpu_die,
439 #endif
440 };
441
442 #endif /* CONFIG_SMP */
443
444 /***********************************************************************
445 * BMIPS vector relocation
446 * This is primarily used for SMP boot, but it is applicable to some
447 * UP BMIPS systems as well.
448 ***********************************************************************/
449
450 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
451 {
452 memcpy((void *)dst, start, end - start);
453 dma_cache_wback(dst, end - start);
454 local_flush_icache_range(dst, dst + (end - start));
455 instruction_hazard();
456 }
457
458 static inline void bmips_nmi_handler_setup(void)
459 {
460 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
461 &bmips_reset_nmi_vec_end);
462 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
463 &bmips_smp_int_vec_end);
464 }
465
466 struct reset_vec_info {
467 int cpu;
468 u32 val;
469 };
470
471 static void bmips_set_reset_vec_remote(void *vinfo)
472 {
473 struct reset_vec_info *info = vinfo;
474 int shift = info->cpu & 0x01 ? 16 : 0;
475 u32 mask = ~(0xffff << shift), val = info->val >> 16;
476
477 preempt_disable();
478 if (smp_processor_id() > 0) {
479 smp_call_function_single(0, &bmips_set_reset_vec_remote,
480 info, 1);
481 } else {
482 if (info->cpu & 0x02) {
483 /* BMIPS5200 "should" use mask/shift, but it's buggy */
484 bmips_write_zscm_reg(0xa0, (val << 16) | val);
485 bmips_read_zscm_reg(0xa0);
486 } else {
487 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
488 (val << shift));
489 }
490 }
491 preempt_enable();
492 }
493
494 static void bmips_set_reset_vec(int cpu, u32 val)
495 {
496 struct reset_vec_info info;
497
498 if (current_cpu_type() == CPU_BMIPS5000) {
499 /* this needs to run from CPU0 (which is always online) */
500 info.cpu = cpu;
501 info.val = val;
502 bmips_set_reset_vec_remote(&info);
503 } else {
504 void __iomem *cbr = BMIPS_GET_CBR();
505
506 if (cpu == 0)
507 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
508 else {
509 if (current_cpu_type() != CPU_BMIPS4380)
510 return;
511 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
512 }
513 }
514 __sync();
515 back_to_back_c0_hazard();
516 }
517
518 void bmips_ebase_setup(void)
519 {
520 unsigned long new_ebase = ebase;
521
522 BUG_ON(ebase != CKSEG0);
523
524 switch (current_cpu_type()) {
525 case CPU_BMIPS4350:
526 /*
527 * BMIPS4350 cannot relocate the normal vectors, but it
528 * can relocate the BEV=1 vectors. So CPU1 starts up at
529 * the relocated BEV=1, IV=0 general exception vector @
530 * 0xa000_0380.
531 *
532 * set_uncached_handler() is used here because:
533 * - CPU1 will run this from uncached space
534 * - None of the cacheflush functions are set up yet
535 */
536 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
537 &bmips_smp_int_vec, 0x80);
538 __sync();
539 return;
540 case CPU_BMIPS3300:
541 case CPU_BMIPS4380:
542 /*
543 * 0x8000_0000: reset/NMI (initially in kseg1)
544 * 0x8000_0400: normal vectors
545 */
546 new_ebase = 0x80000400;
547 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
548 break;
549 case CPU_BMIPS5000:
550 /*
551 * 0x8000_0000: reset/NMI (initially in kseg1)
552 * 0x8000_1000: normal vectors
553 */
554 new_ebase = 0x80001000;
555 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
556 write_c0_ebase(new_ebase);
557 break;
558 default:
559 return;
560 }
561
562 board_nmi_handler_setup = &bmips_nmi_handler_setup;
563 ebase = new_ebase;
564 }
565
566 asmlinkage void __weak plat_wired_tlb_setup(void)
567 {
568 /*
569 * Called when starting/restarting a secondary CPU.
570 * Kernel stacks and other important data might only be accessible
571 * once the wired entries are present.
572 */
573 }
574
575 void __init bmips_cpu_setup(void)
576 {
577 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
578 u32 __maybe_unused cfg;
579
580 switch (current_cpu_type()) {
581 case CPU_BMIPS3300:
582 /* Set BIU to async mode */
583 set_c0_brcm_bus_pll(BIT(22));
584 __sync();
585
586 /* put the BIU back in sync mode */
587 clear_c0_brcm_bus_pll(BIT(22));
588
589 /* clear BHTD to enable branch history table */
590 clear_c0_brcm_reset(BIT(16));
591
592 /* Flush and enable RAC */
593 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
594 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
595 __raw_readl(cbr + BMIPS_RAC_CONFIG);
596
597 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
598 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
599 __raw_readl(cbr + BMIPS_RAC_CONFIG);
600
601 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
602 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
603 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
604 break;
605
606 case CPU_BMIPS4380:
607 /* CBG workaround for early BMIPS4380 CPUs */
608 switch (read_c0_prid()) {
609 case 0x2a040:
610 case 0x2a042:
611 case 0x2a044:
612 case 0x2a060:
613 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
614 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
615 __raw_readl(cbr + BMIPS_L2_CONFIG);
616 }
617
618 /* clear BHTD to enable branch history table */
619 clear_c0_brcm_config_0(BIT(21));
620
621 /* XI/ROTR enable */
622 set_c0_brcm_config_0(BIT(23));
623 set_c0_brcm_cmt_ctrl(BIT(15));
624 break;
625
626 case CPU_BMIPS5000:
627 /* enable RDHWR, BRDHWR */
628 set_c0_brcm_config(BIT(17) | BIT(21));
629
630 /* Disable JTB */
631 __asm__ __volatile__(
632 " .set noreorder\n"
633 " li $8, 0x5a455048\n"
634 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
635 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
636 " li $9, 0x00008000\n"
637 " or $8, $8, $9\n"
638 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
639 " sync\n"
640 " li $8, 0x0\n"
641 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
642 " .set reorder\n"
643 : : : "$8", "$9");
644
645 /* XI enable */
646 set_c0_brcm_config(BIT(27));
647
648 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
649 __asm__ __volatile__(
650 " li $8, 0x5a455048\n"
651 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
652 " nop; nop; nop\n"
653 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
654 " lui $9, 0x0100\n"
655 " or $8, $9\n"
656 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
657 : : : "$8", "$9");
658 break;
659 }
660 }
661
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