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TOMOYO Linux Cross Reference
Linux/arch/mips/kernel/smp.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This program is free software; you can redistribute it and/or
  3  * modify it under the terms of the GNU General Public License
  4  * as published by the Free Software Foundation; either version 2
  5  * of the License, or (at your option) any later version.
  6  *
  7  * This program is distributed in the hope that it will be useful,
  8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 10  * GNU General Public License for more details.
 11  *
 12  * You should have received a copy of the GNU General Public License
 13  * along with this program; if not, write to the Free Software
 14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 15  *
 16  * Copyright (C) 2000, 2001 Kanoj Sarcar
 17  * Copyright (C) 2000, 2001 Ralf Baechle
 18  * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
 19  * Copyright (C) 2000, 2001 Broadcom Corporation
 20  */
 21 #include <linux/config.h>
 22 #include <linux/cache.h>
 23 #include <linux/delay.h>
 24 #include <linux/init.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/threads.h>
 28 #include <linux/module.h>
 29 #include <linux/time.h>
 30 #include <linux/timex.h>
 31 #include <linux/sched.h>
 32 
 33 #include <asm/atomic.h>
 34 #include <asm/cpu.h>
 35 #include <asm/processor.h>
 36 #include <asm/system.h>
 37 #include <asm/hardirq.h>
 38 #include <asm/mmu_context.h>
 39 #include <asm/smp.h>
 40 
 41 int smp_threads_ready;  /* Not used */
 42 
 43 // static atomic_t cpus_booted = ATOMIC_INIT(0);
 44 atomic_t cpus_booted = ATOMIC_INIT(0);
 45 
 46 cpumask_t phys_cpu_present_map;         /* Bitmask of physically CPUs */
 47 cpumask_t cpu_online_map;               /* Bitmask of currently online CPUs */
 48 int __cpu_number_map[NR_CPUS];
 49 int __cpu_logical_map[NR_CPUS];
 50 
 51 EXPORT_SYMBOL(cpu_online_map);
 52 
 53 /* These are defined by the board-specific code. */
 54 
 55 /*
 56  * Cause the function described by call_data to be executed on the passed
 57  * cpu.  When the function has finished, increment the finished field of
 58  * call_data.
 59  */
 60 void core_send_ipi(int cpu, unsigned int action);
 61 
 62 /*
 63  * Clear all undefined state in the cpu, set up sp and gp to the passed
 64  * values, and kick the cpu into smp_bootstrap();
 65  */
 66 void prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp);
 67 
 68 /*
 69  *  After we've done initial boot, this function is called to allow the
 70  *  board code to clean up state, if needed
 71  */
 72 void prom_init_secondary(void);
 73 
 74 void prom_smp_finish(void);
 75 
 76 cycles_t cacheflush_time;
 77 unsigned long cache_decay_ticks;
 78 
 79 void smp_tune_scheduling (void)
 80 {
 81         struct cache_desc *cd = &current_cpu_data.scache;
 82         unsigned long cachesize;       /* kB   */
 83         unsigned long bandwidth = 350; /* MB/s */
 84         unsigned long cpu_khz;
 85 
 86         /*
 87          * Crude estimate until we actually meassure ...
 88          */
 89         cpu_khz = loops_per_jiffy * 2 * HZ / 1000;
 90 
 91         /*
 92          * Rough estimation for SMP scheduling, this is the number of
 93          * cycles it takes for a fully memory-limited process to flush
 94          * the SMP-local cache.
 95          *
 96          * (For a P5 this pretty much means we will choose another idle
 97          *  CPU almost always at wakeup time (this is due to the small
 98          *  L1 cache), on PIIs it's around 50-100 usecs, depending on
 99          *  the cache size)
100          */
101         if (!cpu_khz) {
102                 /*
103                  * This basically disables processor-affinity scheduling on SMP
104                  * without a cycle counter.  Currently all SMP capable MIPS
105                  * processors have a cycle counter.
106                  */
107                 cacheflush_time = 0;
108                 return;
109         }
110 
111         cachesize = cd->linesz * cd->sets * cd->ways;
112         cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth;
113         cache_decay_ticks = (long)cacheflush_time/cpu_khz * HZ / 1000;
114 
115         printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n",
116                 (long)cacheflush_time/(cpu_khz/1000),
117                 ((long)cacheflush_time*100/(cpu_khz/1000)) % 100);
118         printk("task migration cache decay timeout: %ld msecs.\n",
119                 (cache_decay_ticks + 1) * 1000 / HZ);
120 }
121 
122 void __init smp_callin(void)
123 {
124 #if 0
125         calibrate_delay();
126         smp_store_cpu_info(cpuid);
127 #endif
128 }
129 
130 #ifndef CONFIG_SGI_IP27
131 /*
132  * Hook for doing final board-specific setup after the generic smp setup
133  * is done
134  */
135 asmlinkage void start_secondary(void)
136 {
137         unsigned int cpu = smp_processor_id();
138 
139         cpu_probe();
140         prom_init_secondary();
141         per_cpu_trap_init();
142 
143         /*
144          * XXX parity protection should be folded in here when it's converted
145          * to an option instead of something based on .cputype
146          */
147         pgd_current[cpu] = init_mm.pgd;
148         cpu_data[cpu].udelay_val = loops_per_jiffy;
149         prom_smp_finish();
150         printk("Slave cpu booted successfully\n");
151         cpu_set(cpu, cpu_online_map);
152         atomic_inc(&cpus_booted);
153         cpu_idle();
154 }
155 #endif /* CONFIG_SGI_IP27 */
156 
157 /*
158  * this function sends a 'reschedule' IPI to another CPU.
159  * it goes straight through and wastes no time serializing
160  * anything. Worst case is that we lose a reschedule ...
161  */
162 void smp_send_reschedule(int cpu)
163 {
164         core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF);
165 }
166 
167 spinlock_t smp_call_lock = SPIN_LOCK_UNLOCKED;
168 
169 struct call_data_struct *call_data;
170 
171 /*
172  * Run a function on all other CPUs.
173  *  <func>      The function to run. This must be fast and non-blocking.
174  *  <info>      An arbitrary pointer to pass to the function.
175  *  <retry>     If true, keep retrying until ready.
176  *  <wait>      If true, wait until function has completed on other CPUs.
177  *  [RETURNS]   0 on success, else a negative status code.
178  *
179  * Does not return until remote CPUs are nearly ready to execute <func>
180  * or are or have executed.
181  *
182  * You must not call this function with disabled interrupts or from a
183  * hardware interrupt handler or from a bottom half handler.
184  */
185 int smp_call_function (void (*func) (void *info), void *info, int retry,
186                                                                 int wait)
187 {
188         struct call_data_struct data;
189         int i, cpus = num_online_cpus() - 1;
190         int cpu = smp_processor_id();
191 
192         if (!cpus)
193                 return 0;
194 
195         data.func = func;
196         data.info = info;
197         atomic_set(&data.started, 0);
198         data.wait = wait;
199         if (wait)
200                 atomic_set(&data.finished, 0);
201 
202         spin_lock(&smp_call_lock);
203         call_data = &data;
204 
205         /* Send a message to all other CPUs and wait for them to respond */
206         for (i = 0; i < NR_CPUS; i++)
207                 if (cpu_online(cpu) && i != cpu)
208                         core_send_ipi(i, SMP_CALL_FUNCTION);
209 
210         /* Wait for response */
211         /* FIXME: lock-up detection, backtrace on lock-up */
212         while (atomic_read(&data.started) != cpus)
213                 barrier();
214 
215         if (wait)
216                 while (atomic_read(&data.finished) != cpus)
217                         barrier();
218         spin_unlock(&smp_call_lock);
219 
220         return 0;
221 }
222 
223 void smp_call_function_interrupt(void)
224 {
225         void (*func) (void *info) = call_data->func;
226         void *info = call_data->info;
227         int wait = call_data->wait;
228 
229         /*
230          * Notify initiating CPU that I've grabbed the data and am
231          * about to execute the function.
232          */
233         mb();
234         atomic_inc(&call_data->started);
235 
236         /*
237          * At this point the info structure may be out of scope unless wait==1.
238          */
239         irq_enter();
240         (*func)(info);
241         irq_exit();
242 
243         if (wait) {
244                 mb();
245                 atomic_inc(&call_data->finished);
246         }
247 }
248 
249 static void stop_this_cpu(void *dummy)
250 {
251         /*
252          * Remove this CPU:
253          */
254         cpu_clear(smp_processor_id(), cpu_online_map);
255         local_irq_enable();     /* May need to service _machine_restart IPI */
256         for (;;);               /* Wait if available. */
257 }
258 
259 void smp_send_stop(void)
260 {
261         smp_call_function(stop_this_cpu, NULL, 1, 0);
262 }
263 
264 /* Not really SMP stuff ... */
265 int setup_profiling_timer(unsigned int multiplier)
266 {
267         return 0;
268 }
269 
270 static void flush_tlb_all_ipi(void *info)
271 {
272         local_flush_tlb_all();
273 }
274 
275 void flush_tlb_all(void)
276 {
277         on_each_cpu(flush_tlb_all_ipi, 0, 1, 1);
278 }
279 
280 static void flush_tlb_mm_ipi(void *mm)
281 {
282         local_flush_tlb_mm((struct mm_struct *)mm);
283 }
284 
285 /*
286  * The following tlb flush calls are invoked when old translations are
287  * being torn down, or pte attributes are changing. For single threaded
288  * address spaces, a new context is obtained on the current cpu, and tlb
289  * context on other cpus are invalidated to force a new context allocation
290  * at switch_mm time, should the mm ever be used on other cpus. For
291  * multithreaded address spaces, intercpu interrupts have to be sent.
292  * Another case where intercpu interrupts are required is when the target
293  * mm might be active on another cpu (eg debuggers doing the flushes on
294  * behalf of debugees, kswapd stealing pages from another process etc).
295  * Kanoj 07/00.
296  */
297 
298 void flush_tlb_mm(struct mm_struct *mm)
299 {
300         preempt_disable();
301 
302         if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
303                 smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1);
304         } else {
305                 int i;
306                 for (i = 0; i < num_online_cpus(); i++)
307                         if (smp_processor_id() != i)
308                                 cpu_context(i, mm) = 0;
309         }
310         local_flush_tlb_mm(mm);
311 
312         preempt_enable();
313 }
314 
315 struct flush_tlb_data {
316         struct vm_area_struct *vma;
317         unsigned long addr1;
318         unsigned long addr2;
319 };
320 
321 static void flush_tlb_range_ipi(void *info)
322 {
323         struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
324 
325         local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
326 }
327 
328 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
329 {
330         struct mm_struct *mm = vma->vm_mm;
331 
332         preempt_disable();
333         if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
334                 struct flush_tlb_data fd;
335 
336                 fd.vma = vma;
337                 fd.addr1 = start;
338                 fd.addr2 = end;
339                 smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1);
340         } else {
341                 int i;
342                 for (i = 0; i < num_online_cpus(); i++)
343                         if (smp_processor_id() != i)
344                                 cpu_context(i, mm) = 0;
345         }
346         local_flush_tlb_range(vma, start, end);
347         preempt_enable();
348 }
349 
350 static void flush_tlb_kernel_range_ipi(void *info)
351 {
352         struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
353 
354         local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
355 }
356 
357 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
358 {
359         struct flush_tlb_data fd;
360 
361         fd.addr1 = start;
362         fd.addr2 = end;
363         on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1);
364 }
365 
366 static void flush_tlb_page_ipi(void *info)
367 {
368         struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
369 
370         local_flush_tlb_page(fd->vma, fd->addr1);
371 }
372 
373 void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
374 {
375         preempt_disable();
376         if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
377                 struct flush_tlb_data fd;
378 
379                 fd.vma = vma;
380                 fd.addr1 = page;
381                 smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1);
382         } else {
383                 int i;
384                 for (i = 0; i < num_online_cpus(); i++)
385                         if (smp_processor_id() != i)
386                                 cpu_context(i, vma->vm_mm) = 0;
387         }
388         local_flush_tlb_page(vma, page);
389         preempt_enable();
390 }
391 
392 static void flush_tlb_one_ipi(void *info)
393 {
394         unsigned long vaddr = (unsigned long) info;
395 
396         local_flush_tlb_one(vaddr);
397 }
398 
399 void flush_tlb_one(unsigned long vaddr)
400 {
401         smp_call_function(flush_tlb_one_ipi, (void *) vaddr, 1, 1);
402         local_flush_tlb_one(vaddr);
403 }
404 
405 EXPORT_SYMBOL(flush_tlb_page);
406 EXPORT_SYMBOL(flush_tlb_one);
407 EXPORT_SYMBOL(cpu_data);
408 EXPORT_SYMBOL(synchronize_irq);
409 

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