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Linux/arch/mips/kernel/traps.c

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  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
  7  * Copyright (C) 1995, 1996 Paul M. Antoine
  8  * Copyright (C) 1998 Ulf Carlsson
  9  * Copyright (C) 1999 Silicon Graphics, Inc.
 10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 11  * Copyright (C) 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
 12  * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
 13  */
 14 #include <linux/bug.h>
 15 #include <linux/compiler.h>
 16 #include <linux/context_tracking.h>
 17 #include <linux/kexec.h>
 18 #include <linux/init.h>
 19 #include <linux/kernel.h>
 20 #include <linux/module.h>
 21 #include <linux/mm.h>
 22 #include <linux/sched.h>
 23 #include <linux/smp.h>
 24 #include <linux/spinlock.h>
 25 #include <linux/kallsyms.h>
 26 #include <linux/bootmem.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/ptrace.h>
 29 #include <linux/kgdb.h>
 30 #include <linux/kdebug.h>
 31 #include <linux/kprobes.h>
 32 #include <linux/notifier.h>
 33 #include <linux/kdb.h>
 34 #include <linux/irq.h>
 35 #include <linux/perf_event.h>
 36 
 37 #include <asm/bootinfo.h>
 38 #include <asm/branch.h>
 39 #include <asm/break.h>
 40 #include <asm/cop2.h>
 41 #include <asm/cpu.h>
 42 #include <asm/cpu-type.h>
 43 #include <asm/dsp.h>
 44 #include <asm/fpu.h>
 45 #include <asm/fpu_emulator.h>
 46 #include <asm/idle.h>
 47 #include <asm/mipsregs.h>
 48 #include <asm/mipsmtregs.h>
 49 #include <asm/module.h>
 50 #include <asm/pgtable.h>
 51 #include <asm/ptrace.h>
 52 #include <asm/sections.h>
 53 #include <asm/tlbdebug.h>
 54 #include <asm/traps.h>
 55 #include <asm/uaccess.h>
 56 #include <asm/watch.h>
 57 #include <asm/mmu_context.h>
 58 #include <asm/types.h>
 59 #include <asm/stacktrace.h>
 60 #include <asm/uasm.h>
 61 
 62 extern void check_wait(void);
 63 extern asmlinkage void rollback_handle_int(void);
 64 extern asmlinkage void handle_int(void);
 65 extern u32 handle_tlbl[];
 66 extern u32 handle_tlbs[];
 67 extern u32 handle_tlbm[];
 68 extern asmlinkage void handle_adel(void);
 69 extern asmlinkage void handle_ades(void);
 70 extern asmlinkage void handle_ibe(void);
 71 extern asmlinkage void handle_dbe(void);
 72 extern asmlinkage void handle_sys(void);
 73 extern asmlinkage void handle_bp(void);
 74 extern asmlinkage void handle_ri(void);
 75 extern asmlinkage void handle_ri_rdhwr_vivt(void);
 76 extern asmlinkage void handle_ri_rdhwr(void);
 77 extern asmlinkage void handle_cpu(void);
 78 extern asmlinkage void handle_ov(void);
 79 extern asmlinkage void handle_tr(void);
 80 extern asmlinkage void handle_fpe(void);
 81 extern asmlinkage void handle_ftlb(void);
 82 extern asmlinkage void handle_mdmx(void);
 83 extern asmlinkage void handle_watch(void);
 84 extern asmlinkage void handle_mt(void);
 85 extern asmlinkage void handle_dsp(void);
 86 extern asmlinkage void handle_mcheck(void);
 87 extern asmlinkage void handle_reserved(void);
 88 
 89 void (*board_be_init)(void);
 90 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 91 void (*board_nmi_handler_setup)(void);
 92 void (*board_ejtag_handler_setup)(void);
 93 void (*board_bind_eic_interrupt)(int irq, int regset);
 94 void (*board_ebase_setup)(void);
 95 void(*board_cache_error_setup)(void);
 96 
 97 static void show_raw_backtrace(unsigned long reg29)
 98 {
 99         unsigned long *sp = (unsigned long *)(reg29 & ~3);
100         unsigned long addr;
101 
102         printk("Call Trace:");
103 #ifdef CONFIG_KALLSYMS
104         printk("\n");
105 #endif
106         while (!kstack_end(sp)) {
107                 unsigned long __user *p =
108                         (unsigned long __user *)(unsigned long)sp++;
109                 if (__get_user(addr, p)) {
110                         printk(" (Bad stack address)");
111                         break;
112                 }
113                 if (__kernel_text_address(addr))
114                         print_ip_sym(addr);
115         }
116         printk("\n");
117 }
118 
119 #ifdef CONFIG_KALLSYMS
120 int raw_show_trace;
121 static int __init set_raw_show_trace(char *str)
122 {
123         raw_show_trace = 1;
124         return 1;
125 }
126 __setup("raw_show_trace", set_raw_show_trace);
127 #endif
128 
129 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
130 {
131         unsigned long sp = regs->regs[29];
132         unsigned long ra = regs->regs[31];
133         unsigned long pc = regs->cp0_epc;
134 
135         if (!task)
136                 task = current;
137 
138         if (raw_show_trace || !__kernel_text_address(pc)) {
139                 show_raw_backtrace(sp);
140                 return;
141         }
142         printk("Call Trace:\n");
143         do {
144                 print_ip_sym(pc);
145                 pc = unwind_stack(task, &sp, pc, &ra);
146         } while (pc);
147         printk("\n");
148 }
149 
150 /*
151  * This routine abuses get_user()/put_user() to reference pointers
152  * with at least a bit of error checking ...
153  */
154 static void show_stacktrace(struct task_struct *task,
155         const struct pt_regs *regs)
156 {
157         const int field = 2 * sizeof(unsigned long);
158         long stackdata;
159         int i;
160         unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
161 
162         printk("Stack :");
163         i = 0;
164         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
165                 if (i && ((i % (64 / field)) == 0))
166                         printk("\n       ");
167                 if (i > 39) {
168                         printk(" ...");
169                         break;
170                 }
171 
172                 if (__get_user(stackdata, sp++)) {
173                         printk(" (Bad stack address)");
174                         break;
175                 }
176 
177                 printk(" %0*lx", field, stackdata);
178                 i++;
179         }
180         printk("\n");
181         show_backtrace(task, regs);
182 }
183 
184 void show_stack(struct task_struct *task, unsigned long *sp)
185 {
186         struct pt_regs regs;
187         if (sp) {
188                 regs.regs[29] = (unsigned long)sp;
189                 regs.regs[31] = 0;
190                 regs.cp0_epc = 0;
191         } else {
192                 if (task && task != current) {
193                         regs.regs[29] = task->thread.reg29;
194                         regs.regs[31] = 0;
195                         regs.cp0_epc = task->thread.reg31;
196 #ifdef CONFIG_KGDB_KDB
197                 } else if (atomic_read(&kgdb_active) != -1 &&
198                            kdb_current_regs) {
199                         memcpy(&regs, kdb_current_regs, sizeof(regs));
200 #endif /* CONFIG_KGDB_KDB */
201                 } else {
202                         prepare_frametrace(&regs);
203                 }
204         }
205         show_stacktrace(task, &regs);
206 }
207 
208 static void show_code(unsigned int __user *pc)
209 {
210         long i;
211         unsigned short __user *pc16 = NULL;
212 
213         printk("\nCode:");
214 
215         if ((unsigned long)pc & 1)
216                 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
217         for(i = -3 ; i < 6 ; i++) {
218                 unsigned int insn;
219                 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
220                         printk(" (Bad address in epc)\n");
221                         break;
222                 }
223                 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
224         }
225 }
226 
227 static void __show_regs(const struct pt_regs *regs)
228 {
229         const int field = 2 * sizeof(unsigned long);
230         unsigned int cause = regs->cp0_cause;
231         int i;
232 
233         show_regs_print_info(KERN_DEFAULT);
234 
235         /*
236          * Saved main processor registers
237          */
238         for (i = 0; i < 32; ) {
239                 if ((i % 4) == 0)
240                         printk("$%2d   :", i);
241                 if (i == 0)
242                         printk(" %0*lx", field, 0UL);
243                 else if (i == 26 || i == 27)
244                         printk(" %*s", field, "");
245                 else
246                         printk(" %0*lx", field, regs->regs[i]);
247 
248                 i++;
249                 if ((i % 4) == 0)
250                         printk("\n");
251         }
252 
253 #ifdef CONFIG_CPU_HAS_SMARTMIPS
254         printk("Acx    : %0*lx\n", field, regs->acx);
255 #endif
256         printk("Hi    : %0*lx\n", field, regs->hi);
257         printk("Lo    : %0*lx\n", field, regs->lo);
258 
259         /*
260          * Saved cp0 registers
261          */
262         printk("epc   : %0*lx %pS\n", field, regs->cp0_epc,
263                (void *) regs->cp0_epc);
264         printk("    %s\n", print_tainted());
265         printk("ra    : %0*lx %pS\n", field, regs->regs[31],
266                (void *) regs->regs[31]);
267 
268         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
269 
270         if (cpu_has_3kex) {
271                 if (regs->cp0_status & ST0_KUO)
272                         printk("KUo ");
273                 if (regs->cp0_status & ST0_IEO)
274                         printk("IEo ");
275                 if (regs->cp0_status & ST0_KUP)
276                         printk("KUp ");
277                 if (regs->cp0_status & ST0_IEP)
278                         printk("IEp ");
279                 if (regs->cp0_status & ST0_KUC)
280                         printk("KUc ");
281                 if (regs->cp0_status & ST0_IEC)
282                         printk("IEc ");
283         } else if (cpu_has_4kex) {
284                 if (regs->cp0_status & ST0_KX)
285                         printk("KX ");
286                 if (regs->cp0_status & ST0_SX)
287                         printk("SX ");
288                 if (regs->cp0_status & ST0_UX)
289                         printk("UX ");
290                 switch (regs->cp0_status & ST0_KSU) {
291                 case KSU_USER:
292                         printk("USER ");
293                         break;
294                 case KSU_SUPERVISOR:
295                         printk("SUPERVISOR ");
296                         break;
297                 case KSU_KERNEL:
298                         printk("KERNEL ");
299                         break;
300                 default:
301                         printk("BAD_MODE ");
302                         break;
303                 }
304                 if (regs->cp0_status & ST0_ERL)
305                         printk("ERL ");
306                 if (regs->cp0_status & ST0_EXL)
307                         printk("EXL ");
308                 if (regs->cp0_status & ST0_IE)
309                         printk("IE ");
310         }
311         printk("\n");
312 
313         printk("Cause : %08x\n", cause);
314 
315         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
316         if (1 <= cause && cause <= 5)
317                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
318 
319         printk("PrId  : %08x (%s)\n", read_c0_prid(),
320                cpu_name_string());
321 }
322 
323 /*
324  * FIXME: really the generic show_regs should take a const pointer argument.
325  */
326 void show_regs(struct pt_regs *regs)
327 {
328         __show_regs((struct pt_regs *)regs);
329 }
330 
331 void show_registers(struct pt_regs *regs)
332 {
333         const int field = 2 * sizeof(unsigned long);
334         mm_segment_t old_fs = get_fs();
335 
336         __show_regs(regs);
337         print_modules();
338         printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
339                current->comm, current->pid, current_thread_info(), current,
340               field, current_thread_info()->tp_value);
341         if (cpu_has_userlocal) {
342                 unsigned long tls;
343 
344                 tls = read_c0_userlocal();
345                 if (tls != current_thread_info()->tp_value)
346                         printk("*HwTLS: %0*lx\n", field, tls);
347         }
348 
349         if (!user_mode(regs))
350                 /* Necessary for getting the correct stack content */
351                 set_fs(KERNEL_DS);
352         show_stacktrace(current, regs);
353         show_code((unsigned int __user *) regs->cp0_epc);
354         printk("\n");
355         set_fs(old_fs);
356 }
357 
358 static int regs_to_trapnr(struct pt_regs *regs)
359 {
360         return (regs->cp0_cause >> 2) & 0x1f;
361 }
362 
363 static DEFINE_RAW_SPINLOCK(die_lock);
364 
365 void __noreturn die(const char *str, struct pt_regs *regs)
366 {
367         static int die_counter;
368         int sig = SIGSEGV;
369 #ifdef CONFIG_MIPS_MT_SMTC
370         unsigned long dvpret;
371 #endif /* CONFIG_MIPS_MT_SMTC */
372 
373         oops_enter();
374 
375         if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
376                        SIGSEGV) == NOTIFY_STOP)
377                 sig = 0;
378 
379         console_verbose();
380         raw_spin_lock_irq(&die_lock);
381 #ifdef CONFIG_MIPS_MT_SMTC
382         dvpret = dvpe();
383 #endif /* CONFIG_MIPS_MT_SMTC */
384         bust_spinlocks(1);
385 #ifdef CONFIG_MIPS_MT_SMTC
386         mips_mt_regdump(dvpret);
387 #endif /* CONFIG_MIPS_MT_SMTC */
388 
389         printk("%s[#%d]:\n", str, ++die_counter);
390         show_registers(regs);
391         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
392         raw_spin_unlock_irq(&die_lock);
393 
394         oops_exit();
395 
396         if (in_interrupt())
397                 panic("Fatal exception in interrupt");
398 
399         if (panic_on_oops) {
400                 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
401                 ssleep(5);
402                 panic("Fatal exception");
403         }
404 
405         if (regs && kexec_should_crash(current))
406                 crash_kexec(regs);
407 
408         do_exit(sig);
409 }
410 
411 extern struct exception_table_entry __start___dbe_table[];
412 extern struct exception_table_entry __stop___dbe_table[];
413 
414 __asm__(
415 "       .section        __dbe_table, \"a\"\n"
416 "       .previous                       \n");
417 
418 /* Given an address, look for it in the exception tables. */
419 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
420 {
421         const struct exception_table_entry *e;
422 
423         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
424         if (!e)
425                 e = search_module_dbetables(addr);
426         return e;
427 }
428 
429 asmlinkage void do_be(struct pt_regs *regs)
430 {
431         const int field = 2 * sizeof(unsigned long);
432         const struct exception_table_entry *fixup = NULL;
433         int data = regs->cp0_cause & 4;
434         int action = MIPS_BE_FATAL;
435         enum ctx_state prev_state;
436 
437         prev_state = exception_enter();
438         /* XXX For now.  Fixme, this searches the wrong table ...  */
439         if (data && !user_mode(regs))
440                 fixup = search_dbe_tables(exception_epc(regs));
441 
442         if (fixup)
443                 action = MIPS_BE_FIXUP;
444 
445         if (board_be_handler)
446                 action = board_be_handler(regs, fixup != NULL);
447 
448         switch (action) {
449         case MIPS_BE_DISCARD:
450                 goto out;
451         case MIPS_BE_FIXUP:
452                 if (fixup) {
453                         regs->cp0_epc = fixup->nextinsn;
454                         goto out;
455                 }
456                 break;
457         default:
458                 break;
459         }
460 
461         /*
462          * Assume it would be too dangerous to continue ...
463          */
464         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
465                data ? "Data" : "Instruction",
466                field, regs->cp0_epc, field, regs->regs[31]);
467         if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
468                        SIGBUS) == NOTIFY_STOP)
469                 goto out;
470 
471         die_if_kernel("Oops", regs);
472         force_sig(SIGBUS, current);
473 
474 out:
475         exception_exit(prev_state);
476 }
477 
478 /*
479  * ll/sc, rdhwr, sync emulation
480  */
481 
482 #define OPCODE 0xfc000000
483 #define BASE   0x03e00000
484 #define RT     0x001f0000
485 #define OFFSET 0x0000ffff
486 #define LL     0xc0000000
487 #define SC     0xe0000000
488 #define SPEC0  0x00000000
489 #define SPEC3  0x7c000000
490 #define RD     0x0000f800
491 #define FUNC   0x0000003f
492 #define SYNC   0x0000000f
493 #define RDHWR  0x0000003b
494 
495 /*  microMIPS definitions   */
496 #define MM_POOL32A_FUNC 0xfc00ffff
497 #define MM_RDHWR        0x00006b3c
498 #define MM_RS           0x001f0000
499 #define MM_RT           0x03e00000
500 
501 /*
502  * The ll_bit is cleared by r*_switch.S
503  */
504 
505 unsigned int ll_bit;
506 struct task_struct *ll_task;
507 
508 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
509 {
510         unsigned long value, __user *vaddr;
511         long offset;
512 
513         /*
514          * analyse the ll instruction that just caused a ri exception
515          * and put the referenced address to addr.
516          */
517 
518         /* sign extend offset */
519         offset = opcode & OFFSET;
520         offset <<= 16;
521         offset >>= 16;
522 
523         vaddr = (unsigned long __user *)
524                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
525 
526         if ((unsigned long)vaddr & 3)
527                 return SIGBUS;
528         if (get_user(value, vaddr))
529                 return SIGSEGV;
530 
531         preempt_disable();
532 
533         if (ll_task == NULL || ll_task == current) {
534                 ll_bit = 1;
535         } else {
536                 ll_bit = 0;
537         }
538         ll_task = current;
539 
540         preempt_enable();
541 
542         regs->regs[(opcode & RT) >> 16] = value;
543 
544         return 0;
545 }
546 
547 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
548 {
549         unsigned long __user *vaddr;
550         unsigned long reg;
551         long offset;
552 
553         /*
554          * analyse the sc instruction that just caused a ri exception
555          * and put the referenced address to addr.
556          */
557 
558         /* sign extend offset */
559         offset = opcode & OFFSET;
560         offset <<= 16;
561         offset >>= 16;
562 
563         vaddr = (unsigned long __user *)
564                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
565         reg = (opcode & RT) >> 16;
566 
567         if ((unsigned long)vaddr & 3)
568                 return SIGBUS;
569 
570         preempt_disable();
571 
572         if (ll_bit == 0 || ll_task != current) {
573                 regs->regs[reg] = 0;
574                 preempt_enable();
575                 return 0;
576         }
577 
578         preempt_enable();
579 
580         if (put_user(regs->regs[reg], vaddr))
581                 return SIGSEGV;
582 
583         regs->regs[reg] = 1;
584 
585         return 0;
586 }
587 
588 /*
589  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
590  * opcodes are supposed to result in coprocessor unusable exceptions if
591  * executed on ll/sc-less processors.  That's the theory.  In practice a
592  * few processors such as NEC's VR4100 throw reserved instruction exceptions
593  * instead, so we're doing the emulation thing in both exception handlers.
594  */
595 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
596 {
597         if ((opcode & OPCODE) == LL) {
598                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
599                                 1, regs, 0);
600                 return simulate_ll(regs, opcode);
601         }
602         if ((opcode & OPCODE) == SC) {
603                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
604                                 1, regs, 0);
605                 return simulate_sc(regs, opcode);
606         }
607 
608         return -1;                      /* Must be something else ... */
609 }
610 
611 /*
612  * Simulate trapping 'rdhwr' instructions to provide user accessible
613  * registers not implemented in hardware.
614  */
615 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
616 {
617         struct thread_info *ti = task_thread_info(current);
618 
619         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
620                         1, regs, 0);
621         switch (rd) {
622         case 0:         /* CPU number */
623                 regs->regs[rt] = smp_processor_id();
624                 return 0;
625         case 1:         /* SYNCI length */
626                 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
627                                      current_cpu_data.icache.linesz);
628                 return 0;
629         case 2:         /* Read count register */
630                 regs->regs[rt] = read_c0_count();
631                 return 0;
632         case 3:         /* Count register resolution */
633                 switch (current_cpu_type()) {
634                 case CPU_20KC:
635                 case CPU_25KF:
636                         regs->regs[rt] = 1;
637                         break;
638                 default:
639                         regs->regs[rt] = 2;
640                 }
641                 return 0;
642         case 29:
643                 regs->regs[rt] = ti->tp_value;
644                 return 0;
645         default:
646                 return -1;
647         }
648 }
649 
650 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
651 {
652         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
653                 int rd = (opcode & RD) >> 11;
654                 int rt = (opcode & RT) >> 16;
655 
656                 simulate_rdhwr(regs, rd, rt);
657                 return 0;
658         }
659 
660         /* Not ours.  */
661         return -1;
662 }
663 
664 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
665 {
666         if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
667                 int rd = (opcode & MM_RS) >> 16;
668                 int rt = (opcode & MM_RT) >> 21;
669                 simulate_rdhwr(regs, rd, rt);
670                 return 0;
671         }
672 
673         /* Not ours.  */
674         return -1;
675 }
676 
677 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
678 {
679         if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
680                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
681                                 1, regs, 0);
682                 return 0;
683         }
684 
685         return -1;                      /* Must be something else ... */
686 }
687 
688 asmlinkage void do_ov(struct pt_regs *regs)
689 {
690         enum ctx_state prev_state;
691         siginfo_t info = {
692                 .si_signo = SIGFPE,
693                 .si_code = FPE_INTOVF,
694                 .si_addr = (void __user *)regs->cp0_epc,
695         };
696 
697         prev_state = exception_enter();
698         die_if_kernel("Integer overflow", regs);
699 
700         force_sig_info(SIGFPE, &info, current);
701         exception_exit(prev_state);
702 }
703 
704 int process_fpemu_return(int sig, void __user *fault_addr)
705 {
706         if (sig == SIGSEGV || sig == SIGBUS) {
707                 struct siginfo si = {0};
708                 si.si_addr = fault_addr;
709                 si.si_signo = sig;
710                 if (sig == SIGSEGV) {
711                         if (find_vma(current->mm, (unsigned long)fault_addr))
712                                 si.si_code = SEGV_ACCERR;
713                         else
714                                 si.si_code = SEGV_MAPERR;
715                 } else {
716                         si.si_code = BUS_ADRERR;
717                 }
718                 force_sig_info(sig, &si, current);
719                 return 1;
720         } else if (sig) {
721                 force_sig(sig, current);
722                 return 1;
723         } else {
724                 return 0;
725         }
726 }
727 
728 /*
729  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
730  */
731 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
732 {
733         enum ctx_state prev_state;
734         siginfo_t info = {0};
735 
736         prev_state = exception_enter();
737         if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
738                        SIGFPE) == NOTIFY_STOP)
739                 goto out;
740         die_if_kernel("FP exception in kernel code", regs);
741 
742         if (fcr31 & FPU_CSR_UNI_X) {
743                 int sig;
744                 void __user *fault_addr = NULL;
745 
746                 /*
747                  * Unimplemented operation exception.  If we've got the full
748                  * software emulator on-board, let's use it...
749                  *
750                  * Force FPU to dump state into task/thread context.  We're
751                  * moving a lot of data here for what is probably a single
752                  * instruction, but the alternative is to pre-decode the FP
753                  * register operands before invoking the emulator, which seems
754                  * a bit extreme for what should be an infrequent event.
755                  */
756                 /* Ensure 'resume' not overwrite saved fp context again. */
757                 lose_fpu(1);
758 
759                 /* Run the emulator */
760                 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
761                                                &fault_addr);
762 
763                 /*
764                  * We can't allow the emulated instruction to leave any of
765                  * the cause bit set in $fcr31.
766                  */
767                 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
768 
769                 /* Restore the hardware register state */
770                 own_fpu(1);     /* Using the FPU again.  */
771 
772                 /* If something went wrong, signal */
773                 process_fpemu_return(sig, fault_addr);
774 
775                 goto out;
776         } else if (fcr31 & FPU_CSR_INV_X)
777                 info.si_code = FPE_FLTINV;
778         else if (fcr31 & FPU_CSR_DIV_X)
779                 info.si_code = FPE_FLTDIV;
780         else if (fcr31 & FPU_CSR_OVF_X)
781                 info.si_code = FPE_FLTOVF;
782         else if (fcr31 & FPU_CSR_UDF_X)
783                 info.si_code = FPE_FLTUND;
784         else if (fcr31 & FPU_CSR_INE_X)
785                 info.si_code = FPE_FLTRES;
786         else
787                 info.si_code = __SI_FAULT;
788         info.si_signo = SIGFPE;
789         info.si_errno = 0;
790         info.si_addr = (void __user *) regs->cp0_epc;
791         force_sig_info(SIGFPE, &info, current);
792 
793 out:
794         exception_exit(prev_state);
795 }
796 
797 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
798         const char *str)
799 {
800         siginfo_t info = { 0 };
801         char b[40];
802 
803 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
804         if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
805                 return;
806 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
807 
808         if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
809                        SIGTRAP) == NOTIFY_STOP)
810                 return;
811 
812         /*
813          * A short test says that IRIX 5.3 sends SIGTRAP for all trap
814          * insns, even for trap and break codes that indicate arithmetic
815          * failures.  Weird ...
816          * But should we continue the brokenness???  --macro
817          */
818         switch (code) {
819         case BRK_OVERFLOW:
820         case BRK_DIVZERO:
821                 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
822                 die_if_kernel(b, regs);
823                 if (code == BRK_DIVZERO)
824                         info.si_code = FPE_INTDIV;
825                 else
826                         info.si_code = FPE_INTOVF;
827                 info.si_signo = SIGFPE;
828                 info.si_addr = (void __user *) regs->cp0_epc;
829                 force_sig_info(SIGFPE, &info, current);
830                 break;
831         case BRK_BUG:
832                 die_if_kernel("Kernel bug detected", regs);
833                 force_sig(SIGTRAP, current);
834                 break;
835         case BRK_MEMU:
836                 /*
837                  * Address errors may be deliberately induced by the FPU
838                  * emulator to retake control of the CPU after executing the
839                  * instruction in the delay slot of an emulated branch.
840                  *
841                  * Terminate if exception was recognized as a delay slot return
842                  * otherwise handle as normal.
843                  */
844                 if (do_dsemulret(regs))
845                         return;
846 
847                 die_if_kernel("Math emu break/trap", regs);
848                 force_sig(SIGTRAP, current);
849                 break;
850         default:
851                 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
852                 die_if_kernel(b, regs);
853                 force_sig(SIGTRAP, current);
854         }
855 }
856 
857 asmlinkage void do_bp(struct pt_regs *regs)
858 {
859         unsigned int opcode, bcode;
860         enum ctx_state prev_state;
861         unsigned long epc;
862         u16 instr[2];
863 
864         prev_state = exception_enter();
865         if (get_isa16_mode(regs->cp0_epc)) {
866                 /* Calculate EPC. */
867                 epc = exception_epc(regs);
868                 if (cpu_has_mmips) {
869                         if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
870                             (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
871                                 goto out_sigsegv;
872                     opcode = (instr[0] << 16) | instr[1];
873                 } else {
874                     /* MIPS16e mode */
875                     if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
876                                 goto out_sigsegv;
877                     bcode = (instr[0] >> 6) & 0x3f;
878                     do_trap_or_bp(regs, bcode, "Break");
879                     goto out;
880                 }
881         } else {
882                 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
883                         goto out_sigsegv;
884         }
885 
886         /*
887          * There is the ancient bug in the MIPS assemblers that the break
888          * code starts left to bit 16 instead to bit 6 in the opcode.
889          * Gas is bug-compatible, but not always, grrr...
890          * We handle both cases with a simple heuristics.  --macro
891          */
892         bcode = ((opcode >> 6) & ((1 << 20) - 1));
893         if (bcode >= (1 << 10))
894                 bcode >>= 10;
895 
896         /*
897          * notify the kprobe handlers, if instruction is likely to
898          * pertain to them.
899          */
900         switch (bcode) {
901         case BRK_KPROBE_BP:
902                 if (notify_die(DIE_BREAK, "debug", regs, bcode,
903                                regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
904                         goto out;
905                 else
906                         break;
907         case BRK_KPROBE_SSTEPBP:
908                 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
909                                regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
910                         goto out;
911                 else
912                         break;
913         default:
914                 break;
915         }
916 
917         do_trap_or_bp(regs, bcode, "Break");
918 
919 out:
920         exception_exit(prev_state);
921         return;
922 
923 out_sigsegv:
924         force_sig(SIGSEGV, current);
925         goto out;
926 }
927 
928 asmlinkage void do_tr(struct pt_regs *regs)
929 {
930         u32 opcode, tcode = 0;
931         enum ctx_state prev_state;
932         u16 instr[2];
933         unsigned long epc = msk_isa16_mode(exception_epc(regs));
934 
935         prev_state = exception_enter();
936         if (get_isa16_mode(regs->cp0_epc)) {
937                 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
938                     __get_user(instr[1], (u16 __user *)(epc + 2)))
939                         goto out_sigsegv;
940                 opcode = (instr[0] << 16) | instr[1];
941                 /* Immediate versions don't provide a code.  */
942                 if (!(opcode & OPCODE))
943                         tcode = (opcode >> 12) & ((1 << 4) - 1);
944         } else {
945                 if (__get_user(opcode, (u32 __user *)epc))
946                         goto out_sigsegv;
947                 /* Immediate versions don't provide a code.  */
948                 if (!(opcode & OPCODE))
949                         tcode = (opcode >> 6) & ((1 << 10) - 1);
950         }
951 
952         do_trap_or_bp(regs, tcode, "Trap");
953 
954 out:
955         exception_exit(prev_state);
956         return;
957 
958 out_sigsegv:
959         force_sig(SIGSEGV, current);
960         goto out;
961 }
962 
963 asmlinkage void do_ri(struct pt_regs *regs)
964 {
965         unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
966         unsigned long old_epc = regs->cp0_epc;
967         unsigned long old31 = regs->regs[31];
968         enum ctx_state prev_state;
969         unsigned int opcode = 0;
970         int status = -1;
971 
972         prev_state = exception_enter();
973         if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
974                        SIGILL) == NOTIFY_STOP)
975                 goto out;
976 
977         die_if_kernel("Reserved instruction in kernel code", regs);
978 
979         if (unlikely(compute_return_epc(regs) < 0))
980                 goto out;
981 
982         if (get_isa16_mode(regs->cp0_epc)) {
983                 unsigned short mmop[2] = { 0 };
984 
985                 if (unlikely(get_user(mmop[0], epc) < 0))
986                         status = SIGSEGV;
987                 if (unlikely(get_user(mmop[1], epc) < 0))
988                         status = SIGSEGV;
989                 opcode = (mmop[0] << 16) | mmop[1];
990 
991                 if (status < 0)
992                         status = simulate_rdhwr_mm(regs, opcode);
993         } else {
994                 if (unlikely(get_user(opcode, epc) < 0))
995                         status = SIGSEGV;
996 
997                 if (!cpu_has_llsc && status < 0)
998                         status = simulate_llsc(regs, opcode);
999 
1000                 if (status < 0)
1001                         status = simulate_rdhwr_normal(regs, opcode);
1002 
1003                 if (status < 0)
1004                         status = simulate_sync(regs, opcode);
1005         }
1006 
1007         if (status < 0)
1008                 status = SIGILL;
1009 
1010         if (unlikely(status > 0)) {
1011                 regs->cp0_epc = old_epc;                /* Undo skip-over.  */
1012                 regs->regs[31] = old31;
1013                 force_sig(status, current);
1014         }
1015 
1016 out:
1017         exception_exit(prev_state);
1018 }
1019 
1020 /*
1021  * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1022  * emulated more than some threshold number of instructions, force migration to
1023  * a "CPU" that has FP support.
1024  */
1025 static void mt_ase_fp_affinity(void)
1026 {
1027 #ifdef CONFIG_MIPS_MT_FPAFF
1028         if (mt_fpemul_threshold > 0 &&
1029              ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1030                 /*
1031                  * If there's no FPU present, or if the application has already
1032                  * restricted the allowed set to exclude any CPUs with FPUs,
1033                  * we'll skip the procedure.
1034                  */
1035                 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1036                         cpumask_t tmask;
1037 
1038                         current->thread.user_cpus_allowed
1039                                 = current->cpus_allowed;
1040                         cpus_and(tmask, current->cpus_allowed,
1041                                 mt_fpu_cpumask);
1042                         set_cpus_allowed_ptr(current, &tmask);
1043                         set_thread_flag(TIF_FPUBOUND);
1044                 }
1045         }
1046 #endif /* CONFIG_MIPS_MT_FPAFF */
1047 }
1048 
1049 /*
1050  * No lock; only written during early bootup by CPU 0.
1051  */
1052 static RAW_NOTIFIER_HEAD(cu2_chain);
1053 
1054 int __ref register_cu2_notifier(struct notifier_block *nb)
1055 {
1056         return raw_notifier_chain_register(&cu2_chain, nb);
1057 }
1058 
1059 int cu2_notifier_call_chain(unsigned long val, void *v)
1060 {
1061         return raw_notifier_call_chain(&cu2_chain, val, v);
1062 }
1063 
1064 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1065         void *data)
1066 {
1067         struct pt_regs *regs = data;
1068 
1069         die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1070                               "instruction", regs);
1071         force_sig(SIGILL, current);
1072 
1073         return NOTIFY_OK;
1074 }
1075 
1076 asmlinkage void do_cpu(struct pt_regs *regs)
1077 {
1078         enum ctx_state prev_state;
1079         unsigned int __user *epc;
1080         unsigned long old_epc, old31;
1081         unsigned int opcode;
1082         unsigned int cpid;
1083         int status, err;
1084         unsigned long __maybe_unused flags;
1085 
1086         prev_state = exception_enter();
1087         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1088 
1089         if (cpid != 2)
1090                 die_if_kernel("do_cpu invoked from kernel context!", regs);
1091 
1092         switch (cpid) {
1093         case 0:
1094                 epc = (unsigned int __user *)exception_epc(regs);
1095                 old_epc = regs->cp0_epc;
1096                 old31 = regs->regs[31];
1097                 opcode = 0;
1098                 status = -1;
1099 
1100                 if (unlikely(compute_return_epc(regs) < 0))
1101                         goto out;
1102 
1103                 if (get_isa16_mode(regs->cp0_epc)) {
1104                         unsigned short mmop[2] = { 0 };
1105 
1106                         if (unlikely(get_user(mmop[0], epc) < 0))
1107                                 status = SIGSEGV;
1108                         if (unlikely(get_user(mmop[1], epc) < 0))
1109                                 status = SIGSEGV;
1110                         opcode = (mmop[0] << 16) | mmop[1];
1111 
1112                         if (status < 0)
1113                                 status = simulate_rdhwr_mm(regs, opcode);
1114                 } else {
1115                         if (unlikely(get_user(opcode, epc) < 0))
1116                                 status = SIGSEGV;
1117 
1118                         if (!cpu_has_llsc && status < 0)
1119                                 status = simulate_llsc(regs, opcode);
1120 
1121                         if (status < 0)
1122                                 status = simulate_rdhwr_normal(regs, opcode);
1123                 }
1124 
1125                 if (status < 0)
1126                         status = SIGILL;
1127 
1128                 if (unlikely(status > 0)) {
1129                         regs->cp0_epc = old_epc;        /* Undo skip-over.  */
1130                         regs->regs[31] = old31;
1131                         force_sig(status, current);
1132                 }
1133 
1134                 goto out;
1135 
1136         case 3:
1137                 /*
1138                  * Old (MIPS I and MIPS II) processors will set this code
1139                  * for COP1X opcode instructions that replaced the original
1140                  * COP3 space.  We don't limit COP1 space instructions in
1141                  * the emulator according to the CPU ISA, so we want to
1142                  * treat COP1X instructions consistently regardless of which
1143                  * code the CPU chose.  Therefore we redirect this trap to
1144                  * the FP emulator too.
1145                  *
1146                  * Then some newer FPU-less processors use this code
1147                  * erroneously too, so they are covered by this choice
1148                  * as well.
1149                  */
1150                 if (raw_cpu_has_fpu)
1151                         break;
1152                 /* Fall through.  */
1153 
1154         case 1:
1155                 if (used_math())        /* Using the FPU again.  */
1156                         err = own_fpu(1);
1157                 else {                  /* First time FPU user.  */
1158                         err = init_fpu();
1159                         set_used_math();
1160                 }
1161 
1162                 if (!raw_cpu_has_fpu || err) {
1163                         int sig;
1164                         void __user *fault_addr = NULL;
1165                         sig = fpu_emulator_cop1Handler(regs,
1166                                                        &current->thread.fpu,
1167                                                        0, &fault_addr);
1168                         if (!process_fpemu_return(sig, fault_addr) && !err)
1169                                 mt_ase_fp_affinity();
1170                 }
1171 
1172                 goto out;
1173 
1174         case 2:
1175                 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1176                 goto out;
1177         }
1178 
1179         force_sig(SIGILL, current);
1180 
1181 out:
1182         exception_exit(prev_state);
1183 }
1184 
1185 asmlinkage void do_mdmx(struct pt_regs *regs)
1186 {
1187         enum ctx_state prev_state;
1188 
1189         prev_state = exception_enter();
1190         force_sig(SIGILL, current);
1191         exception_exit(prev_state);
1192 }
1193 
1194 /*
1195  * Called with interrupts disabled.
1196  */
1197 asmlinkage void do_watch(struct pt_regs *regs)
1198 {
1199         enum ctx_state prev_state;
1200         u32 cause;
1201 
1202         prev_state = exception_enter();
1203         /*
1204          * Clear WP (bit 22) bit of cause register so we don't loop
1205          * forever.
1206          */
1207         cause = read_c0_cause();
1208         cause &= ~(1 << 22);
1209         write_c0_cause(cause);
1210 
1211         /*
1212          * If the current thread has the watch registers loaded, save
1213          * their values and send SIGTRAP.  Otherwise another thread
1214          * left the registers set, clear them and continue.
1215          */
1216         if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1217                 mips_read_watch_registers();
1218                 local_irq_enable();
1219                 force_sig(SIGTRAP, current);
1220         } else {
1221                 mips_clear_watch_registers();
1222                 local_irq_enable();
1223         }
1224         exception_exit(prev_state);
1225 }
1226 
1227 asmlinkage void do_mcheck(struct pt_regs *regs)
1228 {
1229         const int field = 2 * sizeof(unsigned long);
1230         int multi_match = regs->cp0_status & ST0_TS;
1231         enum ctx_state prev_state;
1232 
1233         prev_state = exception_enter();
1234         show_regs(regs);
1235 
1236         if (multi_match) {
1237                 printk("Index   : %0x\n", read_c0_index());
1238                 printk("Pagemask: %0x\n", read_c0_pagemask());
1239                 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1240                 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1241                 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1242                 printk("\n");
1243                 dump_tlb_all();
1244         }
1245 
1246         show_code((unsigned int __user *) regs->cp0_epc);
1247 
1248         /*
1249          * Some chips may have other causes of machine check (e.g. SB1
1250          * graduation timer)
1251          */
1252         panic("Caught Machine Check exception - %scaused by multiple "
1253               "matching entries in the TLB.",
1254               (multi_match) ? "" : "not ");
1255 }
1256 
1257 asmlinkage void do_mt(struct pt_regs *regs)
1258 {
1259         int subcode;
1260 
1261         subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1262                         >> VPECONTROL_EXCPT_SHIFT;
1263         switch (subcode) {
1264         case 0:
1265                 printk(KERN_DEBUG "Thread Underflow\n");
1266                 break;
1267         case 1:
1268                 printk(KERN_DEBUG "Thread Overflow\n");
1269                 break;
1270         case 2:
1271                 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1272                 break;
1273         case 3:
1274                 printk(KERN_DEBUG "Gating Storage Exception\n");
1275                 break;
1276         case 4:
1277                 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1278                 break;
1279         case 5:
1280                 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1281                 break;
1282         default:
1283                 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1284                         subcode);
1285                 break;
1286         }
1287         die_if_kernel("MIPS MT Thread exception in kernel", regs);
1288 
1289         force_sig(SIGILL, current);
1290 }
1291 
1292 
1293 asmlinkage void do_dsp(struct pt_regs *regs)
1294 {
1295         if (cpu_has_dsp)
1296                 panic("Unexpected DSP exception");
1297 
1298         force_sig(SIGILL, current);
1299 }
1300 
1301 asmlinkage void do_reserved(struct pt_regs *regs)
1302 {
1303         /*
1304          * Game over - no way to handle this if it ever occurs.  Most probably
1305          * caused by a new unknown cpu type or after another deadly
1306          * hard/software error.
1307          */
1308         show_regs(regs);
1309         panic("Caught reserved exception %ld - should not happen.",
1310               (regs->cp0_cause & 0x7f) >> 2);
1311 }
1312 
1313 static int __initdata l1parity = 1;
1314 static int __init nol1parity(char *s)
1315 {
1316         l1parity = 0;
1317         return 1;
1318 }
1319 __setup("nol1par", nol1parity);
1320 static int __initdata l2parity = 1;
1321 static int __init nol2parity(char *s)
1322 {
1323         l2parity = 0;
1324         return 1;
1325 }
1326 __setup("nol2par", nol2parity);
1327 
1328 /*
1329  * Some MIPS CPUs can enable/disable for cache parity detection, but do
1330  * it different ways.
1331  */
1332 static inline void parity_protection_init(void)
1333 {
1334         switch (current_cpu_type()) {
1335         case CPU_24K:
1336         case CPU_34K:
1337         case CPU_74K:
1338         case CPU_1004K:
1339         case CPU_INTERAPTIV:
1340         case CPU_PROAPTIV:
1341                 {
1342 #define ERRCTL_PE       0x80000000
1343 #define ERRCTL_L2P      0x00800000
1344                         unsigned long errctl;
1345                         unsigned int l1parity_present, l2parity_present;
1346 
1347                         errctl = read_c0_ecc();
1348                         errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1349 
1350                         /* probe L1 parity support */
1351                         write_c0_ecc(errctl | ERRCTL_PE);
1352                         back_to_back_c0_hazard();
1353                         l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1354 
1355                         /* probe L2 parity support */
1356                         write_c0_ecc(errctl|ERRCTL_L2P);
1357                         back_to_back_c0_hazard();
1358                         l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1359 
1360                         if (l1parity_present && l2parity_present) {
1361                                 if (l1parity)
1362                                         errctl |= ERRCTL_PE;
1363                                 if (l1parity ^ l2parity)
1364                                         errctl |= ERRCTL_L2P;
1365                         } else if (l1parity_present) {
1366                                 if (l1parity)
1367                                         errctl |= ERRCTL_PE;
1368                         } else if (l2parity_present) {
1369                                 if (l2parity)
1370                                         errctl |= ERRCTL_L2P;
1371                         } else {
1372                                 /* No parity available */
1373                         }
1374 
1375                         printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1376 
1377                         write_c0_ecc(errctl);
1378                         back_to_back_c0_hazard();
1379                         errctl = read_c0_ecc();
1380                         printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1381 
1382                         if (l1parity_present)
1383                                 printk(KERN_INFO "Cache parity protection %sabled\n",
1384                                        (errctl & ERRCTL_PE) ? "en" : "dis");
1385 
1386                         if (l2parity_present) {
1387                                 if (l1parity_present && l1parity)
1388                                         errctl ^= ERRCTL_L2P;
1389                                 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1390                                        (errctl & ERRCTL_L2P) ? "en" : "dis");
1391                         }
1392                 }
1393                 break;
1394 
1395         case CPU_5KC:
1396         case CPU_5KE:
1397         case CPU_LOONGSON1:
1398                 write_c0_ecc(0x80000000);
1399                 back_to_back_c0_hazard();
1400                 /* Set the PE bit (bit 31) in the c0_errctl register. */
1401                 printk(KERN_INFO "Cache parity protection %sabled\n",
1402                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1403                 break;
1404         case CPU_20KC:
1405         case CPU_25KF:
1406                 /* Clear the DE bit (bit 16) in the c0_status register. */
1407                 printk(KERN_INFO "Enable cache parity protection for "
1408                        "MIPS 20KC/25KF CPUs.\n");
1409                 clear_c0_status(ST0_DE);
1410                 break;
1411         default:
1412                 break;
1413         }
1414 }
1415 
1416 asmlinkage void cache_parity_error(void)
1417 {
1418         const int field = 2 * sizeof(unsigned long);
1419         unsigned int reg_val;
1420 
1421         /* For the moment, report the problem and hang. */
1422         printk("Cache error exception:\n");
1423         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1424         reg_val = read_c0_cacheerr();
1425         printk("c0_cacheerr == %08x\n", reg_val);
1426 
1427         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1428                reg_val & (1<<30) ? "secondary" : "primary",
1429                reg_val & (1<<31) ? "data" : "insn");
1430         if (cpu_has_mips_r2 &&
1431             ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1432                 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1433                         reg_val & (1<<29) ? "ED " : "",
1434                         reg_val & (1<<28) ? "ET " : "",
1435                         reg_val & (1<<27) ? "ES " : "",
1436                         reg_val & (1<<26) ? "EE " : "",
1437                         reg_val & (1<<25) ? "EB " : "",
1438                         reg_val & (1<<24) ? "EI " : "",
1439                         reg_val & (1<<23) ? "E1 " : "",
1440                         reg_val & (1<<22) ? "E0 " : "");
1441         } else {
1442                 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1443                         reg_val & (1<<29) ? "ED " : "",
1444                         reg_val & (1<<28) ? "ET " : "",
1445                         reg_val & (1<<26) ? "EE " : "",
1446                         reg_val & (1<<25) ? "EB " : "",
1447                         reg_val & (1<<24) ? "EI " : "",
1448                         reg_val & (1<<23) ? "E1 " : "",
1449                         reg_val & (1<<22) ? "E0 " : "");
1450         }
1451         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1452 
1453 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1454         if (reg_val & (1<<22))
1455                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1456 
1457         if (reg_val & (1<<23))
1458                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1459 #endif
1460 
1461         panic("Can't handle the cache error!");
1462 }
1463 
1464 asmlinkage void do_ftlb(void)
1465 {
1466         const int field = 2 * sizeof(unsigned long);
1467         unsigned int reg_val;
1468 
1469         /* For the moment, report the problem and hang. */
1470         if (cpu_has_mips_r2 &&
1471             ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1472                 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1473                        read_c0_ecc());
1474                 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1475                 reg_val = read_c0_cacheerr();
1476                 pr_err("c0_cacheerr == %08x\n", reg_val);
1477 
1478                 if ((reg_val & 0xc0000000) == 0xc0000000) {
1479                         pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1480                 } else {
1481                         pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1482                                reg_val & (1<<30) ? "secondary" : "primary",
1483                                reg_val & (1<<31) ? "data" : "insn");
1484                 }
1485         } else {
1486                 pr_err("FTLB error exception\n");
1487         }
1488         /* Just print the cacheerr bits for now */
1489         cache_parity_error();
1490 }
1491 
1492 /*
1493  * SDBBP EJTAG debug exception handler.
1494  * We skip the instruction and return to the next instruction.
1495  */
1496 void ejtag_exception_handler(struct pt_regs *regs)
1497 {
1498         const int field = 2 * sizeof(unsigned long);
1499         unsigned long depc, old_epc, old_ra;
1500         unsigned int debug;
1501 
1502         printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1503         depc = read_c0_depc();
1504         debug = read_c0_debug();
1505         printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1506         if (debug & 0x80000000) {
1507                 /*
1508                  * In branch delay slot.
1509                  * We cheat a little bit here and use EPC to calculate the
1510                  * debug return address (DEPC). EPC is restored after the
1511                  * calculation.
1512                  */
1513                 old_epc = regs->cp0_epc;
1514                 old_ra = regs->regs[31];
1515                 regs->cp0_epc = depc;
1516                 compute_return_epc(regs);
1517                 depc = regs->cp0_epc;
1518                 regs->cp0_epc = old_epc;
1519                 regs->regs[31] = old_ra;
1520         } else
1521                 depc += 4;
1522         write_c0_depc(depc);
1523 
1524 #if 0
1525         printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1526         write_c0_debug(debug | 0x100);
1527 #endif
1528 }
1529 
1530 /*
1531  * NMI exception handler.
1532  * No lock; only written during early bootup by CPU 0.
1533  */
1534 static RAW_NOTIFIER_HEAD(nmi_chain);
1535 
1536 int register_nmi_notifier(struct notifier_block *nb)
1537 {
1538         return raw_notifier_chain_register(&nmi_chain, nb);
1539 }
1540 
1541 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1542 {
1543         char str[100];
1544 
1545         raw_notifier_call_chain(&nmi_chain, 0, regs);
1546         bust_spinlocks(1);
1547         snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1548                  smp_processor_id(), regs->cp0_epc);
1549         regs->cp0_epc = read_c0_errorepc();
1550         die(str, regs);
1551 }
1552 
1553 #define VECTORSPACING 0x100     /* for EI/VI mode */
1554 
1555 unsigned long ebase;
1556 unsigned long exception_handlers[32];
1557 unsigned long vi_handlers[64];
1558 
1559 void __init *set_except_vector(int n, void *addr)
1560 {
1561         unsigned long handler = (unsigned long) addr;
1562         unsigned long old_handler;
1563 
1564 #ifdef CONFIG_CPU_MICROMIPS
1565         /*
1566          * Only the TLB handlers are cache aligned with an even
1567          * address. All other handlers are on an odd address and
1568          * require no modification. Otherwise, MIPS32 mode will
1569          * be entered when handling any TLB exceptions. That
1570          * would be bad...since we must stay in microMIPS mode.
1571          */
1572         if (!(handler & 0x1))
1573                 handler |= 1;
1574 #endif
1575         old_handler = xchg(&exception_handlers[n], handler);
1576 
1577         if (n == 0 && cpu_has_divec) {
1578 #ifdef CONFIG_CPU_MICROMIPS
1579                 unsigned long jump_mask = ~((1 << 27) - 1);
1580 #else
1581                 unsigned long jump_mask = ~((1 << 28) - 1);
1582 #endif
1583                 u32 *buf = (u32 *)(ebase + 0x200);
1584                 unsigned int k0 = 26;
1585                 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1586                         uasm_i_j(&buf, handler & ~jump_mask);
1587                         uasm_i_nop(&buf);
1588                 } else {
1589                         UASM_i_LA(&buf, k0, handler);
1590                         uasm_i_jr(&buf, k0);
1591                         uasm_i_nop(&buf);
1592                 }
1593                 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1594         }
1595         return (void *)old_handler;
1596 }
1597 
1598 static void do_default_vi(void)
1599 {
1600         show_regs(get_irq_regs());
1601         panic("Caught unexpected vectored interrupt.");
1602 }
1603 
1604 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1605 {
1606         unsigned long handler;
1607         unsigned long old_handler = vi_handlers[n];
1608         int srssets = current_cpu_data.srsets;
1609         u16 *h;
1610         unsigned char *b;
1611 
1612         BUG_ON(!cpu_has_veic && !cpu_has_vint);
1613 
1614         if (addr == NULL) {
1615                 handler = (unsigned long) do_default_vi;
1616                 srs = 0;
1617         } else
1618                 handler = (unsigned long) addr;
1619         vi_handlers[n] = handler;
1620 
1621         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1622 
1623         if (srs >= srssets)
1624                 panic("Shadow register set %d not supported", srs);
1625 
1626         if (cpu_has_veic) {
1627                 if (board_bind_eic_interrupt)
1628                         board_bind_eic_interrupt(n, srs);
1629         } else if (cpu_has_vint) {
1630                 /* SRSMap is only defined if shadow sets are implemented */
1631                 if (srssets > 1)
1632                         change_c0_srsmap(0xf << n*4, srs << n*4);
1633         }
1634 
1635         if (srs == 0) {
1636                 /*
1637                  * If no shadow set is selected then use the default handler
1638                  * that does normal register saving and standard interrupt exit
1639                  */
1640                 extern char except_vec_vi, except_vec_vi_lui;
1641                 extern char except_vec_vi_ori, except_vec_vi_end;
1642                 extern char rollback_except_vec_vi;
1643                 char *vec_start = using_rollback_handler() ?
1644                         &rollback_except_vec_vi : &except_vec_vi;
1645 #ifdef CONFIG_MIPS_MT_SMTC
1646                 /*
1647                  * We need to provide the SMTC vectored interrupt handler
1648                  * not only with the address of the handler, but with the
1649                  * Status.IM bit to be masked before going there.
1650                  */
1651                 extern char except_vec_vi_mori;
1652 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1653                 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1654 #else
1655                 const int mori_offset = &except_vec_vi_mori - vec_start;
1656 #endif
1657 #endif /* CONFIG_MIPS_MT_SMTC */
1658 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1659                 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1660                 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1661 #else
1662                 const int lui_offset = &except_vec_vi_lui - vec_start;
1663                 const int ori_offset = &except_vec_vi_ori - vec_start;
1664 #endif
1665                 const int handler_len = &except_vec_vi_end - vec_start;
1666 
1667                 if (handler_len > VECTORSPACING) {
1668                         /*
1669                          * Sigh... panicing won't help as the console
1670                          * is probably not configured :(
1671                          */
1672                         panic("VECTORSPACING too small");
1673                 }
1674 
1675                 set_handler(((unsigned long)b - ebase), vec_start,
1676 #ifdef CONFIG_CPU_MICROMIPS
1677                                 (handler_len - 1));
1678 #else
1679                                 handler_len);
1680 #endif
1681 #ifdef CONFIG_MIPS_MT_SMTC
1682                 BUG_ON(n > 7);  /* Vector index %d exceeds SMTC maximum. */
1683 
1684                 h = (u16 *)(b + mori_offset);
1685                 *h = (0x100 << n);
1686 #endif /* CONFIG_MIPS_MT_SMTC */
1687                 h = (u16 *)(b + lui_offset);
1688                 *h = (handler >> 16) & 0xffff;
1689                 h = (u16 *)(b + ori_offset);
1690                 *h = (handler & 0xffff);
1691                 local_flush_icache_range((unsigned long)b,
1692                                          (unsigned long)(b+handler_len));
1693         }
1694         else {
1695                 /*
1696                  * In other cases jump directly to the interrupt handler. It
1697                  * is the handler's responsibility to save registers if required
1698                  * (eg hi/lo) and return from the exception using "eret".
1699                  */
1700                 u32 insn;
1701 
1702                 h = (u16 *)b;
1703                 /* j handler */
1704 #ifdef CONFIG_CPU_MICROMIPS
1705                 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1706 #else
1707                 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1708 #endif
1709                 h[0] = (insn >> 16) & 0xffff;
1710                 h[1] = insn & 0xffff;
1711                 h[2] = 0;
1712                 h[3] = 0;
1713                 local_flush_icache_range((unsigned long)b,
1714                                          (unsigned long)(b+8));
1715         }
1716 
1717         return (void *)old_handler;
1718 }
1719 
1720 void *set_vi_handler(int n, vi_handler_t addr)
1721 {
1722         return set_vi_srs_handler(n, addr, 0);
1723 }
1724 
1725 extern void tlb_init(void);
1726 
1727 /*
1728  * Timer interrupt
1729  */
1730 int cp0_compare_irq;
1731 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1732 int cp0_compare_irq_shift;
1733 
1734 /*
1735  * Performance counter IRQ or -1 if shared with timer
1736  */
1737 int cp0_perfcount_irq;
1738 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1739 
1740 static int noulri;
1741 
1742 static int __init ulri_disable(char *s)
1743 {
1744         pr_info("Disabling ulri\n");
1745         noulri = 1;
1746 
1747         return 1;
1748 }
1749 __setup("noulri", ulri_disable);
1750 
1751 void per_cpu_trap_init(bool is_boot_cpu)
1752 {
1753         unsigned int cpu = smp_processor_id();
1754         unsigned int status_set = ST0_CU0;
1755         unsigned int hwrena = cpu_hwrena_impl_bits;
1756 #ifdef CONFIG_MIPS_MT_SMTC
1757         int secondaryTC = 0;
1758         int bootTC = (cpu == 0);
1759 
1760         /*
1761          * Only do per_cpu_trap_init() for first TC of Each VPE.
1762          * Note that this hack assumes that the SMTC init code
1763          * assigns TCs consecutively and in ascending order.
1764          */
1765 
1766         if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1767             ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1768                 secondaryTC = 1;
1769 #endif /* CONFIG_MIPS_MT_SMTC */
1770 
1771         /*
1772          * Disable coprocessors and select 32-bit or 64-bit addressing
1773          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1774          * flag that some firmware may have left set and the TS bit (for
1775          * IP27).  Set XX for ISA IV code to work.
1776          */
1777 #ifdef CONFIG_64BIT
1778         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1779 #endif
1780         if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1781                 status_set |= ST0_XX;
1782         if (cpu_has_dsp)
1783                 status_set |= ST0_MX;
1784 
1785         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1786                          status_set);
1787 
1788         if (cpu_has_mips_r2)
1789                 hwrena |= 0x0000000f;
1790 
1791         if (!noulri && cpu_has_userlocal)
1792                 hwrena |= (1 << 29);
1793 
1794         if (hwrena)
1795                 write_c0_hwrena(hwrena);
1796 
1797 #ifdef CONFIG_MIPS_MT_SMTC
1798         if (!secondaryTC) {
1799 #endif /* CONFIG_MIPS_MT_SMTC */
1800 
1801         if (cpu_has_veic || cpu_has_vint) {
1802                 unsigned long sr = set_c0_status(ST0_BEV);
1803                 write_c0_ebase(ebase);
1804                 write_c0_status(sr);
1805                 /* Setting vector spacing enables EI/VI mode  */
1806                 change_c0_intctl(0x3e0, VECTORSPACING);
1807         }
1808         if (cpu_has_divec) {
1809                 if (cpu_has_mipsmt) {
1810                         unsigned int vpflags = dvpe();
1811                         set_c0_cause(CAUSEF_IV);
1812                         evpe(vpflags);
1813                 } else
1814                         set_c0_cause(CAUSEF_IV);
1815         }
1816 
1817         /*
1818          * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1819          *
1820          *  o read IntCtl.IPTI to determine the timer interrupt
1821          *  o read IntCtl.IPPCI to determine the performance counter interrupt
1822          */
1823         if (cpu_has_mips_r2) {
1824                 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1825                 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1826                 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1827                 if (cp0_perfcount_irq == cp0_compare_irq)
1828                         cp0_perfcount_irq = -1;
1829         } else {
1830                 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1831                 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1832                 cp0_perfcount_irq = -1;
1833         }
1834 
1835 #ifdef CONFIG_MIPS_MT_SMTC
1836         }
1837 #endif /* CONFIG_MIPS_MT_SMTC */
1838 
1839         if (!cpu_data[cpu].asid_cache)
1840                 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1841 
1842         atomic_inc(&init_mm.mm_count);
1843         current->active_mm = &init_mm;
1844         BUG_ON(current->mm);
1845         enter_lazy_tlb(&init_mm, current);
1846 
1847 #ifdef CONFIG_MIPS_MT_SMTC
1848         if (bootTC) {
1849 #endif /* CONFIG_MIPS_MT_SMTC */
1850                 /* Boot CPU's cache setup in setup_arch(). */
1851                 if (!is_boot_cpu)
1852                         cpu_cache_init();
1853                 tlb_init();
1854 #ifdef CONFIG_MIPS_MT_SMTC
1855         } else if (!secondaryTC) {
1856                 /*
1857                  * First TC in non-boot VPE must do subset of tlb_init()
1858                  * for MMU countrol registers.
1859                  */
1860                 write_c0_pagemask(PM_DEFAULT_MASK);
1861                 write_c0_wired(0);
1862         }
1863 #endif /* CONFIG_MIPS_MT_SMTC */
1864         TLBMISS_HANDLER_SETUP();
1865 }
1866 
1867 /* Install CPU exception handler */
1868 void set_handler(unsigned long offset, void *addr, unsigned long size)
1869 {
1870 #ifdef CONFIG_CPU_MICROMIPS
1871         memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1872 #else
1873         memcpy((void *)(ebase + offset), addr, size);
1874 #endif
1875         local_flush_icache_range(ebase + offset, ebase + offset + size);
1876 }
1877 
1878 static char panic_null_cerr[] =
1879         "Trying to set NULL cache error exception handler";
1880 
1881 /*
1882  * Install uncached CPU exception handler.
1883  * This is suitable only for the cache error exception which is the only
1884  * exception handler that is being run uncached.
1885  */
1886 void set_uncached_handler(unsigned long offset, void *addr,
1887         unsigned long size)
1888 {
1889         unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1890 
1891         if (!addr)
1892                 panic(panic_null_cerr);
1893 
1894         memcpy((void *)(uncached_ebase + offset), addr, size);
1895 }
1896 
1897 static int __initdata rdhwr_noopt;
1898 static int __init set_rdhwr_noopt(char *str)
1899 {
1900         rdhwr_noopt = 1;
1901         return 1;
1902 }
1903 
1904 __setup("rdhwr_noopt", set_rdhwr_noopt);
1905 
1906 void __init trap_init(void)
1907 {
1908         extern char except_vec3_generic;
1909         extern char except_vec4;
1910         extern char except_vec3_r4000;
1911         unsigned long i;
1912 
1913         check_wait();
1914 
1915 #if defined(CONFIG_KGDB)
1916         if (kgdb_early_setup)
1917                 return; /* Already done */
1918 #endif
1919 
1920         if (cpu_has_veic || cpu_has_vint) {
1921                 unsigned long size = 0x200 + VECTORSPACING*64;
1922                 ebase = (unsigned long)
1923                         __alloc_bootmem(size, 1 << fls(size), 0);
1924         } else {
1925 #ifdef CONFIG_KVM_GUEST
1926 #define KVM_GUEST_KSEG0     0x40000000
1927         ebase = KVM_GUEST_KSEG0;
1928 #else
1929         ebase = CKSEG0;
1930 #endif
1931                 if (cpu_has_mips_r2)
1932                         ebase += (read_c0_ebase() & 0x3ffff000);
1933         }
1934 
1935         if (cpu_has_mmips) {
1936                 unsigned int config3 = read_c0_config3();
1937 
1938                 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
1939                         write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
1940                 else
1941                         write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
1942         }
1943 
1944         if (board_ebase_setup)
1945                 board_ebase_setup();
1946         per_cpu_trap_init(true);
1947 
1948         /*
1949          * Copy the generic exception handlers to their final destination.
1950          * This will be overriden later as suitable for a particular
1951          * configuration.
1952          */
1953         set_handler(0x180, &except_vec3_generic, 0x80);
1954 
1955         /*
1956          * Setup default vectors
1957          */
1958         for (i = 0; i <= 31; i++)
1959                 set_except_vector(i, handle_reserved);
1960 
1961         /*
1962          * Copy the EJTAG debug exception vector handler code to it's final
1963          * destination.
1964          */
1965         if (cpu_has_ejtag && board_ejtag_handler_setup)
1966                 board_ejtag_handler_setup();
1967 
1968         /*
1969          * Only some CPUs have the watch exceptions.
1970          */
1971         if (cpu_has_watch)
1972                 set_except_vector(23, handle_watch);
1973 
1974         /*
1975          * Initialise interrupt handlers
1976          */
1977         if (cpu_has_veic || cpu_has_vint) {
1978                 int nvec = cpu_has_veic ? 64 : 8;
1979                 for (i = 0; i < nvec; i++)
1980                         set_vi_handler(i, NULL);
1981         }
1982         else if (cpu_has_divec)
1983                 set_handler(0x200, &except_vec4, 0x8);
1984 
1985         /*
1986          * Some CPUs can enable/disable for cache parity detection, but does
1987          * it different ways.
1988          */
1989         parity_protection_init();
1990 
1991         /*
1992          * The Data Bus Errors / Instruction Bus Errors are signaled
1993          * by external hardware.  Therefore these two exceptions
1994          * may have board specific handlers.
1995          */
1996         if (board_be_init)
1997                 board_be_init();
1998 
1999         set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2000                                                       : handle_int);
2001         set_except_vector(1, handle_tlbm);
2002         set_except_vector(2, handle_tlbl);
2003         set_except_vector(3, handle_tlbs);
2004 
2005         set_except_vector(4, handle_adel);
2006         set_except_vector(5, handle_ades);
2007 
2008         set_except_vector(6, handle_ibe);
2009         set_except_vector(7, handle_dbe);
2010 
2011         set_except_vector(8, handle_sys);
2012         set_except_vector(9, handle_bp);
2013         set_except_vector(10, rdhwr_noopt ? handle_ri :
2014                           (cpu_has_vtag_icache ?
2015                            handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2016         set_except_vector(11, handle_cpu);
2017         set_except_vector(12, handle_ov);
2018         set_except_vector(13, handle_tr);
2019 
2020         if (current_cpu_type() == CPU_R6000 ||
2021             current_cpu_type() == CPU_R6000A) {
2022                 /*
2023                  * The R6000 is the only R-series CPU that features a machine
2024                  * check exception (similar to the R4000 cache error) and
2025                  * unaligned ldc1/sdc1 exception.  The handlers have not been
2026                  * written yet.  Well, anyway there is no R6000 machine on the
2027                  * current list of targets for Linux/MIPS.
2028                  * (Duh, crap, there is someone with a triple R6k machine)
2029                  */
2030                 //set_except_vector(14, handle_mc);
2031                 //set_except_vector(15, handle_ndc);
2032         }
2033 
2034 
2035         if (board_nmi_handler_setup)
2036                 board_nmi_handler_setup();
2037 
2038         if (cpu_has_fpu && !cpu_has_nofpuex)
2039                 set_except_vector(15, handle_fpe);
2040 
2041         set_except_vector(16, handle_ftlb);
2042         set_except_vector(22, handle_mdmx);
2043 
2044         if (cpu_has_mcheck)
2045                 set_except_vector(24, handle_mcheck);
2046 
2047         if (cpu_has_mipsmt)
2048                 set_except_vector(25, handle_mt);
2049 
2050         set_except_vector(26, handle_dsp);
2051 
2052         if (board_cache_error_setup)
2053                 board_cache_error_setup();
2054 
2055         if (cpu_has_vce)
2056                 /* Special exception: R4[04]00 uses also the divec space. */
2057                 set_handler(0x180, &except_vec3_r4000, 0x100);
2058         else if (cpu_has_4kex)
2059                 set_handler(0x180, &except_vec3_generic, 0x80);
2060         else
2061                 set_handler(0x080, &except_vec3_generic, 0x80);
2062 
2063         local_flush_icache_range(ebase, ebase + 0x400);
2064 
2065         sort_extable(__start___dbe_table, __stop___dbe_table);
2066 
2067         cu2_notifier(default_cu2_call, 0x80000000);     /* Run last  */
2068 }
2069 

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