1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mm.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/spinlock.h>
28 #include <linux/kallsyms.h>
29 #include <linux/bootmem.h>
30 #include <linux/interrupt.h>
31 #include <linux/ptrace.h>
32 #include <linux/kgdb.h>
33 #include <linux/kdebug.h>
34 #include <linux/kprobes.h>
35 #include <linux/notifier.h>
36 #include <linux/kdb.h>
37 #include <linux/irq.h>
38 #include <linux/perf_event.h>
39
40 #include <asm/addrspace.h>
41 #include <asm/bootinfo.h>
42 #include <asm/branch.h>
43 #include <asm/break.h>
44 #include <asm/cop2.h>
45 #include <asm/cpu.h>
46 #include <asm/cpu-type.h>
47 #include <asm/dsp.h>
48 #include <asm/fpu.h>
49 #include <asm/fpu_emulator.h>
50 #include <asm/idle.h>
51 #include <asm/mips-r2-to-r6-emul.h>
52 #include <asm/mipsregs.h>
53 #include <asm/mipsmtregs.h>
54 #include <asm/module.h>
55 #include <asm/msa.h>
56 #include <asm/pgtable.h>
57 #include <asm/ptrace.h>
58 #include <asm/sections.h>
59 #include <asm/tlbdebug.h>
60 #include <asm/traps.h>
61 #include <asm/uaccess.h>
62 #include <asm/watch.h>
63 #include <asm/mmu_context.h>
64 #include <asm/types.h>
65 #include <asm/stacktrace.h>
66 #include <asm/uasm.h>
67
68 extern void check_wait(void);
69 extern asmlinkage void rollback_handle_int(void);
70 extern asmlinkage void handle_int(void);
71 extern u32 handle_tlbl[];
72 extern u32 handle_tlbs[];
73 extern u32 handle_tlbm[];
74 extern asmlinkage void handle_adel(void);
75 extern asmlinkage void handle_ades(void);
76 extern asmlinkage void handle_ibe(void);
77 extern asmlinkage void handle_dbe(void);
78 extern asmlinkage void handle_sys(void);
79 extern asmlinkage void handle_bp(void);
80 extern asmlinkage void handle_ri(void);
81 extern asmlinkage void handle_ri_rdhwr_vivt(void);
82 extern asmlinkage void handle_ri_rdhwr(void);
83 extern asmlinkage void handle_cpu(void);
84 extern asmlinkage void handle_ov(void);
85 extern asmlinkage void handle_tr(void);
86 extern asmlinkage void handle_msa_fpe(void);
87 extern asmlinkage void handle_fpe(void);
88 extern asmlinkage void handle_ftlb(void);
89 extern asmlinkage void handle_msa(void);
90 extern asmlinkage void handle_mdmx(void);
91 extern asmlinkage void handle_watch(void);
92 extern asmlinkage void handle_mt(void);
93 extern asmlinkage void handle_dsp(void);
94 extern asmlinkage void handle_mcheck(void);
95 extern asmlinkage void handle_reserved(void);
96 extern void tlb_do_page_fault_0(void);
97
98 void (*board_be_init)(void);
99 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
100 void (*board_nmi_handler_setup)(void);
101 void (*board_ejtag_handler_setup)(void);
102 void (*board_bind_eic_interrupt)(int irq, int regset);
103 void (*board_ebase_setup)(void);
104 void(*board_cache_error_setup)(void);
105
106 static void show_raw_backtrace(unsigned long reg29)
107 {
108 unsigned long *sp = (unsigned long *)(reg29 & ~3);
109 unsigned long addr;
110
111 printk("Call Trace:");
112 #ifdef CONFIG_KALLSYMS
113 printk("\n");
114 #endif
115 while (!kstack_end(sp)) {
116 unsigned long __user *p =
117 (unsigned long __user *)(unsigned long)sp++;
118 if (__get_user(addr, p)) {
119 printk(" (Bad stack address)");
120 break;
121 }
122 if (__kernel_text_address(addr))
123 print_ip_sym(addr);
124 }
125 printk("\n");
126 }
127
128 #ifdef CONFIG_KALLSYMS
129 int raw_show_trace;
130 static int __init set_raw_show_trace(char *str)
131 {
132 raw_show_trace = 1;
133 return 1;
134 }
135 __setup("raw_show_trace", set_raw_show_trace);
136 #endif
137
138 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
139 {
140 unsigned long sp = regs->regs[29];
141 unsigned long ra = regs->regs[31];
142 unsigned long pc = regs->cp0_epc;
143
144 if (!task)
145 task = current;
146
147 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
148 show_raw_backtrace(sp);
149 return;
150 }
151 printk("Call Trace:\n");
152 do {
153 print_ip_sym(pc);
154 pc = unwind_stack(task, &sp, pc, &ra);
155 } while (pc);
156 printk("\n");
157 }
158
159 /*
160 * This routine abuses get_user()/put_user() to reference pointers
161 * with at least a bit of error checking ...
162 */
163 static void show_stacktrace(struct task_struct *task,
164 const struct pt_regs *regs)
165 {
166 const int field = 2 * sizeof(unsigned long);
167 long stackdata;
168 int i;
169 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
170
171 printk("Stack :");
172 i = 0;
173 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
174 if (i && ((i % (64 / field)) == 0))
175 printk("\n ");
176 if (i > 39) {
177 printk(" ...");
178 break;
179 }
180
181 if (__get_user(stackdata, sp++)) {
182 printk(" (Bad stack address)");
183 break;
184 }
185
186 printk(" %0*lx", field, stackdata);
187 i++;
188 }
189 printk("\n");
190 show_backtrace(task, regs);
191 }
192
193 void show_stack(struct task_struct *task, unsigned long *sp)
194 {
195 struct pt_regs regs;
196 mm_segment_t old_fs = get_fs();
197
198 regs.cp0_status = KSU_KERNEL;
199 if (sp) {
200 regs.regs[29] = (unsigned long)sp;
201 regs.regs[31] = 0;
202 regs.cp0_epc = 0;
203 } else {
204 if (task && task != current) {
205 regs.regs[29] = task->thread.reg29;
206 regs.regs[31] = 0;
207 regs.cp0_epc = task->thread.reg31;
208 #ifdef CONFIG_KGDB_KDB
209 } else if (atomic_read(&kgdb_active) != -1 &&
210 kdb_current_regs) {
211 memcpy(®s, kdb_current_regs, sizeof(regs));
212 #endif /* CONFIG_KGDB_KDB */
213 } else {
214 prepare_frametrace(®s);
215 }
216 }
217 /*
218 * show_stack() deals exclusively with kernel mode, so be sure to access
219 * the stack in the kernel (not user) address space.
220 */
221 set_fs(KERNEL_DS);
222 show_stacktrace(task, ®s);
223 set_fs(old_fs);
224 }
225
226 static void show_code(unsigned int __user *pc)
227 {
228 long i;
229 unsigned short __user *pc16 = NULL;
230
231 printk("\nCode:");
232
233 if ((unsigned long)pc & 1)
234 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
235 for(i = -3 ; i < 6 ; i++) {
236 unsigned int insn;
237 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
238 printk(" (Bad address in epc)\n");
239 break;
240 }
241 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
242 }
243 }
244
245 static void __show_regs(const struct pt_regs *regs)
246 {
247 const int field = 2 * sizeof(unsigned long);
248 unsigned int cause = regs->cp0_cause;
249 unsigned int exccode;
250 int i;
251
252 show_regs_print_info(KERN_DEFAULT);
253
254 /*
255 * Saved main processor registers
256 */
257 for (i = 0; i < 32; ) {
258 if ((i % 4) == 0)
259 printk("$%2d :", i);
260 if (i == 0)
261 printk(" %0*lx", field, 0UL);
262 else if (i == 26 || i == 27)
263 printk(" %*s", field, "");
264 else
265 printk(" %0*lx", field, regs->regs[i]);
266
267 i++;
268 if ((i % 4) == 0)
269 printk("\n");
270 }
271
272 #ifdef CONFIG_CPU_HAS_SMARTMIPS
273 printk("Acx : %0*lx\n", field, regs->acx);
274 #endif
275 printk("Hi : %0*lx\n", field, regs->hi);
276 printk("Lo : %0*lx\n", field, regs->lo);
277
278 /*
279 * Saved cp0 registers
280 */
281 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
282 (void *) regs->cp0_epc);
283 printk("ra : %0*lx %pS\n", field, regs->regs[31],
284 (void *) regs->regs[31]);
285
286 printk("Status: %08x ", (uint32_t) regs->cp0_status);
287
288 if (cpu_has_3kex) {
289 if (regs->cp0_status & ST0_KUO)
290 printk("KUo ");
291 if (regs->cp0_status & ST0_IEO)
292 printk("IEo ");
293 if (regs->cp0_status & ST0_KUP)
294 printk("KUp ");
295 if (regs->cp0_status & ST0_IEP)
296 printk("IEp ");
297 if (regs->cp0_status & ST0_KUC)
298 printk("KUc ");
299 if (regs->cp0_status & ST0_IEC)
300 printk("IEc ");
301 } else if (cpu_has_4kex) {
302 if (regs->cp0_status & ST0_KX)
303 printk("KX ");
304 if (regs->cp0_status & ST0_SX)
305 printk("SX ");
306 if (regs->cp0_status & ST0_UX)
307 printk("UX ");
308 switch (regs->cp0_status & ST0_KSU) {
309 case KSU_USER:
310 printk("USER ");
311 break;
312 case KSU_SUPERVISOR:
313 printk("SUPERVISOR ");
314 break;
315 case KSU_KERNEL:
316 printk("KERNEL ");
317 break;
318 default:
319 printk("BAD_MODE ");
320 break;
321 }
322 if (regs->cp0_status & ST0_ERL)
323 printk("ERL ");
324 if (regs->cp0_status & ST0_EXL)
325 printk("EXL ");
326 if (regs->cp0_status & ST0_IE)
327 printk("IE ");
328 }
329 printk("\n");
330
331 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
332 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
333
334 if (1 <= exccode && exccode <= 5)
335 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
336
337 printk("PrId : %08x (%s)\n", read_c0_prid(),
338 cpu_name_string());
339 }
340
341 /*
342 * FIXME: really the generic show_regs should take a const pointer argument.
343 */
344 void show_regs(struct pt_regs *regs)
345 {
346 __show_regs((struct pt_regs *)regs);
347 dump_stack();
348 }
349
350 void show_registers(struct pt_regs *regs)
351 {
352 const int field = 2 * sizeof(unsigned long);
353 mm_segment_t old_fs = get_fs();
354
355 __show_regs(regs);
356 print_modules();
357 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
358 current->comm, current->pid, current_thread_info(), current,
359 field, current_thread_info()->tp_value);
360 if (cpu_has_userlocal) {
361 unsigned long tls;
362
363 tls = read_c0_userlocal();
364 if (tls != current_thread_info()->tp_value)
365 printk("*HwTLS: %0*lx\n", field, tls);
366 }
367
368 if (!user_mode(regs))
369 /* Necessary for getting the correct stack content */
370 set_fs(KERNEL_DS);
371 show_stacktrace(current, regs);
372 show_code((unsigned int __user *) regs->cp0_epc);
373 printk("\n");
374 set_fs(old_fs);
375 }
376
377 static DEFINE_RAW_SPINLOCK(die_lock);
378
379 void __noreturn die(const char *str, struct pt_regs *regs)
380 {
381 static int die_counter;
382 int sig = SIGSEGV;
383
384 oops_enter();
385
386 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
387 SIGSEGV) == NOTIFY_STOP)
388 sig = 0;
389
390 console_verbose();
391 raw_spin_lock_irq(&die_lock);
392 bust_spinlocks(1);
393
394 printk("%s[#%d]:\n", str, ++die_counter);
395 show_registers(regs);
396 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
397 raw_spin_unlock_irq(&die_lock);
398
399 oops_exit();
400
401 if (in_interrupt())
402 panic("Fatal exception in interrupt");
403
404 if (panic_on_oops) {
405 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
406 ssleep(5);
407 panic("Fatal exception");
408 }
409
410 if (regs && kexec_should_crash(current))
411 crash_kexec(regs);
412
413 do_exit(sig);
414 }
415
416 extern struct exception_table_entry __start___dbe_table[];
417 extern struct exception_table_entry __stop___dbe_table[];
418
419 __asm__(
420 " .section __dbe_table, \"a\"\n"
421 " .previous \n");
422
423 /* Given an address, look for it in the exception tables. */
424 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
425 {
426 const struct exception_table_entry *e;
427
428 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
429 if (!e)
430 e = search_module_dbetables(addr);
431 return e;
432 }
433
434 asmlinkage void do_be(struct pt_regs *regs)
435 {
436 const int field = 2 * sizeof(unsigned long);
437 const struct exception_table_entry *fixup = NULL;
438 int data = regs->cp0_cause & 4;
439 int action = MIPS_BE_FATAL;
440 enum ctx_state prev_state;
441
442 prev_state = exception_enter();
443 /* XXX For now. Fixme, this searches the wrong table ... */
444 if (data && !user_mode(regs))
445 fixup = search_dbe_tables(exception_epc(regs));
446
447 if (fixup)
448 action = MIPS_BE_FIXUP;
449
450 if (board_be_handler)
451 action = board_be_handler(regs, fixup != NULL);
452
453 switch (action) {
454 case MIPS_BE_DISCARD:
455 goto out;
456 case MIPS_BE_FIXUP:
457 if (fixup) {
458 regs->cp0_epc = fixup->nextinsn;
459 goto out;
460 }
461 break;
462 default:
463 break;
464 }
465
466 /*
467 * Assume it would be too dangerous to continue ...
468 */
469 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
470 data ? "Data" : "Instruction",
471 field, regs->cp0_epc, field, regs->regs[31]);
472 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
473 SIGBUS) == NOTIFY_STOP)
474 goto out;
475
476 die_if_kernel("Oops", regs);
477 force_sig(SIGBUS, current);
478
479 out:
480 exception_exit(prev_state);
481 }
482
483 /*
484 * ll/sc, rdhwr, sync emulation
485 */
486
487 #define OPCODE 0xfc000000
488 #define BASE 0x03e00000
489 #define RT 0x001f0000
490 #define OFFSET 0x0000ffff
491 #define LL 0xc0000000
492 #define SC 0xe0000000
493 #define SPEC0 0x00000000
494 #define SPEC3 0x7c000000
495 #define RD 0x0000f800
496 #define FUNC 0x0000003f
497 #define SYNC 0x0000000f
498 #define RDHWR 0x0000003b
499
500 /* microMIPS definitions */
501 #define MM_POOL32A_FUNC 0xfc00ffff
502 #define MM_RDHWR 0x00006b3c
503 #define MM_RS 0x001f0000
504 #define MM_RT 0x03e00000
505
506 /*
507 * The ll_bit is cleared by r*_switch.S
508 */
509
510 unsigned int ll_bit;
511 struct task_struct *ll_task;
512
513 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
514 {
515 unsigned long value, __user *vaddr;
516 long offset;
517
518 /*
519 * analyse the ll instruction that just caused a ri exception
520 * and put the referenced address to addr.
521 */
522
523 /* sign extend offset */
524 offset = opcode & OFFSET;
525 offset <<= 16;
526 offset >>= 16;
527
528 vaddr = (unsigned long __user *)
529 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
530
531 if ((unsigned long)vaddr & 3)
532 return SIGBUS;
533 if (get_user(value, vaddr))
534 return SIGSEGV;
535
536 preempt_disable();
537
538 if (ll_task == NULL || ll_task == current) {
539 ll_bit = 1;
540 } else {
541 ll_bit = 0;
542 }
543 ll_task = current;
544
545 preempt_enable();
546
547 regs->regs[(opcode & RT) >> 16] = value;
548
549 return 0;
550 }
551
552 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
553 {
554 unsigned long __user *vaddr;
555 unsigned long reg;
556 long offset;
557
558 /*
559 * analyse the sc instruction that just caused a ri exception
560 * and put the referenced address to addr.
561 */
562
563 /* sign extend offset */
564 offset = opcode & OFFSET;
565 offset <<= 16;
566 offset >>= 16;
567
568 vaddr = (unsigned long __user *)
569 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
570 reg = (opcode & RT) >> 16;
571
572 if ((unsigned long)vaddr & 3)
573 return SIGBUS;
574
575 preempt_disable();
576
577 if (ll_bit == 0 || ll_task != current) {
578 regs->regs[reg] = 0;
579 preempt_enable();
580 return 0;
581 }
582
583 preempt_enable();
584
585 if (put_user(regs->regs[reg], vaddr))
586 return SIGSEGV;
587
588 regs->regs[reg] = 1;
589
590 return 0;
591 }
592
593 /*
594 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
595 * opcodes are supposed to result in coprocessor unusable exceptions if
596 * executed on ll/sc-less processors. That's the theory. In practice a
597 * few processors such as NEC's VR4100 throw reserved instruction exceptions
598 * instead, so we're doing the emulation thing in both exception handlers.
599 */
600 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
601 {
602 if ((opcode & OPCODE) == LL) {
603 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
604 1, regs, 0);
605 return simulate_ll(regs, opcode);
606 }
607 if ((opcode & OPCODE) == SC) {
608 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
609 1, regs, 0);
610 return simulate_sc(regs, opcode);
611 }
612
613 return -1; /* Must be something else ... */
614 }
615
616 /*
617 * Simulate trapping 'rdhwr' instructions to provide user accessible
618 * registers not implemented in hardware.
619 */
620 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
621 {
622 struct thread_info *ti = task_thread_info(current);
623
624 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
625 1, regs, 0);
626 switch (rd) {
627 case 0: /* CPU number */
628 regs->regs[rt] = smp_processor_id();
629 return 0;
630 case 1: /* SYNCI length */
631 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
632 current_cpu_data.icache.linesz);
633 return 0;
634 case 2: /* Read count register */
635 regs->regs[rt] = read_c0_count();
636 return 0;
637 case 3: /* Count register resolution */
638 switch (current_cpu_type()) {
639 case CPU_20KC:
640 case CPU_25KF:
641 regs->regs[rt] = 1;
642 break;
643 default:
644 regs->regs[rt] = 2;
645 }
646 return 0;
647 case 29:
648 regs->regs[rt] = ti->tp_value;
649 return 0;
650 default:
651 return -1;
652 }
653 }
654
655 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
656 {
657 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
658 int rd = (opcode & RD) >> 11;
659 int rt = (opcode & RT) >> 16;
660
661 simulate_rdhwr(regs, rd, rt);
662 return 0;
663 }
664
665 /* Not ours. */
666 return -1;
667 }
668
669 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
670 {
671 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
672 int rd = (opcode & MM_RS) >> 16;
673 int rt = (opcode & MM_RT) >> 21;
674 simulate_rdhwr(regs, rd, rt);
675 return 0;
676 }
677
678 /* Not ours. */
679 return -1;
680 }
681
682 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
683 {
684 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
685 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
686 1, regs, 0);
687 return 0;
688 }
689
690 return -1; /* Must be something else ... */
691 }
692
693 asmlinkage void do_ov(struct pt_regs *regs)
694 {
695 enum ctx_state prev_state;
696 siginfo_t info = {
697 .si_signo = SIGFPE,
698 .si_code = FPE_INTOVF,
699 .si_addr = (void __user *)regs->cp0_epc,
700 };
701
702 prev_state = exception_enter();
703 die_if_kernel("Integer overflow", regs);
704
705 force_sig_info(SIGFPE, &info, current);
706 exception_exit(prev_state);
707 }
708
709 /*
710 * Send SIGFPE according to FCSR Cause bits, which must have already
711 * been masked against Enable bits. This is impotant as Inexact can
712 * happen together with Overflow or Underflow, and `ptrace' can set
713 * any bits.
714 */
715 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
716 struct task_struct *tsk)
717 {
718 struct siginfo si = { .si_addr = fault_addr, .si_signo = SIGFPE };
719
720 if (fcr31 & FPU_CSR_INV_X)
721 si.si_code = FPE_FLTINV;
722 else if (fcr31 & FPU_CSR_DIV_X)
723 si.si_code = FPE_FLTDIV;
724 else if (fcr31 & FPU_CSR_OVF_X)
725 si.si_code = FPE_FLTOVF;
726 else if (fcr31 & FPU_CSR_UDF_X)
727 si.si_code = FPE_FLTUND;
728 else if (fcr31 & FPU_CSR_INE_X)
729 si.si_code = FPE_FLTRES;
730 else
731 si.si_code = __SI_FAULT;
732 force_sig_info(SIGFPE, &si, tsk);
733 }
734
735 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
736 {
737 struct siginfo si = { 0 };
738
739 switch (sig) {
740 case 0:
741 return 0;
742
743 case SIGFPE:
744 force_fcr31_sig(fcr31, fault_addr, current);
745 return 1;
746
747 case SIGBUS:
748 si.si_addr = fault_addr;
749 si.si_signo = sig;
750 si.si_code = BUS_ADRERR;
751 force_sig_info(sig, &si, current);
752 return 1;
753
754 case SIGSEGV:
755 si.si_addr = fault_addr;
756 si.si_signo = sig;
757 down_read(¤t->mm->mmap_sem);
758 if (find_vma(current->mm, (unsigned long)fault_addr))
759 si.si_code = SEGV_ACCERR;
760 else
761 si.si_code = SEGV_MAPERR;
762 up_read(¤t->mm->mmap_sem);
763 force_sig_info(sig, &si, current);
764 return 1;
765
766 default:
767 force_sig(sig, current);
768 return 1;
769 }
770 }
771
772 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
773 unsigned long old_epc, unsigned long old_ra)
774 {
775 union mips_instruction inst = { .word = opcode };
776 void __user *fault_addr;
777 unsigned long fcr31;
778 int sig;
779
780 /* If it's obviously not an FP instruction, skip it */
781 switch (inst.i_format.opcode) {
782 case cop1_op:
783 case cop1x_op:
784 case lwc1_op:
785 case ldc1_op:
786 case swc1_op:
787 case sdc1_op:
788 break;
789
790 default:
791 return -1;
792 }
793
794 /*
795 * do_ri skipped over the instruction via compute_return_epc, undo
796 * that for the FPU emulator.
797 */
798 regs->cp0_epc = old_epc;
799 regs->regs[31] = old_ra;
800
801 /* Save the FP context to struct thread_struct */
802 lose_fpu(1);
803
804 /* Run the emulator */
805 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
806 &fault_addr);
807
808 /*
809 * We can't allow the emulated instruction to leave any
810 * enabled Cause bits set in $fcr31.
811 */
812 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
813 current->thread.fpu.fcr31 &= ~fcr31;
814
815 /* Restore the hardware register state */
816 own_fpu(1);
817
818 /* Send a signal if required. */
819 process_fpemu_return(sig, fault_addr, fcr31);
820
821 return 0;
822 }
823
824 /*
825 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
826 */
827 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
828 {
829 enum ctx_state prev_state;
830 void __user *fault_addr;
831 int sig;
832
833 prev_state = exception_enter();
834 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
835 SIGFPE) == NOTIFY_STOP)
836 goto out;
837
838 /* Clear FCSR.Cause before enabling interrupts */
839 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
840 local_irq_enable();
841
842 die_if_kernel("FP exception in kernel code", regs);
843
844 if (fcr31 & FPU_CSR_UNI_X) {
845 /*
846 * Unimplemented operation exception. If we've got the full
847 * software emulator on-board, let's use it...
848 *
849 * Force FPU to dump state into task/thread context. We're
850 * moving a lot of data here for what is probably a single
851 * instruction, but the alternative is to pre-decode the FP
852 * register operands before invoking the emulator, which seems
853 * a bit extreme for what should be an infrequent event.
854 */
855 /* Ensure 'resume' not overwrite saved fp context again. */
856 lose_fpu(1);
857
858 /* Run the emulator */
859 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
860 &fault_addr);
861
862 /*
863 * We can't allow the emulated instruction to leave any
864 * enabled Cause bits set in $fcr31.
865 */
866 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
867 current->thread.fpu.fcr31 &= ~fcr31;
868
869 /* Restore the hardware register state */
870 own_fpu(1); /* Using the FPU again. */
871 } else {
872 sig = SIGFPE;
873 fault_addr = (void __user *) regs->cp0_epc;
874 }
875
876 /* Send a signal if required. */
877 process_fpemu_return(sig, fault_addr, fcr31);
878
879 out:
880 exception_exit(prev_state);
881 }
882
883 void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
884 const char *str)
885 {
886 siginfo_t info = { 0 };
887 char b[40];
888
889 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
890 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
891 SIGTRAP) == NOTIFY_STOP)
892 return;
893 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
894
895 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
896 SIGTRAP) == NOTIFY_STOP)
897 return;
898
899 /*
900 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
901 * insns, even for trap and break codes that indicate arithmetic
902 * failures. Weird ...
903 * But should we continue the brokenness??? --macro
904 */
905 switch (code) {
906 case BRK_OVERFLOW:
907 case BRK_DIVZERO:
908 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
909 die_if_kernel(b, regs);
910 if (code == BRK_DIVZERO)
911 info.si_code = FPE_INTDIV;
912 else
913 info.si_code = FPE_INTOVF;
914 info.si_signo = SIGFPE;
915 info.si_addr = (void __user *) regs->cp0_epc;
916 force_sig_info(SIGFPE, &info, current);
917 break;
918 case BRK_BUG:
919 die_if_kernel("Kernel bug detected", regs);
920 force_sig(SIGTRAP, current);
921 break;
922 case BRK_MEMU:
923 /*
924 * This breakpoint code is used by the FPU emulator to retake
925 * control of the CPU after executing the instruction from the
926 * delay slot of an emulated branch.
927 *
928 * Terminate if exception was recognized as a delay slot return
929 * otherwise handle as normal.
930 */
931 if (do_dsemulret(regs))
932 return;
933
934 die_if_kernel("Math emu break/trap", regs);
935 force_sig(SIGTRAP, current);
936 break;
937 default:
938 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
939 die_if_kernel(b, regs);
940 force_sig(SIGTRAP, current);
941 }
942 }
943
944 asmlinkage void do_bp(struct pt_regs *regs)
945 {
946 unsigned long epc = msk_isa16_mode(exception_epc(regs));
947 unsigned int opcode, bcode;
948 enum ctx_state prev_state;
949 mm_segment_t seg;
950
951 seg = get_fs();
952 if (!user_mode(regs))
953 set_fs(KERNEL_DS);
954
955 prev_state = exception_enter();
956 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
957 if (get_isa16_mode(regs->cp0_epc)) {
958 u16 instr[2];
959
960 if (__get_user(instr[0], (u16 __user *)epc))
961 goto out_sigsegv;
962
963 if (!cpu_has_mmips) {
964 /* MIPS16e mode */
965 bcode = (instr[0] >> 5) & 0x3f;
966 } else if (mm_insn_16bit(instr[0])) {
967 /* 16-bit microMIPS BREAK */
968 bcode = instr[0] & 0xf;
969 } else {
970 /* 32-bit microMIPS BREAK */
971 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
972 goto out_sigsegv;
973 opcode = (instr[0] << 16) | instr[1];
974 bcode = (opcode >> 6) & ((1 << 20) - 1);
975 }
976 } else {
977 if (__get_user(opcode, (unsigned int __user *)epc))
978 goto out_sigsegv;
979 bcode = (opcode >> 6) & ((1 << 20) - 1);
980 }
981
982 /*
983 * There is the ancient bug in the MIPS assemblers that the break
984 * code starts left to bit 16 instead to bit 6 in the opcode.
985 * Gas is bug-compatible, but not always, grrr...
986 * We handle both cases with a simple heuristics. --macro
987 */
988 if (bcode >= (1 << 10))
989 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
990
991 /*
992 * notify the kprobe handlers, if instruction is likely to
993 * pertain to them.
994 */
995 switch (bcode) {
996 case BRK_UPROBE:
997 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
998 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
999 goto out;
1000 else
1001 break;
1002 case BRK_UPROBE_XOL:
1003 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1004 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1005 goto out;
1006 else
1007 break;
1008 case BRK_KPROBE_BP:
1009 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1010 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1011 goto out;
1012 else
1013 break;
1014 case BRK_KPROBE_SSTEPBP:
1015 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1016 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1017 goto out;
1018 else
1019 break;
1020 default:
1021 break;
1022 }
1023
1024 do_trap_or_bp(regs, bcode, "Break");
1025
1026 out:
1027 set_fs(seg);
1028 exception_exit(prev_state);
1029 return;
1030
1031 out_sigsegv:
1032 force_sig(SIGSEGV, current);
1033 goto out;
1034 }
1035
1036 asmlinkage void do_tr(struct pt_regs *regs)
1037 {
1038 u32 opcode, tcode = 0;
1039 enum ctx_state prev_state;
1040 u16 instr[2];
1041 mm_segment_t seg;
1042 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1043
1044 seg = get_fs();
1045 if (!user_mode(regs))
1046 set_fs(get_ds());
1047
1048 prev_state = exception_enter();
1049 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1050 if (get_isa16_mode(regs->cp0_epc)) {
1051 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1052 __get_user(instr[1], (u16 __user *)(epc + 2)))
1053 goto out_sigsegv;
1054 opcode = (instr[0] << 16) | instr[1];
1055 /* Immediate versions don't provide a code. */
1056 if (!(opcode & OPCODE))
1057 tcode = (opcode >> 12) & ((1 << 4) - 1);
1058 } else {
1059 if (__get_user(opcode, (u32 __user *)epc))
1060 goto out_sigsegv;
1061 /* Immediate versions don't provide a code. */
1062 if (!(opcode & OPCODE))
1063 tcode = (opcode >> 6) & ((1 << 10) - 1);
1064 }
1065
1066 do_trap_or_bp(regs, tcode, "Trap");
1067
1068 out:
1069 set_fs(seg);
1070 exception_exit(prev_state);
1071 return;
1072
1073 out_sigsegv:
1074 force_sig(SIGSEGV, current);
1075 goto out;
1076 }
1077
1078 asmlinkage void do_ri(struct pt_regs *regs)
1079 {
1080 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1081 unsigned long old_epc = regs->cp0_epc;
1082 unsigned long old31 = regs->regs[31];
1083 enum ctx_state prev_state;
1084 unsigned int opcode = 0;
1085 int status = -1;
1086
1087 /*
1088 * Avoid any kernel code. Just emulate the R2 instruction
1089 * as quickly as possible.
1090 */
1091 if (mipsr2_emulation && cpu_has_mips_r6 &&
1092 likely(user_mode(regs)) &&
1093 likely(get_user(opcode, epc) >= 0)) {
1094 unsigned long fcr31 = 0;
1095
1096 status = mipsr2_decoder(regs, opcode, &fcr31);
1097 switch (status) {
1098 case 0:
1099 case SIGEMT:
1100 task_thread_info(current)->r2_emul_return = 1;
1101 return;
1102 case SIGILL:
1103 goto no_r2_instr;
1104 default:
1105 process_fpemu_return(status,
1106 ¤t->thread.cp0_baduaddr,
1107 fcr31);
1108 task_thread_info(current)->r2_emul_return = 1;
1109 return;
1110 }
1111 }
1112
1113 no_r2_instr:
1114
1115 prev_state = exception_enter();
1116 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1117
1118 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1119 SIGILL) == NOTIFY_STOP)
1120 goto out;
1121
1122 die_if_kernel("Reserved instruction in kernel code", regs);
1123
1124 if (unlikely(compute_return_epc(regs) < 0))
1125 goto out;
1126
1127 if (get_isa16_mode(regs->cp0_epc)) {
1128 unsigned short mmop[2] = { 0 };
1129
1130 if (unlikely(get_user(mmop[0], epc) < 0))
1131 status = SIGSEGV;
1132 if (unlikely(get_user(mmop[1], epc) < 0))
1133 status = SIGSEGV;
1134 opcode = (mmop[0] << 16) | mmop[1];
1135
1136 if (status < 0)
1137 status = simulate_rdhwr_mm(regs, opcode);
1138 } else {
1139 if (unlikely(get_user(opcode, epc) < 0))
1140 status = SIGSEGV;
1141
1142 if (!cpu_has_llsc && status < 0)
1143 status = simulate_llsc(regs, opcode);
1144
1145 if (status < 0)
1146 status = simulate_rdhwr_normal(regs, opcode);
1147
1148 if (status < 0)
1149 status = simulate_sync(regs, opcode);
1150
1151 if (status < 0)
1152 status = simulate_fp(regs, opcode, old_epc, old31);
1153 }
1154
1155 if (status < 0)
1156 status = SIGILL;
1157
1158 if (unlikely(status > 0)) {
1159 regs->cp0_epc = old_epc; /* Undo skip-over. */
1160 regs->regs[31] = old31;
1161 force_sig(status, current);
1162 }
1163
1164 out:
1165 exception_exit(prev_state);
1166 }
1167
1168 /*
1169 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1170 * emulated more than some threshold number of instructions, force migration to
1171 * a "CPU" that has FP support.
1172 */
1173 static void mt_ase_fp_affinity(void)
1174 {
1175 #ifdef CONFIG_MIPS_MT_FPAFF
1176 if (mt_fpemul_threshold > 0 &&
1177 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1178 /*
1179 * If there's no FPU present, or if the application has already
1180 * restricted the allowed set to exclude any CPUs with FPUs,
1181 * we'll skip the procedure.
1182 */
1183 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1184 cpumask_t tmask;
1185
1186 current->thread.user_cpus_allowed
1187 = current->cpus_allowed;
1188 cpumask_and(&tmask, ¤t->cpus_allowed,
1189 &mt_fpu_cpumask);
1190 set_cpus_allowed_ptr(current, &tmask);
1191 set_thread_flag(TIF_FPUBOUND);
1192 }
1193 }
1194 #endif /* CONFIG_MIPS_MT_FPAFF */
1195 }
1196
1197 /*
1198 * No lock; only written during early bootup by CPU 0.
1199 */
1200 static RAW_NOTIFIER_HEAD(cu2_chain);
1201
1202 int __ref register_cu2_notifier(struct notifier_block *nb)
1203 {
1204 return raw_notifier_chain_register(&cu2_chain, nb);
1205 }
1206
1207 int cu2_notifier_call_chain(unsigned long val, void *v)
1208 {
1209 return raw_notifier_call_chain(&cu2_chain, val, v);
1210 }
1211
1212 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1213 void *data)
1214 {
1215 struct pt_regs *regs = data;
1216
1217 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1218 "instruction", regs);
1219 force_sig(SIGILL, current);
1220
1221 return NOTIFY_OK;
1222 }
1223
1224 static int wait_on_fp_mode_switch(atomic_t *p)
1225 {
1226 /*
1227 * The FP mode for this task is currently being switched. That may
1228 * involve modifications to the format of this tasks FP context which
1229 * make it unsafe to proceed with execution for the moment. Instead,
1230 * schedule some other task.
1231 */
1232 schedule();
1233 return 0;
1234 }
1235
1236 static int enable_restore_fp_context(int msa)
1237 {
1238 int err, was_fpu_owner, prior_msa;
1239
1240 /*
1241 * If an FP mode switch is currently underway, wait for it to
1242 * complete before proceeding.
1243 */
1244 wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
1245 wait_on_fp_mode_switch, TASK_KILLABLE);
1246
1247 if (!used_math()) {
1248 /* First time FP context user. */
1249 preempt_disable();
1250 err = init_fpu();
1251 if (msa && !err) {
1252 enable_msa();
1253 init_msa_upper();
1254 set_thread_flag(TIF_USEDMSA);
1255 set_thread_flag(TIF_MSA_CTX_LIVE);
1256 }
1257 preempt_enable();
1258 if (!err)
1259 set_used_math();
1260 return err;
1261 }
1262
1263 /*
1264 * This task has formerly used the FP context.
1265 *
1266 * If this thread has no live MSA vector context then we can simply
1267 * restore the scalar FP context. If it has live MSA vector context
1268 * (that is, it has or may have used MSA since last performing a
1269 * function call) then we'll need to restore the vector context. This
1270 * applies even if we're currently only executing a scalar FP
1271 * instruction. This is because if we were to later execute an MSA
1272 * instruction then we'd either have to:
1273 *
1274 * - Restore the vector context & clobber any registers modified by
1275 * scalar FP instructions between now & then.
1276 *
1277 * or
1278 *
1279 * - Not restore the vector context & lose the most significant bits
1280 * of all vector registers.
1281 *
1282 * Neither of those options is acceptable. We cannot restore the least
1283 * significant bits of the registers now & only restore the most
1284 * significant bits later because the most significant bits of any
1285 * vector registers whose aliased FP register is modified now will have
1286 * been zeroed. We'd have no way to know that when restoring the vector
1287 * context & thus may load an outdated value for the most significant
1288 * bits of a vector register.
1289 */
1290 if (!msa && !thread_msa_context_live())
1291 return own_fpu(1);
1292
1293 /*
1294 * This task is using or has previously used MSA. Thus we require
1295 * that Status.FR == 1.
1296 */
1297 preempt_disable();
1298 was_fpu_owner = is_fpu_owner();
1299 err = own_fpu_inatomic(0);
1300 if (err)
1301 goto out;
1302
1303 enable_msa();
1304 write_msa_csr(current->thread.fpu.msacsr);
1305 set_thread_flag(TIF_USEDMSA);
1306
1307 /*
1308 * If this is the first time that the task is using MSA and it has
1309 * previously used scalar FP in this time slice then we already nave
1310 * FP context which we shouldn't clobber. We do however need to clear
1311 * the upper 64b of each vector register so that this task has no
1312 * opportunity to see data left behind by another.
1313 */
1314 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1315 if (!prior_msa && was_fpu_owner) {
1316 init_msa_upper();
1317
1318 goto out;
1319 }
1320
1321 if (!prior_msa) {
1322 /*
1323 * Restore the least significant 64b of each vector register
1324 * from the existing scalar FP context.
1325 */
1326 _restore_fp(current);
1327
1328 /*
1329 * The task has not formerly used MSA, so clear the upper 64b
1330 * of each vector register such that it cannot see data left
1331 * behind by another task.
1332 */
1333 init_msa_upper();
1334 } else {
1335 /* We need to restore the vector context. */
1336 restore_msa(current);
1337
1338 /* Restore the scalar FP control & status register */
1339 if (!was_fpu_owner)
1340 write_32bit_cp1_register(CP1_STATUS,
1341 current->thread.fpu.fcr31);
1342 }
1343
1344 out:
1345 preempt_enable();
1346
1347 return 0;
1348 }
1349
1350 asmlinkage void do_cpu(struct pt_regs *regs)
1351 {
1352 enum ctx_state prev_state;
1353 unsigned int __user *epc;
1354 unsigned long old_epc, old31;
1355 void __user *fault_addr;
1356 unsigned int opcode;
1357 unsigned long fcr31;
1358 unsigned int cpid;
1359 int status, err;
1360 unsigned long __maybe_unused flags;
1361 int sig;
1362
1363 prev_state = exception_enter();
1364 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1365
1366 if (cpid != 2)
1367 die_if_kernel("do_cpu invoked from kernel context!", regs);
1368
1369 switch (cpid) {
1370 case 0:
1371 epc = (unsigned int __user *)exception_epc(regs);
1372 old_epc = regs->cp0_epc;
1373 old31 = regs->regs[31];
1374 opcode = 0;
1375 status = -1;
1376
1377 if (unlikely(compute_return_epc(regs) < 0))
1378 break;
1379
1380 if (get_isa16_mode(regs->cp0_epc)) {
1381 unsigned short mmop[2] = { 0 };
1382
1383 if (unlikely(get_user(mmop[0], epc) < 0))
1384 status = SIGSEGV;
1385 if (unlikely(get_user(mmop[1], epc) < 0))
1386 status = SIGSEGV;
1387 opcode = (mmop[0] << 16) | mmop[1];
1388
1389 if (status < 0)
1390 status = simulate_rdhwr_mm(regs, opcode);
1391 } else {
1392 if (unlikely(get_user(opcode, epc) < 0))
1393 status = SIGSEGV;
1394
1395 if (!cpu_has_llsc && status < 0)
1396 status = simulate_llsc(regs, opcode);
1397
1398 if (status < 0)
1399 status = simulate_rdhwr_normal(regs, opcode);
1400 }
1401
1402 if (status < 0)
1403 status = SIGILL;
1404
1405 if (unlikely(status > 0)) {
1406 regs->cp0_epc = old_epc; /* Undo skip-over. */
1407 regs->regs[31] = old31;
1408 force_sig(status, current);
1409 }
1410
1411 break;
1412
1413 case 3:
1414 /*
1415 * The COP3 opcode space and consequently the CP0.Status.CU3
1416 * bit and the CP0.Cause.CE=3 encoding have been removed as
1417 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1418 * up the space has been reused for COP1X instructions, that
1419 * are enabled by the CP0.Status.CU1 bit and consequently
1420 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1421 * exceptions. Some FPU-less processors that implement one
1422 * of these ISAs however use this code erroneously for COP1X
1423 * instructions. Therefore we redirect this trap to the FP
1424 * emulator too.
1425 */
1426 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1427 force_sig(SIGILL, current);
1428 break;
1429 }
1430 /* Fall through. */
1431
1432 case 1:
1433 err = enable_restore_fp_context(0);
1434
1435 if (raw_cpu_has_fpu && !err)
1436 break;
1437
1438 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1439 &fault_addr);
1440
1441 /*
1442 * We can't allow the emulated instruction to leave
1443 * any enabled Cause bits set in $fcr31.
1444 */
1445 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1446 current->thread.fpu.fcr31 &= ~fcr31;
1447
1448 /* Send a signal if required. */
1449 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1450 mt_ase_fp_affinity();
1451
1452 break;
1453
1454 case 2:
1455 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1456 break;
1457 }
1458
1459 exception_exit(prev_state);
1460 }
1461
1462 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1463 {
1464 enum ctx_state prev_state;
1465
1466 prev_state = exception_enter();
1467 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1468 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1469 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1470 goto out;
1471
1472 /* Clear MSACSR.Cause before enabling interrupts */
1473 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1474 local_irq_enable();
1475
1476 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1477 force_sig(SIGFPE, current);
1478 out:
1479 exception_exit(prev_state);
1480 }
1481
1482 asmlinkage void do_msa(struct pt_regs *regs)
1483 {
1484 enum ctx_state prev_state;
1485 int err;
1486
1487 prev_state = exception_enter();
1488
1489 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1490 force_sig(SIGILL, current);
1491 goto out;
1492 }
1493
1494 die_if_kernel("do_msa invoked from kernel context!", regs);
1495
1496 err = enable_restore_fp_context(1);
1497 if (err)
1498 force_sig(SIGILL, current);
1499 out:
1500 exception_exit(prev_state);
1501 }
1502
1503 asmlinkage void do_mdmx(struct pt_regs *regs)
1504 {
1505 enum ctx_state prev_state;
1506
1507 prev_state = exception_enter();
1508 force_sig(SIGILL, current);
1509 exception_exit(prev_state);
1510 }
1511
1512 /*
1513 * Called with interrupts disabled.
1514 */
1515 asmlinkage void do_watch(struct pt_regs *regs)
1516 {
1517 enum ctx_state prev_state;
1518 u32 cause;
1519
1520 prev_state = exception_enter();
1521 /*
1522 * Clear WP (bit 22) bit of cause register so we don't loop
1523 * forever.
1524 */
1525 cause = read_c0_cause();
1526 cause &= ~(1 << 22);
1527 write_c0_cause(cause);
1528
1529 /*
1530 * If the current thread has the watch registers loaded, save
1531 * their values and send SIGTRAP. Otherwise another thread
1532 * left the registers set, clear them and continue.
1533 */
1534 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1535 mips_read_watch_registers();
1536 local_irq_enable();
1537 force_sig(SIGTRAP, current);
1538 } else {
1539 mips_clear_watch_registers();
1540 local_irq_enable();
1541 }
1542 exception_exit(prev_state);
1543 }
1544
1545 asmlinkage void do_mcheck(struct pt_regs *regs)
1546 {
1547 int multi_match = regs->cp0_status & ST0_TS;
1548 enum ctx_state prev_state;
1549 mm_segment_t old_fs = get_fs();
1550
1551 prev_state = exception_enter();
1552 show_regs(regs);
1553
1554 if (multi_match) {
1555 dump_tlb_regs();
1556 pr_info("\n");
1557 dump_tlb_all();
1558 }
1559
1560 if (!user_mode(regs))
1561 set_fs(KERNEL_DS);
1562
1563 show_code((unsigned int __user *) regs->cp0_epc);
1564
1565 set_fs(old_fs);
1566
1567 /*
1568 * Some chips may have other causes of machine check (e.g. SB1
1569 * graduation timer)
1570 */
1571 panic("Caught Machine Check exception - %scaused by multiple "
1572 "matching entries in the TLB.",
1573 (multi_match) ? "" : "not ");
1574 }
1575
1576 asmlinkage void do_mt(struct pt_regs *regs)
1577 {
1578 int subcode;
1579
1580 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1581 >> VPECONTROL_EXCPT_SHIFT;
1582 switch (subcode) {
1583 case 0:
1584 printk(KERN_DEBUG "Thread Underflow\n");
1585 break;
1586 case 1:
1587 printk(KERN_DEBUG "Thread Overflow\n");
1588 break;
1589 case 2:
1590 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1591 break;
1592 case 3:
1593 printk(KERN_DEBUG "Gating Storage Exception\n");
1594 break;
1595 case 4:
1596 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1597 break;
1598 case 5:
1599 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1600 break;
1601 default:
1602 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1603 subcode);
1604 break;
1605 }
1606 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1607
1608 force_sig(SIGILL, current);
1609 }
1610
1611
1612 asmlinkage void do_dsp(struct pt_regs *regs)
1613 {
1614 if (cpu_has_dsp)
1615 panic("Unexpected DSP exception");
1616
1617 force_sig(SIGILL, current);
1618 }
1619
1620 asmlinkage void do_reserved(struct pt_regs *regs)
1621 {
1622 /*
1623 * Game over - no way to handle this if it ever occurs. Most probably
1624 * caused by a new unknown cpu type or after another deadly
1625 * hard/software error.
1626 */
1627 show_regs(regs);
1628 panic("Caught reserved exception %ld - should not happen.",
1629 (regs->cp0_cause & 0x7f) >> 2);
1630 }
1631
1632 static int __initdata l1parity = 1;
1633 static int __init nol1parity(char *s)
1634 {
1635 l1parity = 0;
1636 return 1;
1637 }
1638 __setup("nol1par", nol1parity);
1639 static int __initdata l2parity = 1;
1640 static int __init nol2parity(char *s)
1641 {
1642 l2parity = 0;
1643 return 1;
1644 }
1645 __setup("nol2par", nol2parity);
1646
1647 /*
1648 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1649 * it different ways.
1650 */
1651 static inline void parity_protection_init(void)
1652 {
1653 switch (current_cpu_type()) {
1654 case CPU_24K:
1655 case CPU_34K:
1656 case CPU_74K:
1657 case CPU_1004K:
1658 case CPU_1074K:
1659 case CPU_INTERAPTIV:
1660 case CPU_PROAPTIV:
1661 case CPU_P5600:
1662 case CPU_QEMU_GENERIC:
1663 case CPU_I6400:
1664 {
1665 #define ERRCTL_PE 0x80000000
1666 #define ERRCTL_L2P 0x00800000
1667 unsigned long errctl;
1668 unsigned int l1parity_present, l2parity_present;
1669
1670 errctl = read_c0_ecc();
1671 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1672
1673 /* probe L1 parity support */
1674 write_c0_ecc(errctl | ERRCTL_PE);
1675 back_to_back_c0_hazard();
1676 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1677
1678 /* probe L2 parity support */
1679 write_c0_ecc(errctl|ERRCTL_L2P);
1680 back_to_back_c0_hazard();
1681 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1682
1683 if (l1parity_present && l2parity_present) {
1684 if (l1parity)
1685 errctl |= ERRCTL_PE;
1686 if (l1parity ^ l2parity)
1687 errctl |= ERRCTL_L2P;
1688 } else if (l1parity_present) {
1689 if (l1parity)
1690 errctl |= ERRCTL_PE;
1691 } else if (l2parity_present) {
1692 if (l2parity)
1693 errctl |= ERRCTL_L2P;
1694 } else {
1695 /* No parity available */
1696 }
1697
1698 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1699
1700 write_c0_ecc(errctl);
1701 back_to_back_c0_hazard();
1702 errctl = read_c0_ecc();
1703 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1704
1705 if (l1parity_present)
1706 printk(KERN_INFO "Cache parity protection %sabled\n",
1707 (errctl & ERRCTL_PE) ? "en" : "dis");
1708
1709 if (l2parity_present) {
1710 if (l1parity_present && l1parity)
1711 errctl ^= ERRCTL_L2P;
1712 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1713 (errctl & ERRCTL_L2P) ? "en" : "dis");
1714 }
1715 }
1716 break;
1717
1718 case CPU_5KC:
1719 case CPU_5KE:
1720 case CPU_LOONGSON1:
1721 write_c0_ecc(0x80000000);
1722 back_to_back_c0_hazard();
1723 /* Set the PE bit (bit 31) in the c0_errctl register. */
1724 printk(KERN_INFO "Cache parity protection %sabled\n",
1725 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1726 break;
1727 case CPU_20KC:
1728 case CPU_25KF:
1729 /* Clear the DE bit (bit 16) in the c0_status register. */
1730 printk(KERN_INFO "Enable cache parity protection for "
1731 "MIPS 20KC/25KF CPUs.\n");
1732 clear_c0_status(ST0_DE);
1733 break;
1734 default:
1735 break;
1736 }
1737 }
1738
1739 asmlinkage void cache_parity_error(void)
1740 {
1741 const int field = 2 * sizeof(unsigned long);
1742 unsigned int reg_val;
1743
1744 /* For the moment, report the problem and hang. */
1745 printk("Cache error exception:\n");
1746 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1747 reg_val = read_c0_cacheerr();
1748 printk("c0_cacheerr == %08x\n", reg_val);
1749
1750 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1751 reg_val & (1<<30) ? "secondary" : "primary",
1752 reg_val & (1<<31) ? "data" : "insn");
1753 if ((cpu_has_mips_r2_r6) &&
1754 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1755 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1756 reg_val & (1<<29) ? "ED " : "",
1757 reg_val & (1<<28) ? "ET " : "",
1758 reg_val & (1<<27) ? "ES " : "",
1759 reg_val & (1<<26) ? "EE " : "",
1760 reg_val & (1<<25) ? "EB " : "",
1761 reg_val & (1<<24) ? "EI " : "",
1762 reg_val & (1<<23) ? "E1 " : "",
1763 reg_val & (1<<22) ? "E0 " : "");
1764 } else {
1765 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1766 reg_val & (1<<29) ? "ED " : "",
1767 reg_val & (1<<28) ? "ET " : "",
1768 reg_val & (1<<26) ? "EE " : "",
1769 reg_val & (1<<25) ? "EB " : "",
1770 reg_val & (1<<24) ? "EI " : "",
1771 reg_val & (1<<23) ? "E1 " : "",
1772 reg_val & (1<<22) ? "E0 " : "");
1773 }
1774 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1775
1776 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1777 if (reg_val & (1<<22))
1778 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1779
1780 if (reg_val & (1<<23))
1781 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1782 #endif
1783
1784 panic("Can't handle the cache error!");
1785 }
1786
1787 asmlinkage void do_ftlb(void)
1788 {
1789 const int field = 2 * sizeof(unsigned long);
1790 unsigned int reg_val;
1791
1792 /* For the moment, report the problem and hang. */
1793 if ((cpu_has_mips_r2_r6) &&
1794 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1795 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1796 read_c0_ecc());
1797 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1798 reg_val = read_c0_cacheerr();
1799 pr_err("c0_cacheerr == %08x\n", reg_val);
1800
1801 if ((reg_val & 0xc0000000) == 0xc0000000) {
1802 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1803 } else {
1804 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1805 reg_val & (1<<30) ? "secondary" : "primary",
1806 reg_val & (1<<31) ? "data" : "insn");
1807 }
1808 } else {
1809 pr_err("FTLB error exception\n");
1810 }
1811 /* Just print the cacheerr bits for now */
1812 cache_parity_error();
1813 }
1814
1815 /*
1816 * SDBBP EJTAG debug exception handler.
1817 * We skip the instruction and return to the next instruction.
1818 */
1819 void ejtag_exception_handler(struct pt_regs *regs)
1820 {
1821 const int field = 2 * sizeof(unsigned long);
1822 unsigned long depc, old_epc, old_ra;
1823 unsigned int debug;
1824
1825 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1826 depc = read_c0_depc();
1827 debug = read_c0_debug();
1828 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1829 if (debug & 0x80000000) {
1830 /*
1831 * In branch delay slot.
1832 * We cheat a little bit here and use EPC to calculate the
1833 * debug return address (DEPC). EPC is restored after the
1834 * calculation.
1835 */
1836 old_epc = regs->cp0_epc;
1837 old_ra = regs->regs[31];
1838 regs->cp0_epc = depc;
1839 compute_return_epc(regs);
1840 depc = regs->cp0_epc;
1841 regs->cp0_epc = old_epc;
1842 regs->regs[31] = old_ra;
1843 } else
1844 depc += 4;
1845 write_c0_depc(depc);
1846
1847 #if 0
1848 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1849 write_c0_debug(debug | 0x100);
1850 #endif
1851 }
1852
1853 /*
1854 * NMI exception handler.
1855 * No lock; only written during early bootup by CPU 0.
1856 */
1857 static RAW_NOTIFIER_HEAD(nmi_chain);
1858
1859 int register_nmi_notifier(struct notifier_block *nb)
1860 {
1861 return raw_notifier_chain_register(&nmi_chain, nb);
1862 }
1863
1864 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1865 {
1866 char str[100];
1867
1868 nmi_enter();
1869 raw_notifier_call_chain(&nmi_chain, 0, regs);
1870 bust_spinlocks(1);
1871 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1872 smp_processor_id(), regs->cp0_epc);
1873 regs->cp0_epc = read_c0_errorepc();
1874 die(str, regs);
1875 nmi_exit();
1876 }
1877
1878 #define VECTORSPACING 0x100 /* for EI/VI mode */
1879
1880 unsigned long ebase;
1881 unsigned long exception_handlers[32];
1882 unsigned long vi_handlers[64];
1883
1884 void __init *set_except_vector(int n, void *addr)
1885 {
1886 unsigned long handler = (unsigned long) addr;
1887 unsigned long old_handler;
1888
1889 #ifdef CONFIG_CPU_MICROMIPS
1890 /*
1891 * Only the TLB handlers are cache aligned with an even
1892 * address. All other handlers are on an odd address and
1893 * require no modification. Otherwise, MIPS32 mode will
1894 * be entered when handling any TLB exceptions. That
1895 * would be bad...since we must stay in microMIPS mode.
1896 */
1897 if (!(handler & 0x1))
1898 handler |= 1;
1899 #endif
1900 old_handler = xchg(&exception_handlers[n], handler);
1901
1902 if (n == 0 && cpu_has_divec) {
1903 #ifdef CONFIG_CPU_MICROMIPS
1904 unsigned long jump_mask = ~((1 << 27) - 1);
1905 #else
1906 unsigned long jump_mask = ~((1 << 28) - 1);
1907 #endif
1908 u32 *buf = (u32 *)(ebase + 0x200);
1909 unsigned int k0 = 26;
1910 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1911 uasm_i_j(&buf, handler & ~jump_mask);
1912 uasm_i_nop(&buf);
1913 } else {
1914 UASM_i_LA(&buf, k0, handler);
1915 uasm_i_jr(&buf, k0);
1916 uasm_i_nop(&buf);
1917 }
1918 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1919 }
1920 return (void *)old_handler;
1921 }
1922
1923 static void do_default_vi(void)
1924 {
1925 show_regs(get_irq_regs());
1926 panic("Caught unexpected vectored interrupt.");
1927 }
1928
1929 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1930 {
1931 unsigned long handler;
1932 unsigned long old_handler = vi_handlers[n];
1933 int srssets = current_cpu_data.srsets;
1934 u16 *h;
1935 unsigned char *b;
1936
1937 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1938
1939 if (addr == NULL) {
1940 handler = (unsigned long) do_default_vi;
1941 srs = 0;
1942 } else
1943 handler = (unsigned long) addr;
1944 vi_handlers[n] = handler;
1945
1946 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1947
1948 if (srs >= srssets)
1949 panic("Shadow register set %d not supported", srs);
1950
1951 if (cpu_has_veic) {
1952 if (board_bind_eic_interrupt)
1953 board_bind_eic_interrupt(n, srs);
1954 } else if (cpu_has_vint) {
1955 /* SRSMap is only defined if shadow sets are implemented */
1956 if (srssets > 1)
1957 change_c0_srsmap(0xf << n*4, srs << n*4);
1958 }
1959
1960 if (srs == 0) {
1961 /*
1962 * If no shadow set is selected then use the default handler
1963 * that does normal register saving and standard interrupt exit
1964 */
1965 extern char except_vec_vi, except_vec_vi_lui;
1966 extern char except_vec_vi_ori, except_vec_vi_end;
1967 extern char rollback_except_vec_vi;
1968 char *vec_start = using_rollback_handler() ?
1969 &rollback_except_vec_vi : &except_vec_vi;
1970 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1971 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1972 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1973 #else
1974 const int lui_offset = &except_vec_vi_lui - vec_start;
1975 const int ori_offset = &except_vec_vi_ori - vec_start;
1976 #endif
1977 const int handler_len = &except_vec_vi_end - vec_start;
1978
1979 if (handler_len > VECTORSPACING) {
1980 /*
1981 * Sigh... panicing won't help as the console
1982 * is probably not configured :(
1983 */
1984 panic("VECTORSPACING too small");
1985 }
1986
1987 set_handler(((unsigned long)b - ebase), vec_start,
1988 #ifdef CONFIG_CPU_MICROMIPS
1989 (handler_len - 1));
1990 #else
1991 handler_len);
1992 #endif
1993 h = (u16 *)(b + lui_offset);
1994 *h = (handler >> 16) & 0xffff;
1995 h = (u16 *)(b + ori_offset);
1996 *h = (handler & 0xffff);
1997 local_flush_icache_range((unsigned long)b,
1998 (unsigned long)(b+handler_len));
1999 }
2000 else {
2001 /*
2002 * In other cases jump directly to the interrupt handler. It
2003 * is the handler's responsibility to save registers if required
2004 * (eg hi/lo) and return from the exception using "eret".
2005 */
2006 u32 insn;
2007
2008 h = (u16 *)b;
2009 /* j handler */
2010 #ifdef CONFIG_CPU_MICROMIPS
2011 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2012 #else
2013 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2014 #endif
2015 h[0] = (insn >> 16) & 0xffff;
2016 h[1] = insn & 0xffff;
2017 h[2] = 0;
2018 h[3] = 0;
2019 local_flush_icache_range((unsigned long)b,
2020 (unsigned long)(b+8));
2021 }
2022
2023 return (void *)old_handler;
2024 }
2025
2026 void *set_vi_handler(int n, vi_handler_t addr)
2027 {
2028 return set_vi_srs_handler(n, addr, 0);
2029 }
2030
2031 extern void tlb_init(void);
2032
2033 /*
2034 * Timer interrupt
2035 */
2036 int cp0_compare_irq;
2037 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2038 int cp0_compare_irq_shift;
2039
2040 /*
2041 * Performance counter IRQ or -1 if shared with timer
2042 */
2043 int cp0_perfcount_irq;
2044 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2045
2046 /*
2047 * Fast debug channel IRQ or -1 if not present
2048 */
2049 int cp0_fdc_irq;
2050 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2051
2052 static int noulri;
2053
2054 static int __init ulri_disable(char *s)
2055 {
2056 pr_info("Disabling ulri\n");
2057 noulri = 1;
2058
2059 return 1;
2060 }
2061 __setup("noulri", ulri_disable);
2062
2063 /* configure STATUS register */
2064 static void configure_status(void)
2065 {
2066 /*
2067 * Disable coprocessors and select 32-bit or 64-bit addressing
2068 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2069 * flag that some firmware may have left set and the TS bit (for
2070 * IP27). Set XX for ISA IV code to work.
2071 */
2072 unsigned int status_set = ST0_CU0;
2073 #ifdef CONFIG_64BIT
2074 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2075 #endif
2076 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2077 status_set |= ST0_XX;
2078 if (cpu_has_dsp)
2079 status_set |= ST0_MX;
2080
2081 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2082 status_set);
2083 back_to_back_c0_hazard();
2084 }
2085
2086 /* configure HWRENA register */
2087 static void configure_hwrena(void)
2088 {
2089 unsigned int hwrena = cpu_hwrena_impl_bits;
2090
2091 if (cpu_has_mips_r2_r6)
2092 hwrena |= 0x0000000f;
2093
2094 if (!noulri && cpu_has_userlocal)
2095 hwrena |= (1 << 29);
2096
2097 if (hwrena)
2098 write_c0_hwrena(hwrena);
2099 }
2100
2101 static void configure_exception_vector(void)
2102 {
2103 if (cpu_has_veic || cpu_has_vint) {
2104 unsigned long sr = set_c0_status(ST0_BEV);
2105 write_c0_ebase(ebase);
2106 write_c0_status(sr);
2107 /* Setting vector spacing enables EI/VI mode */
2108 change_c0_intctl(0x3e0, VECTORSPACING);
2109 }
2110 if (cpu_has_divec) {
2111 if (cpu_has_mipsmt) {
2112 unsigned int vpflags = dvpe();
2113 set_c0_cause(CAUSEF_IV);
2114 evpe(vpflags);
2115 } else
2116 set_c0_cause(CAUSEF_IV);
2117 }
2118 }
2119
2120 void per_cpu_trap_init(bool is_boot_cpu)
2121 {
2122 unsigned int cpu = smp_processor_id();
2123
2124 configure_status();
2125 configure_hwrena();
2126
2127 configure_exception_vector();
2128
2129 /*
2130 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2131 *
2132 * o read IntCtl.IPTI to determine the timer interrupt
2133 * o read IntCtl.IPPCI to determine the performance counter interrupt
2134 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2135 */
2136 if (cpu_has_mips_r2_r6) {
2137 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2138 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2139 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2140 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2141 if (!cp0_fdc_irq)
2142 cp0_fdc_irq = -1;
2143
2144 } else {
2145 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2146 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2147 cp0_perfcount_irq = -1;
2148 cp0_fdc_irq = -1;
2149 }
2150
2151 if (!cpu_data[cpu].asid_cache)
2152 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
2153
2154 atomic_inc(&init_mm.mm_count);
2155 current->active_mm = &init_mm;
2156 BUG_ON(current->mm);
2157 enter_lazy_tlb(&init_mm, current);
2158
2159 /* Boot CPU's cache setup in setup_arch(). */
2160 if (!is_boot_cpu)
2161 cpu_cache_init();
2162 tlb_init();
2163 TLBMISS_HANDLER_SETUP();
2164 }
2165
2166 /* Install CPU exception handler */
2167 void set_handler(unsigned long offset, void *addr, unsigned long size)
2168 {
2169 #ifdef CONFIG_CPU_MICROMIPS
2170 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2171 #else
2172 memcpy((void *)(ebase + offset), addr, size);
2173 #endif
2174 local_flush_icache_range(ebase + offset, ebase + offset + size);
2175 }
2176
2177 static char panic_null_cerr[] =
2178 "Trying to set NULL cache error exception handler";
2179
2180 /*
2181 * Install uncached CPU exception handler.
2182 * This is suitable only for the cache error exception which is the only
2183 * exception handler that is being run uncached.
2184 */
2185 void set_uncached_handler(unsigned long offset, void *addr,
2186 unsigned long size)
2187 {
2188 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2189
2190 if (!addr)
2191 panic(panic_null_cerr);
2192
2193 memcpy((void *)(uncached_ebase + offset), addr, size);
2194 }
2195
2196 static int __initdata rdhwr_noopt;
2197 static int __init set_rdhwr_noopt(char *str)
2198 {
2199 rdhwr_noopt = 1;
2200 return 1;
2201 }
2202
2203 __setup("rdhwr_noopt", set_rdhwr_noopt);
2204
2205 void __init trap_init(void)
2206 {
2207 extern char except_vec3_generic;
2208 extern char except_vec4;
2209 extern char except_vec3_r4000;
2210 unsigned long i;
2211
2212 check_wait();
2213
2214 if (cpu_has_veic || cpu_has_vint) {
2215 unsigned long size = 0x200 + VECTORSPACING*64;
2216 ebase = (unsigned long)
2217 __alloc_bootmem(size, 1 << fls(size), 0);
2218 } else {
2219 ebase = CAC_BASE;
2220
2221 if (cpu_has_mips_r2_r6)
2222 ebase += (read_c0_ebase() & 0x3ffff000);
2223 }
2224
2225 if (cpu_has_mmips) {
2226 unsigned int config3 = read_c0_config3();
2227
2228 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2229 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2230 else
2231 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2232 }
2233
2234 if (board_ebase_setup)
2235 board_ebase_setup();
2236 per_cpu_trap_init(true);
2237
2238 /*
2239 * Copy the generic exception handlers to their final destination.
2240 * This will be overriden later as suitable for a particular
2241 * configuration.
2242 */
2243 set_handler(0x180, &except_vec3_generic, 0x80);
2244
2245 /*
2246 * Setup default vectors
2247 */
2248 for (i = 0; i <= 31; i++)
2249 set_except_vector(i, handle_reserved);
2250
2251 /*
2252 * Copy the EJTAG debug exception vector handler code to it's final
2253 * destination.
2254 */
2255 if (cpu_has_ejtag && board_ejtag_handler_setup)
2256 board_ejtag_handler_setup();
2257
2258 /*
2259 * Only some CPUs have the watch exceptions.
2260 */
2261 if (cpu_has_watch)
2262 set_except_vector(23, handle_watch);
2263
2264 /*
2265 * Initialise interrupt handlers
2266 */
2267 if (cpu_has_veic || cpu_has_vint) {
2268 int nvec = cpu_has_veic ? 64 : 8;
2269 for (i = 0; i < nvec; i++)
2270 set_vi_handler(i, NULL);
2271 }
2272 else if (cpu_has_divec)
2273 set_handler(0x200, &except_vec4, 0x8);
2274
2275 /*
2276 * Some CPUs can enable/disable for cache parity detection, but does
2277 * it different ways.
2278 */
2279 parity_protection_init();
2280
2281 /*
2282 * The Data Bus Errors / Instruction Bus Errors are signaled
2283 * by external hardware. Therefore these two exceptions
2284 * may have board specific handlers.
2285 */
2286 if (board_be_init)
2287 board_be_init();
2288
2289 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2290 : handle_int);
2291 set_except_vector(1, handle_tlbm);
2292 set_except_vector(2, handle_tlbl);
2293 set_except_vector(3, handle_tlbs);
2294
2295 set_except_vector(4, handle_adel);
2296 set_except_vector(5, handle_ades);
2297
2298 set_except_vector(6, handle_ibe);
2299 set_except_vector(7, handle_dbe);
2300
2301 set_except_vector(8, handle_sys);
2302 set_except_vector(9, handle_bp);
2303 set_except_vector(10, rdhwr_noopt ? handle_ri :
2304 (cpu_has_vtag_icache ?
2305 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2306 set_except_vector(11, handle_cpu);
2307 set_except_vector(12, handle_ov);
2308 set_except_vector(13, handle_tr);
2309 set_except_vector(14, handle_msa_fpe);
2310
2311 if (current_cpu_type() == CPU_R6000 ||
2312 current_cpu_type() == CPU_R6000A) {
2313 /*
2314 * The R6000 is the only R-series CPU that features a machine
2315 * check exception (similar to the R4000 cache error) and
2316 * unaligned ldc1/sdc1 exception. The handlers have not been
2317 * written yet. Well, anyway there is no R6000 machine on the
2318 * current list of targets for Linux/MIPS.
2319 * (Duh, crap, there is someone with a triple R6k machine)
2320 */
2321 //set_except_vector(14, handle_mc);
2322 //set_except_vector(15, handle_ndc);
2323 }
2324
2325
2326 if (board_nmi_handler_setup)
2327 board_nmi_handler_setup();
2328
2329 if (cpu_has_fpu && !cpu_has_nofpuex)
2330 set_except_vector(15, handle_fpe);
2331
2332 set_except_vector(16, handle_ftlb);
2333
2334 if (cpu_has_rixiex) {
2335 set_except_vector(19, tlb_do_page_fault_0);
2336 set_except_vector(20, tlb_do_page_fault_0);
2337 }
2338
2339 set_except_vector(21, handle_msa);
2340 set_except_vector(22, handle_mdmx);
2341
2342 if (cpu_has_mcheck)
2343 set_except_vector(24, handle_mcheck);
2344
2345 if (cpu_has_mipsmt)
2346 set_except_vector(25, handle_mt);
2347
2348 set_except_vector(26, handle_dsp);
2349
2350 if (board_cache_error_setup)
2351 board_cache_error_setup();
2352
2353 if (cpu_has_vce)
2354 /* Special exception: R4[04]00 uses also the divec space. */
2355 set_handler(0x180, &except_vec3_r4000, 0x100);
2356 else if (cpu_has_4kex)
2357 set_handler(0x180, &except_vec3_generic, 0x80);
2358 else
2359 set_handler(0x080, &except_vec3_generic, 0x80);
2360
2361 local_flush_icache_range(ebase, ebase + 0x400);
2362
2363 sort_extable(__start___dbe_table, __stop___dbe_table);
2364
2365 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2366 }
2367
2368 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2369 void *v)
2370 {
2371 switch (cmd) {
2372 case CPU_PM_ENTER_FAILED:
2373 case CPU_PM_EXIT:
2374 configure_status();
2375 configure_hwrena();
2376 configure_exception_vector();
2377
2378 /* Restore register with CPU number for TLB handlers */
2379 TLBMISS_HANDLER_RESTORE();
2380
2381 break;
2382 }
2383
2384 return NOTIFY_OK;
2385 }
2386
2387 static struct notifier_block trap_pm_notifier_block = {
2388 .notifier_call = trap_pm_notifier,
2389 };
2390
2391 static int __init trap_pm_init(void)
2392 {
2393 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2394 }
2395 arch_initcall(trap_pm_init);
2396
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