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Linux/arch/mips/lantiq/prom.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  *
  4  * Copyright (C) 2010 John Crispin <john@phrozen.org>
  5  */
  6 
  7 #include <linux/export.h>
  8 #include <linux/clk.h>
  9 #include <linux/memblock.h>
 10 #include <linux/of_fdt.h>
 11 
 12 #include <asm/bootinfo.h>
 13 #include <asm/time.h>
 14 #include <asm/prom.h>
 15 
 16 #include <lantiq.h>
 17 
 18 #include "prom.h"
 19 #include "clk.h"
 20 
 21 /* access to the ebu needs to be locked between different drivers */
 22 DEFINE_SPINLOCK(ebu_lock);
 23 EXPORT_SYMBOL_GPL(ebu_lock);
 24 
 25 /*
 26  * This is needed by the VPE loader code, just set it to 0 and assume
 27  * that the firmware hardcodes this value to something useful.
 28  */
 29 unsigned long physical_memsize = 0L;
 30 
 31 /*
 32  * this struct is filled by the soc specific detection code and holds
 33  * information about the specific soc type, revision and name
 34  */
 35 static struct ltq_soc_info soc_info;
 36 
 37 const char *get_system_type(void)
 38 {
 39         return soc_info.sys_type;
 40 }
 41 
 42 int ltq_soc_type(void)
 43 {
 44         return soc_info.type;
 45 }
 46 
 47 void __init prom_free_prom_memory(void)
 48 {
 49 }
 50 
 51 static void __init prom_init_cmdline(void)
 52 {
 53         int argc = fw_arg0;
 54         char **argv = (char **) KSEG1ADDR(fw_arg1);
 55         int i;
 56 
 57         arcs_cmdline[0] = '\0';
 58 
 59         for (i = 0; i < argc; i++) {
 60                 char *p = (char *) KSEG1ADDR(argv[i]);
 61 
 62                 if (CPHYSADDR(p) && *p) {
 63                         strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
 64                         strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
 65                 }
 66         }
 67 }
 68 
 69 void __init plat_mem_setup(void)
 70 {
 71         void *dtb;
 72 
 73         ioport_resource.start = IOPORT_RESOURCE_START;
 74         ioport_resource.end = IOPORT_RESOURCE_END;
 75         iomem_resource.start = IOMEM_RESOURCE_START;
 76         iomem_resource.end = IOMEM_RESOURCE_END;
 77 
 78         set_io_port_base((unsigned long) KSEG1);
 79 
 80         if (fw_passed_dtb) /* UHI interface */
 81                 dtb = (void *)fw_passed_dtb;
 82         else if (__dtb_start != __dtb_end)
 83                 dtb = (void *)__dtb_start;
 84         else
 85                 panic("no dtb found");
 86 
 87         /*
 88          * Load the devicetree. This causes the chosen node to be
 89          * parsed resulting in our memory appearing
 90          */
 91         __dt_setup_arch(dtb);
 92 }
 93 
 94 void __init device_tree_init(void)
 95 {
 96         unflatten_and_copy_device_tree();
 97 }
 98 
 99 void __init prom_init(void)
100 {
101         /* call the soc specific detetcion code and get it to fill soc_info */
102         ltq_soc_detect(&soc_info);
103         snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
104                 soc_info.name, soc_info.rev_type);
105         soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
106         pr_info("SoC: %s\n", soc_info.sys_type);
107         prom_init_cmdline();
108 
109 #if defined(CONFIG_MIPS_MT_SMP)
110         if (register_vsmp_smp_ops())
111                 panic("failed to register_vsmp_smp_ops()");
112 #endif
113 }
114 

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