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Linux/arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c

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  1 /*
  2  * CS5536 General timer functions
  3  *
  4  * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
  5  * Author: Yanhua, yanh@lemote.com
  6  *
  7  * Copyright (C) 2009 Lemote Inc.
  8  * Author: Wu zhangjin, wuzhangjin@gmail.com
  9  *
 10  * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
 11  *
 12  *  This program is free software; you can redistribute  it and/or modify it
 13  *  under  the terms of  the GNU General  Public License as published by the
 14  *  Free Software Foundation;  either version 2 of the  License, or (at your
 15  *  option) any later version.
 16  */
 17 
 18 #include <linux/io.h>
 19 #include <linux/init.h>
 20 #include <linux/export.h>
 21 #include <linux/jiffies.h>
 22 #include <linux/spinlock.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/clockchips.h>
 25 
 26 #include <asm/time.h>
 27 
 28 #include <cs5536/cs5536_mfgpt.h>
 29 
 30 static DEFINE_RAW_SPINLOCK(mfgpt_lock);
 31 
 32 static u32 mfgpt_base;
 33 
 34 /*
 35  * Initialize the MFGPT timer.
 36  *
 37  * This is also called after resume to bring the MFGPT into operation again.
 38  */
 39 
 40 /* disable counter */
 41 void disable_mfgpt0_counter(void)
 42 {
 43         outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
 44 }
 45 EXPORT_SYMBOL(disable_mfgpt0_counter);
 46 
 47 /* enable counter, comparator2 to event mode, 14.318MHz clock */
 48 void enable_mfgpt0_counter(void)
 49 {
 50         outw(0xe310, MFGPT0_SETUP);
 51 }
 52 EXPORT_SYMBOL(enable_mfgpt0_counter);
 53 
 54 static int mfgpt_timer_set_periodic(struct clock_event_device *evt)
 55 {
 56         raw_spin_lock(&mfgpt_lock);
 57 
 58         outw(COMPARE, MFGPT0_CMP2);     /* set comparator2 */
 59         outw(0, MFGPT0_CNT);            /* set counter to 0 */
 60         enable_mfgpt0_counter();
 61 
 62         raw_spin_unlock(&mfgpt_lock);
 63         return 0;
 64 }
 65 
 66 static int mfgpt_timer_shutdown(struct clock_event_device *evt)
 67 {
 68         if (clockevent_state_periodic(evt) || clockevent_state_oneshot(evt)) {
 69                 raw_spin_lock(&mfgpt_lock);
 70                 disable_mfgpt0_counter();
 71                 raw_spin_unlock(&mfgpt_lock);
 72         }
 73 
 74         return 0;
 75 }
 76 
 77 static struct clock_event_device mfgpt_clockevent = {
 78         .name = "mfgpt",
 79         .features = CLOCK_EVT_FEAT_PERIODIC,
 80 
 81         /* The oneshot mode have very high deviation, don't use it! */
 82         .set_state_shutdown = mfgpt_timer_shutdown,
 83         .set_state_periodic = mfgpt_timer_set_periodic,
 84         .irq = CS5536_MFGPT_INTR,
 85 };
 86 
 87 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 88 {
 89         u32 basehi;
 90 
 91         /*
 92          * get MFGPT base address
 93          *
 94          * NOTE: do not remove me, it's need for the value of mfgpt_base is
 95          * variable
 96          */
 97         _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
 98 
 99         /* ack */
100         outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
101 
102         mfgpt_clockevent.event_handler(&mfgpt_clockevent);
103 
104         return IRQ_HANDLED;
105 }
106 
107 static struct irqaction irq5 = {
108         .handler = timer_interrupt,
109         .flags = IRQF_NOBALANCING | IRQF_TIMER,
110         .name = "timer"
111 };
112 
113 /*
114  * Initialize the conversion factor and the min/max deltas of the clock event
115  * structure and register the clock event source with the framework.
116  */
117 void __init setup_mfgpt0_timer(void)
118 {
119         u32 basehi;
120         struct clock_event_device *cd = &mfgpt_clockevent;
121         unsigned int cpu = smp_processor_id();
122 
123         cd->cpumask = cpumask_of(cpu);
124         clockevent_set_clock(cd, MFGPT_TICK_RATE);
125         cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
126         cd->max_delta_ticks = 0xffff;
127         cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
128         cd->min_delta_ticks = 0xf;
129 
130         /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
131         _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
132 
133         /* Enable Interrupt Gate 5 */
134         _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
135 
136         /* get MFGPT base address */
137         _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
138 
139         clockevents_register_device(cd);
140 
141         setup_irq(CS5536_MFGPT_INTR, &irq5);
142 }
143 
144 /*
145  * Since the MFGPT overflows every tick, its not very useful
146  * to just read by itself. So use jiffies to emulate a free
147  * running counter:
148  */
149 static u64 mfgpt_read(struct clocksource *cs)
150 {
151         unsigned long flags;
152         int count;
153         u32 jifs;
154         static int old_count;
155         static u32 old_jifs;
156 
157         raw_spin_lock_irqsave(&mfgpt_lock, flags);
158         /*
159          * Although our caller may have the read side of xtime_lock,
160          * this is now a seqlock, and we are cheating in this routine
161          * by having side effects on state that we cannot undo if
162          * there is a collision on the seqlock and our caller has to
163          * retry.  (Namely, old_jifs and old_count.)  So we must treat
164          * jiffies as volatile despite the lock.  We read jiffies
165          * before latching the timer count to guarantee that although
166          * the jiffies value might be older than the count (that is,
167          * the counter may underflow between the last point where
168          * jiffies was incremented and the point where we latch the
169          * count), it cannot be newer.
170          */
171         jifs = jiffies;
172         /* read the count */
173         count = inw(MFGPT0_CNT);
174 
175         /*
176          * It's possible for count to appear to go the wrong way for this
177          * reason:
178          *
179          *  The timer counter underflows, but we haven't handled the resulting
180          *  interrupt and incremented jiffies yet.
181          *
182          * Previous attempts to handle these cases intelligently were buggy, so
183          * we just do the simple thing now.
184          */
185         if (count < old_count && jifs == old_jifs)
186                 count = old_count;
187 
188         old_count = count;
189         old_jifs = jifs;
190 
191         raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
192 
193         return (u64) (jifs * COMPARE) + count;
194 }
195 
196 static struct clocksource clocksource_mfgpt = {
197         .name = "mfgpt",
198         .rating = 120, /* Functional for real use, but not desired */
199         .read = mfgpt_read,
200         .mask = CLOCKSOURCE_MASK(32),
201 };
202 
203 int __init init_mfgpt_clocksource(void)
204 {
205         if (num_possible_cpus() > 1)    /* MFGPT does not scale! */
206                 return 0;
207 
208         return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
209 }
210 
211 arch_initcall(init_mfgpt_clocksource);
212 

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