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Linux/arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * CS5536 General timer functions
  4  *
  5  * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
  6  * Author: Yanhua, yanh@lemote.com
  7  *
  8  * Copyright (C) 2009 Lemote Inc.
  9  * Author: Wu zhangjin, wuzhangjin@gmail.com
 10  *
 11  * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
 12  */
 13 
 14 #include <linux/io.h>
 15 #include <linux/init.h>
 16 #include <linux/export.h>
 17 #include <linux/jiffies.h>
 18 #include <linux/spinlock.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/clockchips.h>
 21 
 22 #include <asm/time.h>
 23 
 24 #include <cs5536/cs5536_mfgpt.h>
 25 
 26 static DEFINE_RAW_SPINLOCK(mfgpt_lock);
 27 
 28 static u32 mfgpt_base;
 29 
 30 /*
 31  * Initialize the MFGPT timer.
 32  *
 33  * This is also called after resume to bring the MFGPT into operation again.
 34  */
 35 
 36 /* disable counter */
 37 void disable_mfgpt0_counter(void)
 38 {
 39         outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
 40 }
 41 EXPORT_SYMBOL(disable_mfgpt0_counter);
 42 
 43 /* enable counter, comparator2 to event mode, 14.318MHz clock */
 44 void enable_mfgpt0_counter(void)
 45 {
 46         outw(0xe310, MFGPT0_SETUP);
 47 }
 48 EXPORT_SYMBOL(enable_mfgpt0_counter);
 49 
 50 static int mfgpt_timer_set_periodic(struct clock_event_device *evt)
 51 {
 52         raw_spin_lock(&mfgpt_lock);
 53 
 54         outw(COMPARE, MFGPT0_CMP2);     /* set comparator2 */
 55         outw(0, MFGPT0_CNT);            /* set counter to 0 */
 56         enable_mfgpt0_counter();
 57 
 58         raw_spin_unlock(&mfgpt_lock);
 59         return 0;
 60 }
 61 
 62 static int mfgpt_timer_shutdown(struct clock_event_device *evt)
 63 {
 64         if (clockevent_state_periodic(evt) || clockevent_state_oneshot(evt)) {
 65                 raw_spin_lock(&mfgpt_lock);
 66                 disable_mfgpt0_counter();
 67                 raw_spin_unlock(&mfgpt_lock);
 68         }
 69 
 70         return 0;
 71 }
 72 
 73 static struct clock_event_device mfgpt_clockevent = {
 74         .name = "mfgpt",
 75         .features = CLOCK_EVT_FEAT_PERIODIC,
 76 
 77         /* The oneshot mode have very high deviation, don't use it! */
 78         .set_state_shutdown = mfgpt_timer_shutdown,
 79         .set_state_periodic = mfgpt_timer_set_periodic,
 80         .irq = CS5536_MFGPT_INTR,
 81 };
 82 
 83 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 84 {
 85         u32 basehi;
 86 
 87         /*
 88          * get MFGPT base address
 89          *
 90          * NOTE: do not remove me, it's need for the value of mfgpt_base is
 91          * variable
 92          */
 93         _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
 94 
 95         /* ack */
 96         outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
 97 
 98         mfgpt_clockevent.event_handler(&mfgpt_clockevent);
 99 
100         return IRQ_HANDLED;
101 }
102 
103 static struct irqaction irq5 = {
104         .handler = timer_interrupt,
105         .flags = IRQF_NOBALANCING | IRQF_TIMER,
106         .name = "timer"
107 };
108 
109 /*
110  * Initialize the conversion factor and the min/max deltas of the clock event
111  * structure and register the clock event source with the framework.
112  */
113 void __init setup_mfgpt0_timer(void)
114 {
115         u32 basehi;
116         struct clock_event_device *cd = &mfgpt_clockevent;
117         unsigned int cpu = smp_processor_id();
118 
119         cd->cpumask = cpumask_of(cpu);
120         clockevent_set_clock(cd, MFGPT_TICK_RATE);
121         cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
122         cd->max_delta_ticks = 0xffff;
123         cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
124         cd->min_delta_ticks = 0xf;
125 
126         /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
127         _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
128 
129         /* Enable Interrupt Gate 5 */
130         _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
131 
132         /* get MFGPT base address */
133         _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
134 
135         clockevents_register_device(cd);
136 
137         setup_irq(CS5536_MFGPT_INTR, &irq5);
138 }
139 
140 /*
141  * Since the MFGPT overflows every tick, its not very useful
142  * to just read by itself. So use jiffies to emulate a free
143  * running counter:
144  */
145 static u64 mfgpt_read(struct clocksource *cs)
146 {
147         unsigned long flags;
148         int count;
149         u32 jifs;
150         static int old_count;
151         static u32 old_jifs;
152 
153         raw_spin_lock_irqsave(&mfgpt_lock, flags);
154         /*
155          * Although our caller may have the read side of xtime_lock,
156          * this is now a seqlock, and we are cheating in this routine
157          * by having side effects on state that we cannot undo if
158          * there is a collision on the seqlock and our caller has to
159          * retry.  (Namely, old_jifs and old_count.)  So we must treat
160          * jiffies as volatile despite the lock.  We read jiffies
161          * before latching the timer count to guarantee that although
162          * the jiffies value might be older than the count (that is,
163          * the counter may underflow between the last point where
164          * jiffies was incremented and the point where we latch the
165          * count), it cannot be newer.
166          */
167         jifs = jiffies;
168         /* read the count */
169         count = inw(MFGPT0_CNT);
170 
171         /*
172          * It's possible for count to appear to go the wrong way for this
173          * reason:
174          *
175          *  The timer counter underflows, but we haven't handled the resulting
176          *  interrupt and incremented jiffies yet.
177          *
178          * Previous attempts to handle these cases intelligently were buggy, so
179          * we just do the simple thing now.
180          */
181         if (count < old_count && jifs == old_jifs)
182                 count = old_count;
183 
184         old_count = count;
185         old_jifs = jifs;
186 
187         raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
188 
189         return (u64) (jifs * COMPARE) + count;
190 }
191 
192 static struct clocksource clocksource_mfgpt = {
193         .name = "mfgpt",
194         .rating = 120, /* Functional for real use, but not desired */
195         .read = mfgpt_read,
196         .mask = CLOCKSOURCE_MASK(32),
197 };
198 
199 int __init init_mfgpt_clocksource(void)
200 {
201         if (num_possible_cpus() > 1)    /* MFGPT does not scale! */
202                 return 0;
203 
204         return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
205 }
206 
207 arch_initcall(init_mfgpt_clocksource);
208 

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