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TOMOYO Linux Cross Reference
Linux/arch/mips/mm/c-r4k.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
  8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  9  */
 10 #include <linux/cpu_pm.h>
 11 #include <linux/hardirq.h>
 12 #include <linux/init.h>
 13 #include <linux/highmem.h>
 14 #include <linux/kernel.h>
 15 #include <linux/linkage.h>
 16 #include <linux/preempt.h>
 17 #include <linux/sched.h>
 18 #include <linux/smp.h>
 19 #include <linux/mm.h>
 20 #include <linux/export.h>
 21 #include <linux/bitops.h>
 22 
 23 #include <asm/bcache.h>
 24 #include <asm/bootinfo.h>
 25 #include <asm/cache.h>
 26 #include <asm/cacheops.h>
 27 #include <asm/cpu.h>
 28 #include <asm/cpu-features.h>
 29 #include <asm/cpu-type.h>
 30 #include <asm/io.h>
 31 #include <asm/page.h>
 32 #include <asm/pgtable.h>
 33 #include <asm/r4kcache.h>
 34 #include <asm/sections.h>
 35 #include <asm/mmu_context.h>
 36 #include <asm/war.h>
 37 #include <asm/cacheflush.h> /* for run_uncached() */
 38 #include <asm/traps.h>
 39 #include <asm/dma-coherence.h>
 40 #include <asm/mips-cps.h>
 41 
 42 /*
 43  * Bits describing what cache ops an SMP callback function may perform.
 44  *
 45  * R4K_HIT   -  Virtual user or kernel address based cache operations. The
 46  *              active_mm must be checked before using user addresses, falling
 47  *              back to kmap.
 48  * R4K_INDEX -  Index based cache operations.
 49  */
 50 
 51 #define R4K_HIT         BIT(0)
 52 #define R4K_INDEX       BIT(1)
 53 
 54 /**
 55  * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
 56  * @type:       Type of cache operations (R4K_HIT or R4K_INDEX).
 57  *
 58  * Decides whether a cache op needs to be performed on every core in the system.
 59  * This may change depending on the @type of cache operation, as well as the set
 60  * of online CPUs, so preemption should be disabled by the caller to prevent CPU
 61  * hotplug from changing the result.
 62  *
 63  * Returns:     1 if the cache operation @type should be done on every core in
 64  *              the system.
 65  *              0 if the cache operation @type is globalized and only needs to
 66  *              be performed on a simple CPU.
 67  */
 68 static inline bool r4k_op_needs_ipi(unsigned int type)
 69 {
 70         /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
 71         if (type == R4K_HIT && mips_cm_present())
 72                 return false;
 73 
 74         /*
 75          * Hardware doesn't globalize the required cache ops, so SMP calls may
 76          * be needed, but only if there are foreign CPUs (non-siblings with
 77          * separate caches).
 78          */
 79         /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
 80 #ifdef CONFIG_SMP
 81         return !cpumask_empty(&cpu_foreign_map[0]);
 82 #else
 83         return false;
 84 #endif
 85 }
 86 
 87 /*
 88  * Special Variant of smp_call_function for use by cache functions:
 89  *
 90  *  o No return value
 91  *  o collapses to normal function call on UP kernels
 92  *  o collapses to normal function call on systems with a single shared
 93  *    primary cache.
 94  *  o doesn't disable interrupts on the local CPU
 95  */
 96 static inline void r4k_on_each_cpu(unsigned int type,
 97                                    void (*func)(void *info), void *info)
 98 {
 99         preempt_disable();
100         if (r4k_op_needs_ipi(type))
101                 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
102                                        func, info, 1);
103         func(info);
104         preempt_enable();
105 }
106 
107 /*
108  * Must die.
109  */
110 static unsigned long icache_size __read_mostly;
111 static unsigned long dcache_size __read_mostly;
112 static unsigned long vcache_size __read_mostly;
113 static unsigned long scache_size __read_mostly;
114 
115 /*
116  * Dummy cache handling routines for machines without boardcaches
117  */
118 static void cache_noop(void) {}
119 
120 static struct bcache_ops no_sc_ops = {
121         .bc_enable = (void *)cache_noop,
122         .bc_disable = (void *)cache_noop,
123         .bc_wback_inv = (void *)cache_noop,
124         .bc_inv = (void *)cache_noop
125 };
126 
127 struct bcache_ops *bcops = &no_sc_ops;
128 
129 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
130 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
131 
132 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
133 do {                                                                    \
134         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
135                 *(volatile unsigned long *)CKSEG1;                      \
136         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
137                 __asm__ __volatile__("nop;nop;nop;nop");                \
138 } while (0)
139 
140 static void (*r4k_blast_dcache_page)(unsigned long addr);
141 
142 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
143 {
144         R4600_HIT_CACHEOP_WAR_IMPL;
145         blast_dcache32_page(addr);
146 }
147 
148 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
149 {
150         blast_dcache64_page(addr);
151 }
152 
153 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
154 {
155         blast_dcache128_page(addr);
156 }
157 
158 static void r4k_blast_dcache_page_setup(void)
159 {
160         unsigned long  dc_lsize = cpu_dcache_line_size();
161 
162         switch (dc_lsize) {
163         case 0:
164                 r4k_blast_dcache_page = (void *)cache_noop;
165                 break;
166         case 16:
167                 r4k_blast_dcache_page = blast_dcache16_page;
168                 break;
169         case 32:
170                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
171                 break;
172         case 64:
173                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
174                 break;
175         case 128:
176                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
177                 break;
178         default:
179                 break;
180         }
181 }
182 
183 #ifndef CONFIG_EVA
184 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
185 #else
186 
187 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
188 
189 static void r4k_blast_dcache_user_page_setup(void)
190 {
191         unsigned long  dc_lsize = cpu_dcache_line_size();
192 
193         if (dc_lsize == 0)
194                 r4k_blast_dcache_user_page = (void *)cache_noop;
195         else if (dc_lsize == 16)
196                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
197         else if (dc_lsize == 32)
198                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
199         else if (dc_lsize == 64)
200                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
201 }
202 
203 #endif
204 
205 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
206 
207 static void r4k_blast_dcache_page_indexed_setup(void)
208 {
209         unsigned long dc_lsize = cpu_dcache_line_size();
210 
211         if (dc_lsize == 0)
212                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
213         else if (dc_lsize == 16)
214                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
215         else if (dc_lsize == 32)
216                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
217         else if (dc_lsize == 64)
218                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
219         else if (dc_lsize == 128)
220                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
221 }
222 
223 void (* r4k_blast_dcache)(void);
224 EXPORT_SYMBOL(r4k_blast_dcache);
225 
226 static void r4k_blast_dcache_setup(void)
227 {
228         unsigned long dc_lsize = cpu_dcache_line_size();
229 
230         if (dc_lsize == 0)
231                 r4k_blast_dcache = (void *)cache_noop;
232         else if (dc_lsize == 16)
233                 r4k_blast_dcache = blast_dcache16;
234         else if (dc_lsize == 32)
235                 r4k_blast_dcache = blast_dcache32;
236         else if (dc_lsize == 64)
237                 r4k_blast_dcache = blast_dcache64;
238         else if (dc_lsize == 128)
239                 r4k_blast_dcache = blast_dcache128;
240 }
241 
242 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
243 #define JUMP_TO_ALIGN(order) \
244         __asm__ __volatile__( \
245                 "b\t1f\n\t" \
246                 ".align\t" #order "\n\t" \
247                 "1:\n\t" \
248                 )
249 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
250 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
251 
252 static inline void blast_r4600_v1_icache32(void)
253 {
254         unsigned long flags;
255 
256         local_irq_save(flags);
257         blast_icache32();
258         local_irq_restore(flags);
259 }
260 
261 static inline void tx49_blast_icache32(void)
262 {
263         unsigned long start = INDEX_BASE;
264         unsigned long end = start + current_cpu_data.icache.waysize;
265         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
266         unsigned long ws_end = current_cpu_data.icache.ways <<
267                                current_cpu_data.icache.waybit;
268         unsigned long ws, addr;
269 
270         CACHE32_UNROLL32_ALIGN2;
271         /* I'm in even chunk.  blast odd chunks */
272         for (ws = 0; ws < ws_end; ws += ws_inc)
273                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
274                         cache32_unroll32(addr|ws, Index_Invalidate_I);
275         CACHE32_UNROLL32_ALIGN;
276         /* I'm in odd chunk.  blast even chunks */
277         for (ws = 0; ws < ws_end; ws += ws_inc)
278                 for (addr = start; addr < end; addr += 0x400 * 2)
279                         cache32_unroll32(addr|ws, Index_Invalidate_I);
280 }
281 
282 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
283 {
284         unsigned long flags;
285 
286         local_irq_save(flags);
287         blast_icache32_page_indexed(page);
288         local_irq_restore(flags);
289 }
290 
291 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
292 {
293         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
294         unsigned long start = INDEX_BASE + (page & indexmask);
295         unsigned long end = start + PAGE_SIZE;
296         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
297         unsigned long ws_end = current_cpu_data.icache.ways <<
298                                current_cpu_data.icache.waybit;
299         unsigned long ws, addr;
300 
301         CACHE32_UNROLL32_ALIGN2;
302         /* I'm in even chunk.  blast odd chunks */
303         for (ws = 0; ws < ws_end; ws += ws_inc)
304                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
305                         cache32_unroll32(addr|ws, Index_Invalidate_I);
306         CACHE32_UNROLL32_ALIGN;
307         /* I'm in odd chunk.  blast even chunks */
308         for (ws = 0; ws < ws_end; ws += ws_inc)
309                 for (addr = start; addr < end; addr += 0x400 * 2)
310                         cache32_unroll32(addr|ws, Index_Invalidate_I);
311 }
312 
313 static void (* r4k_blast_icache_page)(unsigned long addr);
314 
315 static void r4k_blast_icache_page_setup(void)
316 {
317         unsigned long ic_lsize = cpu_icache_line_size();
318 
319         if (ic_lsize == 0)
320                 r4k_blast_icache_page = (void *)cache_noop;
321         else if (ic_lsize == 16)
322                 r4k_blast_icache_page = blast_icache16_page;
323         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
324                 r4k_blast_icache_page = loongson2_blast_icache32_page;
325         else if (ic_lsize == 32)
326                 r4k_blast_icache_page = blast_icache32_page;
327         else if (ic_lsize == 64)
328                 r4k_blast_icache_page = blast_icache64_page;
329         else if (ic_lsize == 128)
330                 r4k_blast_icache_page = blast_icache128_page;
331 }
332 
333 #ifndef CONFIG_EVA
334 #define r4k_blast_icache_user_page  r4k_blast_icache_page
335 #else
336 
337 static void (*r4k_blast_icache_user_page)(unsigned long addr);
338 
339 static void r4k_blast_icache_user_page_setup(void)
340 {
341         unsigned long ic_lsize = cpu_icache_line_size();
342 
343         if (ic_lsize == 0)
344                 r4k_blast_icache_user_page = (void *)cache_noop;
345         else if (ic_lsize == 16)
346                 r4k_blast_icache_user_page = blast_icache16_user_page;
347         else if (ic_lsize == 32)
348                 r4k_blast_icache_user_page = blast_icache32_user_page;
349         else if (ic_lsize == 64)
350                 r4k_blast_icache_user_page = blast_icache64_user_page;
351 }
352 
353 #endif
354 
355 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
356 
357 static void r4k_blast_icache_page_indexed_setup(void)
358 {
359         unsigned long ic_lsize = cpu_icache_line_size();
360 
361         if (ic_lsize == 0)
362                 r4k_blast_icache_page_indexed = (void *)cache_noop;
363         else if (ic_lsize == 16)
364                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
365         else if (ic_lsize == 32) {
366                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
367                         r4k_blast_icache_page_indexed =
368                                 blast_icache32_r4600_v1_page_indexed;
369                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
370                         r4k_blast_icache_page_indexed =
371                                 tx49_blast_icache32_page_indexed;
372                 else if (current_cpu_type() == CPU_LOONGSON2)
373                         r4k_blast_icache_page_indexed =
374                                 loongson2_blast_icache32_page_indexed;
375                 else
376                         r4k_blast_icache_page_indexed =
377                                 blast_icache32_page_indexed;
378         } else if (ic_lsize == 64)
379                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
380 }
381 
382 void (* r4k_blast_icache)(void);
383 EXPORT_SYMBOL(r4k_blast_icache);
384 
385 static void r4k_blast_icache_setup(void)
386 {
387         unsigned long ic_lsize = cpu_icache_line_size();
388 
389         if (ic_lsize == 0)
390                 r4k_blast_icache = (void *)cache_noop;
391         else if (ic_lsize == 16)
392                 r4k_blast_icache = blast_icache16;
393         else if (ic_lsize == 32) {
394                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
395                         r4k_blast_icache = blast_r4600_v1_icache32;
396                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
397                         r4k_blast_icache = tx49_blast_icache32;
398                 else if (current_cpu_type() == CPU_LOONGSON2)
399                         r4k_blast_icache = loongson2_blast_icache32;
400                 else
401                         r4k_blast_icache = blast_icache32;
402         } else if (ic_lsize == 64)
403                 r4k_blast_icache = blast_icache64;
404         else if (ic_lsize == 128)
405                 r4k_blast_icache = blast_icache128;
406 }
407 
408 static void (* r4k_blast_scache_page)(unsigned long addr);
409 
410 static void r4k_blast_scache_page_setup(void)
411 {
412         unsigned long sc_lsize = cpu_scache_line_size();
413 
414         if (scache_size == 0)
415                 r4k_blast_scache_page = (void *)cache_noop;
416         else if (sc_lsize == 16)
417                 r4k_blast_scache_page = blast_scache16_page;
418         else if (sc_lsize == 32)
419                 r4k_blast_scache_page = blast_scache32_page;
420         else if (sc_lsize == 64)
421                 r4k_blast_scache_page = blast_scache64_page;
422         else if (sc_lsize == 128)
423                 r4k_blast_scache_page = blast_scache128_page;
424 }
425 
426 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
427 
428 static void r4k_blast_scache_page_indexed_setup(void)
429 {
430         unsigned long sc_lsize = cpu_scache_line_size();
431 
432         if (scache_size == 0)
433                 r4k_blast_scache_page_indexed = (void *)cache_noop;
434         else if (sc_lsize == 16)
435                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
436         else if (sc_lsize == 32)
437                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
438         else if (sc_lsize == 64)
439                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
440         else if (sc_lsize == 128)
441                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
442 }
443 
444 static void (* r4k_blast_scache)(void);
445 
446 static void r4k_blast_scache_setup(void)
447 {
448         unsigned long sc_lsize = cpu_scache_line_size();
449 
450         if (scache_size == 0)
451                 r4k_blast_scache = (void *)cache_noop;
452         else if (sc_lsize == 16)
453                 r4k_blast_scache = blast_scache16;
454         else if (sc_lsize == 32)
455                 r4k_blast_scache = blast_scache32;
456         else if (sc_lsize == 64)
457                 r4k_blast_scache = blast_scache64;
458         else if (sc_lsize == 128)
459                 r4k_blast_scache = blast_scache128;
460 }
461 
462 static inline void local_r4k___flush_cache_all(void * args)
463 {
464         switch (current_cpu_type()) {
465         case CPU_LOONGSON2:
466         case CPU_LOONGSON3:
467         case CPU_R4000SC:
468         case CPU_R4000MC:
469         case CPU_R4400SC:
470         case CPU_R4400MC:
471         case CPU_R10000:
472         case CPU_R12000:
473         case CPU_R14000:
474         case CPU_R16000:
475                 /*
476                  * These caches are inclusive caches, that is, if something
477                  * is not cached in the S-cache, we know it also won't be
478                  * in one of the primary caches.
479                  */
480                 r4k_blast_scache();
481                 break;
482 
483         case CPU_BMIPS5000:
484                 r4k_blast_scache();
485                 __sync();
486                 break;
487 
488         default:
489                 r4k_blast_dcache();
490                 r4k_blast_icache();
491                 break;
492         }
493 }
494 
495 static void r4k___flush_cache_all(void)
496 {
497         r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
498 }
499 
500 /**
501  * has_valid_asid() - Determine if an mm already has an ASID.
502  * @mm:         Memory map.
503  * @type:       R4K_HIT or R4K_INDEX, type of cache op.
504  *
505  * Determines whether @mm already has an ASID on any of the CPUs which cache ops
506  * of type @type within an r4k_on_each_cpu() call will affect. If
507  * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
508  * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
509  * will need to be checked.
510  *
511  * Must be called in non-preemptive context.
512  *
513  * Returns:     1 if the CPUs affected by @type cache ops have an ASID for @mm.
514  *              0 otherwise.
515  */
516 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
517 {
518         unsigned int i;
519         const cpumask_t *mask = cpu_present_mask;
520 
521         /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
522 #ifdef CONFIG_SMP
523         /*
524          * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
525          * each foreign core, so we only need to worry about siblings.
526          * Otherwise we need to worry about all present CPUs.
527          */
528         if (r4k_op_needs_ipi(type))
529                 mask = &cpu_sibling_map[smp_processor_id()];
530 #endif
531         for_each_cpu(i, mask)
532                 if (cpu_context(i, mm))
533                         return 1;
534         return 0;
535 }
536 
537 static void r4k__flush_cache_vmap(void)
538 {
539         r4k_blast_dcache();
540 }
541 
542 static void r4k__flush_cache_vunmap(void)
543 {
544         r4k_blast_dcache();
545 }
546 
547 /*
548  * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
549  * whole caches when vma is executable.
550  */
551 static inline void local_r4k_flush_cache_range(void * args)
552 {
553         struct vm_area_struct *vma = args;
554         int exec = vma->vm_flags & VM_EXEC;
555 
556         if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
557                 return;
558 
559         /*
560          * If dcache can alias, we must blast it since mapping is changing.
561          * If executable, we must ensure any dirty lines are written back far
562          * enough to be visible to icache.
563          */
564         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
565                 r4k_blast_dcache();
566         /* If executable, blast stale lines from icache */
567         if (exec)
568                 r4k_blast_icache();
569 }
570 
571 static void r4k_flush_cache_range(struct vm_area_struct *vma,
572         unsigned long start, unsigned long end)
573 {
574         int exec = vma->vm_flags & VM_EXEC;
575 
576         if (cpu_has_dc_aliases || exec)
577                 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
578 }
579 
580 static inline void local_r4k_flush_cache_mm(void * args)
581 {
582         struct mm_struct *mm = args;
583 
584         if (!has_valid_asid(mm, R4K_INDEX))
585                 return;
586 
587         /*
588          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
589          * only flush the primary caches but R1x000 behave sane ...
590          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
591          * caches, so we can bail out early.
592          */
593         if (current_cpu_type() == CPU_R4000SC ||
594             current_cpu_type() == CPU_R4000MC ||
595             current_cpu_type() == CPU_R4400SC ||
596             current_cpu_type() == CPU_R4400MC) {
597                 r4k_blast_scache();
598                 return;
599         }
600 
601         r4k_blast_dcache();
602 }
603 
604 static void r4k_flush_cache_mm(struct mm_struct *mm)
605 {
606         if (!cpu_has_dc_aliases)
607                 return;
608 
609         r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
610 }
611 
612 struct flush_cache_page_args {
613         struct vm_area_struct *vma;
614         unsigned long addr;
615         unsigned long pfn;
616 };
617 
618 static inline void local_r4k_flush_cache_page(void *args)
619 {
620         struct flush_cache_page_args *fcp_args = args;
621         struct vm_area_struct *vma = fcp_args->vma;
622         unsigned long addr = fcp_args->addr;
623         struct page *page = pfn_to_page(fcp_args->pfn);
624         int exec = vma->vm_flags & VM_EXEC;
625         struct mm_struct *mm = vma->vm_mm;
626         int map_coherent = 0;
627         pgd_t *pgdp;
628         pud_t *pudp;
629         pmd_t *pmdp;
630         pte_t *ptep;
631         void *vaddr;
632 
633         /*
634          * If owns no valid ASID yet, cannot possibly have gotten
635          * this page into the cache.
636          */
637         if (!has_valid_asid(mm, R4K_HIT))
638                 return;
639 
640         addr &= PAGE_MASK;
641         pgdp = pgd_offset(mm, addr);
642         pudp = pud_offset(pgdp, addr);
643         pmdp = pmd_offset(pudp, addr);
644         ptep = pte_offset(pmdp, addr);
645 
646         /*
647          * If the page isn't marked valid, the page cannot possibly be
648          * in the cache.
649          */
650         if (!(pte_present(*ptep)))
651                 return;
652 
653         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
654                 vaddr = NULL;
655         else {
656                 /*
657                  * Use kmap_coherent or kmap_atomic to do flushes for
658                  * another ASID than the current one.
659                  */
660                 map_coherent = (cpu_has_dc_aliases &&
661                                 page_mapcount(page) &&
662                                 !Page_dcache_dirty(page));
663                 if (map_coherent)
664                         vaddr = kmap_coherent(page, addr);
665                 else
666                         vaddr = kmap_atomic(page);
667                 addr = (unsigned long)vaddr;
668         }
669 
670         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
671                 vaddr ? r4k_blast_dcache_page(addr) :
672                         r4k_blast_dcache_user_page(addr);
673                 if (exec && !cpu_icache_snoops_remote_store)
674                         r4k_blast_scache_page(addr);
675         }
676         if (exec) {
677                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
678                         int cpu = smp_processor_id();
679 
680                         if (cpu_context(cpu, mm) != 0)
681                                 drop_mmu_context(mm, cpu);
682                 } else
683                         vaddr ? r4k_blast_icache_page(addr) :
684                                 r4k_blast_icache_user_page(addr);
685         }
686 
687         if (vaddr) {
688                 if (map_coherent)
689                         kunmap_coherent();
690                 else
691                         kunmap_atomic(vaddr);
692         }
693 }
694 
695 static void r4k_flush_cache_page(struct vm_area_struct *vma,
696         unsigned long addr, unsigned long pfn)
697 {
698         struct flush_cache_page_args args;
699 
700         args.vma = vma;
701         args.addr = addr;
702         args.pfn = pfn;
703 
704         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
705 }
706 
707 static inline void local_r4k_flush_data_cache_page(void * addr)
708 {
709         r4k_blast_dcache_page((unsigned long) addr);
710 }
711 
712 static void r4k_flush_data_cache_page(unsigned long addr)
713 {
714         if (in_atomic())
715                 local_r4k_flush_data_cache_page((void *)addr);
716         else
717                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
718                                 (void *) addr);
719 }
720 
721 struct flush_icache_range_args {
722         unsigned long start;
723         unsigned long end;
724         unsigned int type;
725         bool user;
726 };
727 
728 static inline void __local_r4k_flush_icache_range(unsigned long start,
729                                                   unsigned long end,
730                                                   unsigned int type,
731                                                   bool user)
732 {
733         if (!cpu_has_ic_fills_f_dc) {
734                 if (type == R4K_INDEX ||
735                     (type & R4K_INDEX && end - start >= dcache_size)) {
736                         r4k_blast_dcache();
737                 } else {
738                         R4600_HIT_CACHEOP_WAR_IMPL;
739                         if (user)
740                                 protected_blast_dcache_range(start, end);
741                         else
742                                 blast_dcache_range(start, end);
743                 }
744         }
745 
746         if (type == R4K_INDEX ||
747             (type & R4K_INDEX && end - start > icache_size))
748                 r4k_blast_icache();
749         else {
750                 switch (boot_cpu_type()) {
751                 case CPU_LOONGSON2:
752                         protected_loongson2_blast_icache_range(start, end);
753                         break;
754 
755                 default:
756                         if (user)
757                                 protected_blast_icache_range(start, end);
758                         else
759                                 blast_icache_range(start, end);
760                         break;
761                 }
762         }
763 }
764 
765 static inline void local_r4k_flush_icache_range(unsigned long start,
766                                                 unsigned long end)
767 {
768         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
769 }
770 
771 static inline void local_r4k_flush_icache_user_range(unsigned long start,
772                                                      unsigned long end)
773 {
774         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
775 }
776 
777 static inline void local_r4k_flush_icache_range_ipi(void *args)
778 {
779         struct flush_icache_range_args *fir_args = args;
780         unsigned long start = fir_args->start;
781         unsigned long end = fir_args->end;
782         unsigned int type = fir_args->type;
783         bool user = fir_args->user;
784 
785         __local_r4k_flush_icache_range(start, end, type, user);
786 }
787 
788 static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
789                                      bool user)
790 {
791         struct flush_icache_range_args args;
792         unsigned long size, cache_size;
793 
794         args.start = start;
795         args.end = end;
796         args.type = R4K_HIT | R4K_INDEX;
797         args.user = user;
798 
799         /*
800          * Indexed cache ops require an SMP call.
801          * Consider if that can or should be avoided.
802          */
803         preempt_disable();
804         if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
805                 /*
806                  * If address-based cache ops don't require an SMP call, then
807                  * use them exclusively for small flushes.
808                  */
809                 size = end - start;
810                 cache_size = icache_size;
811                 if (!cpu_has_ic_fills_f_dc) {
812                         size *= 2;
813                         cache_size += dcache_size;
814                 }
815                 if (size <= cache_size)
816                         args.type &= ~R4K_INDEX;
817         }
818         r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
819         preempt_enable();
820         instruction_hazard();
821 }
822 
823 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
824 {
825         return __r4k_flush_icache_range(start, end, false);
826 }
827 
828 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
829 {
830         return __r4k_flush_icache_range(start, end, true);
831 }
832 
833 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
834 
835 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
836 {
837         /* Catch bad driver code */
838         if (WARN_ON(size == 0))
839                 return;
840 
841         preempt_disable();
842         if (cpu_has_inclusive_pcaches) {
843                 if (size >= scache_size)
844                         r4k_blast_scache();
845                 else
846                         blast_scache_range(addr, addr + size);
847                 preempt_enable();
848                 __sync();
849                 return;
850         }
851 
852         /*
853          * Either no secondary cache or the available caches don't have the
854          * subset property so we have to flush the primary caches
855          * explicitly.
856          * If we would need IPI to perform an INDEX-type operation, then
857          * we have to use the HIT-type alternative as IPI cannot be used
858          * here due to interrupts possibly being disabled.
859          */
860         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
861                 r4k_blast_dcache();
862         } else {
863                 R4600_HIT_CACHEOP_WAR_IMPL;
864                 blast_dcache_range(addr, addr + size);
865         }
866         preempt_enable();
867 
868         bc_wback_inv(addr, size);
869         __sync();
870 }
871 
872 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
873 {
874         /* Catch bad driver code */
875         if (WARN_ON(size == 0))
876                 return;
877 
878         preempt_disable();
879         if (cpu_has_inclusive_pcaches) {
880                 if (size >= scache_size)
881                         r4k_blast_scache();
882                 else {
883                         /*
884                          * There is no clearly documented alignment requirement
885                          * for the cache instruction on MIPS processors and
886                          * some processors, among them the RM5200 and RM7000
887                          * QED processors will throw an address error for cache
888                          * hit ops with insufficient alignment.  Solved by
889                          * aligning the address to cache line size.
890                          */
891                         blast_inv_scache_range(addr, addr + size);
892                 }
893                 preempt_enable();
894                 __sync();
895                 return;
896         }
897 
898         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
899                 r4k_blast_dcache();
900         } else {
901                 R4600_HIT_CACHEOP_WAR_IMPL;
902                 blast_inv_dcache_range(addr, addr + size);
903         }
904         preempt_enable();
905 
906         bc_inv(addr, size);
907         __sync();
908 }
909 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
910 
911 struct flush_cache_sigtramp_args {
912         struct mm_struct *mm;
913         struct page *page;
914         unsigned long addr;
915 };
916 
917 /*
918  * While we're protected against bad userland addresses we don't care
919  * very much about what happens in that case.  Usually a segmentation
920  * fault will dump the process later on anyway ...
921  */
922 static void local_r4k_flush_cache_sigtramp(void *args)
923 {
924         struct flush_cache_sigtramp_args *fcs_args = args;
925         unsigned long addr = fcs_args->addr;
926         struct page *page = fcs_args->page;
927         struct mm_struct *mm = fcs_args->mm;
928         int map_coherent = 0;
929         void *vaddr;
930 
931         unsigned long ic_lsize = cpu_icache_line_size();
932         unsigned long dc_lsize = cpu_dcache_line_size();
933         unsigned long sc_lsize = cpu_scache_line_size();
934 
935         /*
936          * If owns no valid ASID yet, cannot possibly have gotten
937          * this page into the cache.
938          */
939         if (!has_valid_asid(mm, R4K_HIT))
940                 return;
941 
942         if (mm == current->active_mm) {
943                 vaddr = NULL;
944         } else {
945                 /*
946                  * Use kmap_coherent or kmap_atomic to do flushes for
947                  * another ASID than the current one.
948                  */
949                 map_coherent = (cpu_has_dc_aliases &&
950                                 page_mapcount(page) &&
951                                 !Page_dcache_dirty(page));
952                 if (map_coherent)
953                         vaddr = kmap_coherent(page, addr);
954                 else
955                         vaddr = kmap_atomic(page);
956                 addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
957         }
958 
959         R4600_HIT_CACHEOP_WAR_IMPL;
960         if (!cpu_has_ic_fills_f_dc) {
961                 if (dc_lsize)
962                         vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
963                               : protected_writeback_dcache_line(
964                                                         addr & ~(dc_lsize - 1));
965                 if (!cpu_icache_snoops_remote_store && scache_size)
966                         vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
967                               : protected_writeback_scache_line(
968                                                         addr & ~(sc_lsize - 1));
969         }
970         if (ic_lsize)
971                 vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
972                       : protected_flush_icache_line(addr & ~(ic_lsize - 1));
973 
974         if (vaddr) {
975                 if (map_coherent)
976                         kunmap_coherent();
977                 else
978                         kunmap_atomic(vaddr);
979         }
980 
981         if (MIPS4K_ICACHE_REFILL_WAR) {
982                 __asm__ __volatile__ (
983                         ".set push\n\t"
984                         ".set noat\n\t"
985                         ".set "MIPS_ISA_LEVEL"\n\t"
986 #ifdef CONFIG_32BIT
987                         "la     $at,1f\n\t"
988 #endif
989 #ifdef CONFIG_64BIT
990                         "dla    $at,1f\n\t"
991 #endif
992                         "cache  %0,($at)\n\t"
993                         "nop; nop; nop\n"
994                         "1:\n\t"
995                         ".set pop"
996                         :
997                         : "i" (Hit_Invalidate_I));
998         }
999         if (MIPS_CACHE_SYNC_WAR)
1000                 __asm__ __volatile__ ("sync");
1001 }
1002 
1003 static void r4k_flush_cache_sigtramp(unsigned long addr)
1004 {
1005         struct flush_cache_sigtramp_args args;
1006         int npages;
1007 
1008         down_read(&current->mm->mmap_sem);
1009 
1010         npages = get_user_pages_fast(addr, 1, 0, &args.page);
1011         if (npages < 1)
1012                 goto out;
1013 
1014         args.mm = current->mm;
1015         args.addr = addr;
1016 
1017         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
1018 
1019         put_page(args.page);
1020 out:
1021         up_read(&current->mm->mmap_sem);
1022 }
1023 
1024 static void r4k_flush_icache_all(void)
1025 {
1026         if (cpu_has_vtag_icache)
1027                 r4k_blast_icache();
1028 }
1029 
1030 struct flush_kernel_vmap_range_args {
1031         unsigned long   vaddr;
1032         int             size;
1033 };
1034 
1035 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
1036 {
1037         /*
1038          * Aliases only affect the primary caches so don't bother with
1039          * S-caches or T-caches.
1040          */
1041         r4k_blast_dcache();
1042 }
1043 
1044 static inline void local_r4k_flush_kernel_vmap_range(void *args)
1045 {
1046         struct flush_kernel_vmap_range_args *vmra = args;
1047         unsigned long vaddr = vmra->vaddr;
1048         int size = vmra->size;
1049 
1050         /*
1051          * Aliases only affect the primary caches so don't bother with
1052          * S-caches or T-caches.
1053          */
1054         R4600_HIT_CACHEOP_WAR_IMPL;
1055         blast_dcache_range(vaddr, vaddr + size);
1056 }
1057 
1058 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1059 {
1060         struct flush_kernel_vmap_range_args args;
1061 
1062         args.vaddr = (unsigned long) vaddr;
1063         args.size = size;
1064 
1065         if (size >= dcache_size)
1066                 r4k_on_each_cpu(R4K_INDEX,
1067                                 local_r4k_flush_kernel_vmap_range_index, NULL);
1068         else
1069                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1070                                 &args);
1071 }
1072 
1073 static inline void rm7k_erratum31(void)
1074 {
1075         const unsigned long ic_lsize = 32;
1076         unsigned long addr;
1077 
1078         /* RM7000 erratum #31. The icache is screwed at startup. */
1079         write_c0_taglo(0);
1080         write_c0_taghi(0);
1081 
1082         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1083                 __asm__ __volatile__ (
1084                         ".set push\n\t"
1085                         ".set noreorder\n\t"
1086                         ".set mips3\n\t"
1087                         "cache\t%1, 0(%0)\n\t"
1088                         "cache\t%1, 0x1000(%0)\n\t"
1089                         "cache\t%1, 0x2000(%0)\n\t"
1090                         "cache\t%1, 0x3000(%0)\n\t"
1091                         "cache\t%2, 0(%0)\n\t"
1092                         "cache\t%2, 0x1000(%0)\n\t"
1093                         "cache\t%2, 0x2000(%0)\n\t"
1094                         "cache\t%2, 0x3000(%0)\n\t"
1095                         "cache\t%1, 0(%0)\n\t"
1096                         "cache\t%1, 0x1000(%0)\n\t"
1097                         "cache\t%1, 0x2000(%0)\n\t"
1098                         "cache\t%1, 0x3000(%0)\n\t"
1099                         ".set pop\n"
1100                         :
1101                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
1102         }
1103 }
1104 
1105 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1106 {
1107         unsigned int imp = c->processor_id & PRID_IMP_MASK;
1108         unsigned int rev = c->processor_id & PRID_REV_MASK;
1109         int present = 0;
1110 
1111         /*
1112          * Early versions of the 74K do not update the cache tags on a
1113          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1114          * aliases.  In this case it is better to treat the cache as always
1115          * having aliases.  Also disable the synonym tag update feature
1116          * where available.  In this case no opportunistic tag update will
1117          * happen where a load causes a virtual address miss but a physical
1118          * address hit during a D-cache look-up.
1119          */
1120         switch (imp) {
1121         case PRID_IMP_74K:
1122                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1123                         present = 1;
1124                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1125                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1126                 break;
1127         case PRID_IMP_1074K:
1128                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1129                         present = 1;
1130                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1131                 }
1132                 break;
1133         default:
1134                 BUG();
1135         }
1136 
1137         return present;
1138 }
1139 
1140 static void b5k_instruction_hazard(void)
1141 {
1142         __sync();
1143         __sync();
1144         __asm__ __volatile__(
1145         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1146         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1147         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1148         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1149         : : : "memory");
1150 }
1151 
1152 static char *way_string[] = { NULL, "direct mapped", "2-way",
1153         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1154         "9-way", "10-way", "11-way", "12-way",
1155         "13-way", "14-way", "15-way", "16-way",
1156 };
1157 
1158 static void probe_pcache(void)
1159 {
1160         struct cpuinfo_mips *c = &current_cpu_data;
1161         unsigned int config = read_c0_config();
1162         unsigned int prid = read_c0_prid();
1163         int has_74k_erratum = 0;
1164         unsigned long config1;
1165         unsigned int lsize;
1166 
1167         switch (current_cpu_type()) {
1168         case CPU_R4600:                 /* QED style two way caches? */
1169         case CPU_R4700:
1170         case CPU_R5000:
1171         case CPU_NEVADA:
1172                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1173                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1174                 c->icache.ways = 2;
1175                 c->icache.waybit = __ffs(icache_size/2);
1176 
1177                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1178                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1179                 c->dcache.ways = 2;
1180                 c->dcache.waybit= __ffs(dcache_size/2);
1181 
1182                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1183                 break;
1184 
1185         case CPU_R5432:
1186         case CPU_R5500:
1187                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1188                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1189                 c->icache.ways = 2;
1190                 c->icache.waybit= 0;
1191 
1192                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1193                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1194                 c->dcache.ways = 2;
1195                 c->dcache.waybit = 0;
1196 
1197                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1198                 break;
1199 
1200         case CPU_TX49XX:
1201                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1202                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1203                 c->icache.ways = 4;
1204                 c->icache.waybit= 0;
1205 
1206                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1207                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1208                 c->dcache.ways = 4;
1209                 c->dcache.waybit = 0;
1210 
1211                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1212                 c->options |= MIPS_CPU_PREFETCH;
1213                 break;
1214 
1215         case CPU_R4000PC:
1216         case CPU_R4000SC:
1217         case CPU_R4000MC:
1218         case CPU_R4400PC:
1219         case CPU_R4400SC:
1220         case CPU_R4400MC:
1221         case CPU_R4300:
1222                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1223                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1224                 c->icache.ways = 1;
1225                 c->icache.waybit = 0;   /* doesn't matter */
1226 
1227                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1228                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1229                 c->dcache.ways = 1;
1230                 c->dcache.waybit = 0;   /* does not matter */
1231 
1232                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1233                 break;
1234 
1235         case CPU_R10000:
1236         case CPU_R12000:
1237         case CPU_R14000:
1238         case CPU_R16000:
1239                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1240                 c->icache.linesz = 64;
1241                 c->icache.ways = 2;
1242                 c->icache.waybit = 0;
1243 
1244                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1245                 c->dcache.linesz = 32;
1246                 c->dcache.ways = 2;
1247                 c->dcache.waybit = 0;
1248 
1249                 c->options |= MIPS_CPU_PREFETCH;
1250                 break;
1251 
1252         case CPU_VR4133:
1253                 write_c0_config(config & ~VR41_CONF_P4K);
1254         case CPU_VR4131:
1255                 /* Workaround for cache instruction bug of VR4131 */
1256                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1257                     c->processor_id == 0x0c82U) {
1258                         config |= 0x00400000U;
1259                         if (c->processor_id == 0x0c80U)
1260                                 config |= VR41_CONF_BP;
1261                         write_c0_config(config);
1262                 } else
1263                         c->options |= MIPS_CPU_CACHE_CDEX_P;
1264 
1265                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1266                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1267                 c->icache.ways = 2;
1268                 c->icache.waybit = __ffs(icache_size/2);
1269 
1270                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1271                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1272                 c->dcache.ways = 2;
1273                 c->dcache.waybit = __ffs(dcache_size/2);
1274                 break;
1275 
1276         case CPU_VR41XX:
1277         case CPU_VR4111:
1278         case CPU_VR4121:
1279         case CPU_VR4122:
1280         case CPU_VR4181:
1281         case CPU_VR4181A:
1282                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1283                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1284                 c->icache.ways = 1;
1285                 c->icache.waybit = 0;   /* doesn't matter */
1286 
1287                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1288                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1289                 c->dcache.ways = 1;
1290                 c->dcache.waybit = 0;   /* does not matter */
1291 
1292                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1293                 break;
1294 
1295         case CPU_RM7000:
1296                 rm7k_erratum31();
1297 
1298                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1299                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1300                 c->icache.ways = 4;
1301                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1302 
1303                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1304                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1305                 c->dcache.ways = 4;
1306                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1307 
1308                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1309                 c->options |= MIPS_CPU_PREFETCH;
1310                 break;
1311 
1312         case CPU_LOONGSON2:
1313                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1314                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1315                 if (prid & 0x3)
1316                         c->icache.ways = 4;
1317                 else
1318                         c->icache.ways = 2;
1319                 c->icache.waybit = 0;
1320 
1321                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1322                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1323                 if (prid & 0x3)
1324                         c->dcache.ways = 4;
1325                 else
1326                         c->dcache.ways = 2;
1327                 c->dcache.waybit = 0;
1328                 break;
1329 
1330         case CPU_LOONGSON3:
1331                 config1 = read_c0_config1();
1332                 lsize = (config1 >> 19) & 7;
1333                 if (lsize)
1334                         c->icache.linesz = 2 << lsize;
1335                 else
1336                         c->icache.linesz = 0;
1337                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1338                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1339                 icache_size = c->icache.sets *
1340                                           c->icache.ways *
1341                                           c->icache.linesz;
1342                 c->icache.waybit = 0;
1343 
1344                 lsize = (config1 >> 10) & 7;
1345                 if (lsize)
1346                         c->dcache.linesz = 2 << lsize;
1347                 else
1348                         c->dcache.linesz = 0;
1349                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1350                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1351                 dcache_size = c->dcache.sets *
1352                                           c->dcache.ways *
1353                                           c->dcache.linesz;
1354                 c->dcache.waybit = 0;
1355                 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
1356                         c->options |= MIPS_CPU_PREFETCH;
1357                 break;
1358 
1359         case CPU_CAVIUM_OCTEON3:
1360                 /* For now lie about the number of ways. */
1361                 c->icache.linesz = 128;
1362                 c->icache.sets = 16;
1363                 c->icache.ways = 8;
1364                 c->icache.flags |= MIPS_CACHE_VTAG;
1365                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1366 
1367                 c->dcache.linesz = 128;
1368                 c->dcache.ways = 8;
1369                 c->dcache.sets = 8;
1370                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1371                 c->options |= MIPS_CPU_PREFETCH;
1372                 break;
1373 
1374         default:
1375                 if (!(config & MIPS_CONF_M))
1376                         panic("Don't know how to probe P-caches on this cpu.");
1377 
1378                 /*
1379                  * So we seem to be a MIPS32 or MIPS64 CPU
1380                  * So let's probe the I-cache ...
1381                  */
1382                 config1 = read_c0_config1();
1383 
1384                 lsize = (config1 >> 19) & 7;
1385 
1386                 /* IL == 7 is reserved */
1387                 if (lsize == 7)
1388                         panic("Invalid icache line size");
1389 
1390                 c->icache.linesz = lsize ? 2 << lsize : 0;
1391 
1392                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1393                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1394 
1395                 icache_size = c->icache.sets *
1396                               c->icache.ways *
1397                               c->icache.linesz;
1398                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1399 
1400                 if (config & MIPS_CONF_VI)
1401                         c->icache.flags |= MIPS_CACHE_VTAG;
1402 
1403                 /*
1404                  * Now probe the MIPS32 / MIPS64 data cache.
1405                  */
1406                 c->dcache.flags = 0;
1407 
1408                 lsize = (config1 >> 10) & 7;
1409 
1410                 /* DL == 7 is reserved */
1411                 if (lsize == 7)
1412                         panic("Invalid dcache line size");
1413 
1414                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1415 
1416                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1417                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1418 
1419                 dcache_size = c->dcache.sets *
1420                               c->dcache.ways *
1421                               c->dcache.linesz;
1422                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1423 
1424                 c->options |= MIPS_CPU_PREFETCH;
1425                 break;
1426         }
1427 
1428         /*
1429          * Processor configuration sanity check for the R4000SC erratum
1430          * #5.  With page sizes larger than 32kB there is no possibility
1431          * to get a VCE exception anymore so we don't care about this
1432          * misconfiguration.  The case is rather theoretical anyway;
1433          * presumably no vendor is shipping his hardware in the "bad"
1434          * configuration.
1435          */
1436         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1437             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1438             !(config & CONF_SC) && c->icache.linesz != 16 &&
1439             PAGE_SIZE <= 0x8000)
1440                 panic("Improper R4000SC processor configuration detected");
1441 
1442         /* compute a couple of other cache variables */
1443         c->icache.waysize = icache_size / c->icache.ways;
1444         c->dcache.waysize = dcache_size / c->dcache.ways;
1445 
1446         c->icache.sets = c->icache.linesz ?
1447                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1448         c->dcache.sets = c->dcache.linesz ?
1449                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1450 
1451         /*
1452          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1453          * virtually indexed so normally would suffer from aliases.  So
1454          * normally they'd suffer from aliases but magic in the hardware deals
1455          * with that for us so we don't need to take care ourselves.
1456          */
1457         switch (current_cpu_type()) {
1458         case CPU_20KC:
1459         case CPU_25KF:
1460         case CPU_I6400:
1461         case CPU_I6500:
1462         case CPU_SB1:
1463         case CPU_SB1A:
1464         case CPU_XLR:
1465                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1466                 break;
1467 
1468         case CPU_R10000:
1469         case CPU_R12000:
1470         case CPU_R14000:
1471         case CPU_R16000:
1472                 break;
1473 
1474         case CPU_74K:
1475         case CPU_1074K:
1476                 has_74k_erratum = alias_74k_erratum(c);
1477                 /* Fall through. */
1478         case CPU_M14KC:
1479         case CPU_M14KEC:
1480         case CPU_24K:
1481         case CPU_34K:
1482         case CPU_1004K:
1483         case CPU_INTERAPTIV:
1484         case CPU_P5600:
1485         case CPU_PROAPTIV:
1486         case CPU_M5150:
1487         case CPU_QEMU_GENERIC:
1488         case CPU_P6600:
1489         case CPU_M6250:
1490                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1491                     (c->icache.waysize > PAGE_SIZE))
1492                         c->icache.flags |= MIPS_CACHE_ALIASES;
1493                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1494                         /*
1495                          * Effectively physically indexed dcache,
1496                          * thus no virtual aliases.
1497                         */
1498                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1499                         break;
1500                 }
1501         default:
1502                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1503                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1504         }
1505 
1506         /* Physically indexed caches don't suffer from virtual aliasing */
1507         if (c->dcache.flags & MIPS_CACHE_PINDEX)
1508                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1509 
1510         switch (current_cpu_type()) {
1511         case CPU_20KC:
1512                 /*
1513                  * Some older 20Kc chips doesn't have the 'VI' bit in
1514                  * the config register.
1515                  */
1516                 c->icache.flags |= MIPS_CACHE_VTAG;
1517                 break;
1518 
1519         case CPU_ALCHEMY:
1520         case CPU_I6400:
1521         case CPU_I6500:
1522                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1523                 break;
1524 
1525         case CPU_BMIPS5000:
1526                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1527                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1528                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1529                 break;
1530 
1531         case CPU_LOONGSON2:
1532                 /*
1533                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1534                  * one op will act on all 4 ways
1535                  */
1536                 c->icache.ways = 1;
1537         }
1538 
1539         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1540                icache_size >> 10,
1541                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1542                way_string[c->icache.ways], c->icache.linesz);
1543 
1544         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1545                dcache_size >> 10, way_string[c->dcache.ways],
1546                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1547                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1548                         "cache aliases" : "no aliases",
1549                c->dcache.linesz);
1550 }
1551 
1552 static void probe_vcache(void)
1553 {
1554         struct cpuinfo_mips *c = &current_cpu_data;
1555         unsigned int config2, lsize;
1556 
1557         if (current_cpu_type() != CPU_LOONGSON3)
1558                 return;
1559 
1560         config2 = read_c0_config2();
1561         if ((lsize = ((config2 >> 20) & 15)))
1562                 c->vcache.linesz = 2 << lsize;
1563         else
1564                 c->vcache.linesz = lsize;
1565 
1566         c->vcache.sets = 64 << ((config2 >> 24) & 15);
1567         c->vcache.ways = 1 + ((config2 >> 16) & 15);
1568 
1569         vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1570 
1571         c->vcache.waybit = 0;
1572         c->vcache.waysize = vcache_size / c->vcache.ways;
1573 
1574         pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1575                 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1576 }
1577 
1578 /*
1579  * If you even _breathe_ on this function, look at the gcc output and make sure
1580  * it does not pop things on and off the stack for the cache sizing loop that
1581  * executes in KSEG1 space or else you will crash and burn badly.  You have
1582  * been warned.
1583  */
1584 static int probe_scache(void)
1585 {
1586         unsigned long flags, addr, begin, end, pow2;
1587         unsigned int config = read_c0_config();
1588         struct cpuinfo_mips *c = &current_cpu_data;
1589 
1590         if (config & CONF_SC)
1591                 return 0;
1592 
1593         begin = (unsigned long) &_stext;
1594         begin &= ~((4 * 1024 * 1024) - 1);
1595         end = begin + (4 * 1024 * 1024);
1596 
1597         /*
1598          * This is such a bitch, you'd think they would make it easy to do
1599          * this.  Away you daemons of stupidity!
1600          */
1601         local_irq_save(flags);
1602 
1603         /* Fill each size-multiple cache line with a valid tag. */
1604         pow2 = (64 * 1024);
1605         for (addr = begin; addr < end; addr = (begin + pow2)) {
1606                 unsigned long *p = (unsigned long *) addr;
1607                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1608                 pow2 <<= 1;
1609         }
1610 
1611         /* Load first line with zero (therefore invalid) tag. */
1612         write_c0_taglo(0);
1613         write_c0_taghi(0);
1614         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1615         cache_op(Index_Store_Tag_I, begin);
1616         cache_op(Index_Store_Tag_D, begin);
1617         cache_op(Index_Store_Tag_SD, begin);
1618 
1619         /* Now search for the wrap around point. */
1620         pow2 = (128 * 1024);
1621         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1622                 cache_op(Index_Load_Tag_SD, addr);
1623                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1624                 if (!read_c0_taglo())
1625                         break;
1626                 pow2 <<= 1;
1627         }
1628         local_irq_restore(flags);
1629         addr -= begin;
1630 
1631         scache_size = addr;
1632         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1633         c->scache.ways = 1;
1634         c->scache.waybit = 0;           /* does not matter */
1635 
1636         return 1;
1637 }
1638 
1639 static void __init loongson2_sc_init(void)
1640 {
1641         struct cpuinfo_mips *c = &current_cpu_data;
1642 
1643         scache_size = 512*1024;
1644         c->scache.linesz = 32;
1645         c->scache.ways = 4;
1646         c->scache.waybit = 0;
1647         c->scache.waysize = scache_size / (c->scache.ways);
1648         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1649         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1650                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1651 
1652         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1653 }
1654 
1655 static void __init loongson3_sc_init(void)
1656 {
1657         struct cpuinfo_mips *c = &current_cpu_data;
1658         unsigned int config2, lsize;
1659 
1660         config2 = read_c0_config2();
1661         lsize = (config2 >> 4) & 15;
1662         if (lsize)
1663                 c->scache.linesz = 2 << lsize;
1664         else
1665                 c->scache.linesz = 0;
1666         c->scache.sets = 64 << ((config2 >> 8) & 15);
1667         c->scache.ways = 1 + (config2 & 15);
1668 
1669         scache_size = c->scache.sets *
1670                                   c->scache.ways *
1671                                   c->scache.linesz;
1672         /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1673         scache_size *= 4;
1674         c->scache.waybit = 0;
1675         c->scache.waysize = scache_size / c->scache.ways;
1676         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1677                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1678         if (scache_size)
1679                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1680         return;
1681 }
1682 
1683 extern int r5k_sc_init(void);
1684 extern int rm7k_sc_init(void);
1685 extern int mips_sc_init(void);
1686 
1687 static void setup_scache(void)
1688 {
1689         struct cpuinfo_mips *c = &current_cpu_data;
1690         unsigned int config = read_c0_config();
1691         int sc_present = 0;
1692 
1693         /*
1694          * Do the probing thing on R4000SC and R4400SC processors.  Other
1695          * processors don't have a S-cache that would be relevant to the
1696          * Linux memory management.
1697          */
1698         switch (current_cpu_type()) {
1699         case CPU_R4000SC:
1700         case CPU_R4000MC:
1701         case CPU_R4400SC:
1702         case CPU_R4400MC:
1703                 sc_present = run_uncached(probe_scache);
1704                 if (sc_present)
1705                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1706                 break;
1707 
1708         case CPU_R10000:
1709         case CPU_R12000:
1710         case CPU_R14000:
1711         case CPU_R16000:
1712                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1713                 c->scache.linesz = 64 << ((config >> 13) & 1);
1714                 c->scache.ways = 2;
1715                 c->scache.waybit= 0;
1716                 sc_present = 1;
1717                 break;
1718 
1719         case CPU_R5000:
1720         case CPU_NEVADA:
1721 #ifdef CONFIG_R5000_CPU_SCACHE
1722                 r5k_sc_init();
1723 #endif
1724                 return;
1725 
1726         case CPU_RM7000:
1727 #ifdef CONFIG_RM7000_CPU_SCACHE
1728                 rm7k_sc_init();
1729 #endif
1730                 return;
1731 
1732         case CPU_LOONGSON2:
1733                 loongson2_sc_init();
1734                 return;
1735 
1736         case CPU_LOONGSON3:
1737                 loongson3_sc_init();
1738                 return;
1739 
1740         case CPU_CAVIUM_OCTEON3:
1741         case CPU_XLP:
1742                 /* don't need to worry about L2, fully coherent */
1743                 return;
1744 
1745         default:
1746                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1747                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1748                                     MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1749 #ifdef CONFIG_MIPS_CPU_SCACHE
1750                         if (mips_sc_init ()) {
1751                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1752                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1753                                        scache_size >> 10,
1754                                        way_string[c->scache.ways], c->scache.linesz);
1755                         }
1756 #else
1757                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1758                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1759 #endif
1760                         return;
1761                 }
1762                 sc_present = 0;
1763         }
1764 
1765         if (!sc_present)
1766                 return;
1767 
1768         /* compute a couple of other cache variables */
1769         c->scache.waysize = scache_size / c->scache.ways;
1770 
1771         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1772 
1773         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1774                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1775 
1776         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1777 }
1778 
1779 void au1x00_fixup_config_od(void)
1780 {
1781         /*
1782          * c0_config.od (bit 19) was write only (and read as 0)
1783          * on the early revisions of Alchemy SOCs.  It disables the bus
1784          * transaction overlapping and needs to be set to fix various errata.
1785          */
1786         switch (read_c0_prid()) {
1787         case 0x00030100: /* Au1000 DA */
1788         case 0x00030201: /* Au1000 HA */
1789         case 0x00030202: /* Au1000 HB */
1790         case 0x01030200: /* Au1500 AB */
1791         /*
1792          * Au1100 errata actually keeps silence about this bit, so we set it
1793          * just in case for those revisions that require it to be set according
1794          * to the (now gone) cpu table.
1795          */
1796         case 0x02030200: /* Au1100 AB */
1797         case 0x02030201: /* Au1100 BA */
1798         case 0x02030202: /* Au1100 BC */
1799                 set_c0_config(1 << 19);
1800                 break;
1801         }
1802 }
1803 
1804 /* CP0 hazard avoidance. */
1805 #define NXP_BARRIER()                                                   \
1806          __asm__ __volatile__(                                          \
1807         ".set noreorder\n\t"                                            \
1808         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1809         ".set reorder\n\t")
1810 
1811 static void nxp_pr4450_fixup_config(void)
1812 {
1813         unsigned long config0;
1814 
1815         config0 = read_c0_config();
1816 
1817         /* clear all three cache coherency fields */
1818         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1819         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1820                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1821                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1822         write_c0_config(config0);
1823         NXP_BARRIER();
1824 }
1825 
1826 static int cca = -1;
1827 
1828 static int __init cca_setup(char *str)
1829 {
1830         get_option(&str, &cca);
1831 
1832         return 0;
1833 }
1834 
1835 early_param("cca", cca_setup);
1836 
1837 static void coherency_setup(void)
1838 {
1839         if (cca < 0 || cca > 7)
1840                 cca = read_c0_config() & CONF_CM_CMASK;
1841         _page_cachable_default = cca << _CACHE_SHIFT;
1842 
1843         pr_debug("Using cache attribute %d\n", cca);
1844         change_c0_config(CONF_CM_CMASK, cca);
1845 
1846         /*
1847          * c0_status.cu=0 specifies that updates by the sc instruction use
1848          * the coherency mode specified by the TLB; 1 means cachable
1849          * coherent update on write will be used.  Not all processors have
1850          * this bit and; some wire it to zero, others like Toshiba had the
1851          * silly idea of putting something else there ...
1852          */
1853         switch (current_cpu_type()) {
1854         case CPU_R4000PC:
1855         case CPU_R4000SC:
1856         case CPU_R4000MC:
1857         case CPU_R4400PC:
1858         case CPU_R4400SC:
1859         case CPU_R4400MC:
1860                 clear_c0_config(CONF_CU);
1861                 break;
1862         /*
1863          * We need to catch the early Alchemy SOCs with
1864          * the write-only co_config.od bit and set it back to one on:
1865          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1866          */
1867         case CPU_ALCHEMY:
1868                 au1x00_fixup_config_od();
1869                 break;
1870 
1871         case PRID_IMP_PR4450:
1872                 nxp_pr4450_fixup_config();
1873                 break;
1874         }
1875 }
1876 
1877 static void r4k_cache_error_setup(void)
1878 {
1879         extern char __weak except_vec2_generic;
1880         extern char __weak except_vec2_sb1;
1881 
1882         switch (current_cpu_type()) {
1883         case CPU_SB1:
1884         case CPU_SB1A:
1885                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1886                 break;
1887 
1888         default:
1889                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1890                 break;
1891         }
1892 }
1893 
1894 void r4k_cache_init(void)
1895 {
1896         extern void build_clear_page(void);
1897         extern void build_copy_page(void);
1898         struct cpuinfo_mips *c = &current_cpu_data;
1899 
1900         probe_pcache();
1901         probe_vcache();
1902         setup_scache();
1903 
1904         r4k_blast_dcache_page_setup();
1905         r4k_blast_dcache_page_indexed_setup();
1906         r4k_blast_dcache_setup();
1907         r4k_blast_icache_page_setup();
1908         r4k_blast_icache_page_indexed_setup();
1909         r4k_blast_icache_setup();
1910         r4k_blast_scache_page_setup();
1911         r4k_blast_scache_page_indexed_setup();
1912         r4k_blast_scache_setup();
1913 #ifdef CONFIG_EVA
1914         r4k_blast_dcache_user_page_setup();
1915         r4k_blast_icache_user_page_setup();
1916 #endif
1917 
1918         /*
1919          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1920          * This code supports virtually indexed processors and will be
1921          * unnecessarily inefficient on physically indexed processors.
1922          */
1923         if (c->dcache.linesz && cpu_has_dc_aliases)
1924                 shm_align_mask = max_t( unsigned long,
1925                                         c->dcache.sets * c->dcache.linesz - 1,
1926                                         PAGE_SIZE - 1);
1927         else
1928                 shm_align_mask = PAGE_SIZE-1;
1929 
1930         __flush_cache_vmap      = r4k__flush_cache_vmap;
1931         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1932 
1933         flush_cache_all         = cache_noop;
1934         __flush_cache_all       = r4k___flush_cache_all;
1935         flush_cache_mm          = r4k_flush_cache_mm;
1936         flush_cache_page        = r4k_flush_cache_page;
1937         flush_cache_range       = r4k_flush_cache_range;
1938 
1939         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1940 
1941         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1942         flush_icache_all        = r4k_flush_icache_all;
1943         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1944         flush_data_cache_page   = r4k_flush_data_cache_page;
1945         flush_icache_range      = r4k_flush_icache_range;
1946         local_flush_icache_range        = local_r4k_flush_icache_range;
1947         __flush_icache_user_range       = r4k_flush_icache_user_range;
1948         __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1949 
1950 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1951 # if defined(CONFIG_DMA_PERDEV_COHERENT)
1952         if (0) {
1953 # else
1954         if ((coherentio == IO_COHERENCE_ENABLED) ||
1955             ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) {
1956 # endif
1957                 _dma_cache_wback_inv    = (void *)cache_noop;
1958                 _dma_cache_wback        = (void *)cache_noop;
1959                 _dma_cache_inv          = (void *)cache_noop;
1960         } else {
1961                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1962                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1963                 _dma_cache_inv          = r4k_dma_cache_inv;
1964         }
1965 #endif
1966 
1967         build_clear_page();
1968         build_copy_page();
1969 
1970         /*
1971          * We want to run CMP kernels on core with and without coherent
1972          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1973          * or not to flush caches.
1974          */
1975         local_r4k___flush_cache_all(NULL);
1976 
1977         coherency_setup();
1978         board_cache_error_setup = r4k_cache_error_setup;
1979 
1980         /*
1981          * Per-CPU overrides
1982          */
1983         switch (current_cpu_type()) {
1984         case CPU_BMIPS4350:
1985         case CPU_BMIPS4380:
1986                 /* No IPI is needed because all CPUs share the same D$ */
1987                 flush_data_cache_page = r4k_blast_dcache_page;
1988                 break;
1989         case CPU_BMIPS5000:
1990                 /* We lose our superpowers if L2 is disabled */
1991                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1992                         break;
1993 
1994                 /* I$ fills from D$ just by emptying the write buffers */
1995                 flush_cache_page = (void *)b5k_instruction_hazard;
1996                 flush_cache_range = (void *)b5k_instruction_hazard;
1997                 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1998                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1999                 flush_data_cache_page = (void *)b5k_instruction_hazard;
2000                 flush_icache_range = (void *)b5k_instruction_hazard;
2001                 local_flush_icache_range = (void *)b5k_instruction_hazard;
2002 
2003 
2004                 /* Optimization: an L2 flush implicitly flushes the L1 */
2005                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
2006                 break;
2007         case CPU_LOONGSON3:
2008                 /* Loongson-3 maintains cache coherency by hardware */
2009                 __flush_cache_all       = cache_noop;
2010                 __flush_cache_vmap      = cache_noop;
2011                 __flush_cache_vunmap    = cache_noop;
2012                 __flush_kernel_vmap_range = (void *)cache_noop;
2013                 flush_cache_mm          = (void *)cache_noop;
2014                 flush_cache_page        = (void *)cache_noop;
2015                 flush_cache_range       = (void *)cache_noop;
2016                 flush_cache_sigtramp    = (void *)cache_noop;
2017                 flush_icache_all        = (void *)cache_noop;
2018                 flush_data_cache_page   = (void *)cache_noop;
2019                 local_flush_data_cache_page     = (void *)cache_noop;
2020                 break;
2021         }
2022 }
2023 
2024 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
2025                                void *v)
2026 {
2027         switch (cmd) {
2028         case CPU_PM_ENTER_FAILED:
2029         case CPU_PM_EXIT:
2030                 coherency_setup();
2031                 break;
2032         }
2033 
2034         return NOTIFY_OK;
2035 }
2036 
2037 static struct notifier_block r4k_cache_pm_notifier_block = {
2038         .notifier_call = r4k_cache_pm_notifier,
2039 };
2040 
2041 int __init r4k_cache_init_pm(void)
2042 {
2043         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
2044 }
2045 arch_initcall(r4k_cache_init_pm);
2046 

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