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TOMOYO Linux Cross Reference
Linux/arch/mips/mm/tlbex.c

Version: ~ [ linux-5.15-rc5 ] ~ [ linux-5.14.11 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.72 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.152 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.210 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.250 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.286 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.288 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Synthesize TLB refill handlers at runtime.
  7  *
  8  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  9  * Copyright (C) 2005, 2007, 2008, 2009  Maciej W. Rozycki
 10  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 11  * Copyright (C) 2008, 2009 Cavium Networks, Inc.
 12  * Copyright (C) 2011  MIPS Technologies, Inc.
 13  *
 14  * ... and the days got worse and worse and now you see
 15  * I've gone completely out of my mind.
 16  *
 17  * They're coming to take me a away haha
 18  * they're coming to take me a away hoho hihi haha
 19  * to the funny farm where code is beautiful all the time ...
 20  *
 21  * (Condolences to Napoleon XIV)
 22  */
 23 
 24 #include <linux/bug.h>
 25 #include <linux/export.h>
 26 #include <linux/kernel.h>
 27 #include <linux/types.h>
 28 #include <linux/smp.h>
 29 #include <linux/string.h>
 30 #include <linux/cache.h>
 31 
 32 #include <asm/cacheflush.h>
 33 #include <asm/cpu-type.h>
 34 #include <asm/mmu_context.h>
 35 #include <asm/pgtable.h>
 36 #include <asm/war.h>
 37 #include <asm/uasm.h>
 38 #include <asm/setup.h>
 39 #include <asm/tlbex.h>
 40 
 41 static int mips_xpa_disabled;
 42 
 43 static int __init xpa_disable(char *s)
 44 {
 45         mips_xpa_disabled = 1;
 46 
 47         return 1;
 48 }
 49 
 50 __setup("noxpa", xpa_disable);
 51 
 52 /*
 53  * TLB load/store/modify handlers.
 54  *
 55  * Only the fastpath gets synthesized at runtime, the slowpath for
 56  * do_page_fault remains normal asm.
 57  */
 58 extern void tlb_do_page_fault_0(void);
 59 extern void tlb_do_page_fault_1(void);
 60 
 61 struct work_registers {
 62         int r1;
 63         int r2;
 64         int r3;
 65 };
 66 
 67 struct tlb_reg_save {
 68         unsigned long a;
 69         unsigned long b;
 70 } ____cacheline_aligned_in_smp;
 71 
 72 static struct tlb_reg_save handler_reg_save[NR_CPUS];
 73 
 74 static inline int r45k_bvahwbug(void)
 75 {
 76         /* XXX: We should probe for the presence of this bug, but we don't. */
 77         return 0;
 78 }
 79 
 80 static inline int r4k_250MHZhwbug(void)
 81 {
 82         /* XXX: We should probe for the presence of this bug, but we don't. */
 83         return 0;
 84 }
 85 
 86 static inline int __maybe_unused bcm1250_m3_war(void)
 87 {
 88         return BCM1250_M3_WAR;
 89 }
 90 
 91 static inline int __maybe_unused r10000_llsc_war(void)
 92 {
 93         return R10000_LLSC_WAR;
 94 }
 95 
 96 static int use_bbit_insns(void)
 97 {
 98         switch (current_cpu_type()) {
 99         case CPU_CAVIUM_OCTEON:
100         case CPU_CAVIUM_OCTEON_PLUS:
101         case CPU_CAVIUM_OCTEON2:
102         case CPU_CAVIUM_OCTEON3:
103                 return 1;
104         default:
105                 return 0;
106         }
107 }
108 
109 static int use_lwx_insns(void)
110 {
111         switch (current_cpu_type()) {
112         case CPU_CAVIUM_OCTEON2:
113         case CPU_CAVIUM_OCTEON3:
114                 return 1;
115         default:
116                 return 0;
117         }
118 }
119 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
120     CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
121 static bool scratchpad_available(void)
122 {
123         return true;
124 }
125 static int scratchpad_offset(int i)
126 {
127         /*
128          * CVMSEG starts at address -32768 and extends for
129          * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
130          */
131         i += 1; /* Kernel use starts at the top and works down. */
132         return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
133 }
134 #else
135 static bool scratchpad_available(void)
136 {
137         return false;
138 }
139 static int scratchpad_offset(int i)
140 {
141         BUG();
142         /* Really unreachable, but evidently some GCC want this. */
143         return 0;
144 }
145 #endif
146 /*
147  * Found by experiment: At least some revisions of the 4kc throw under
148  * some circumstances a machine check exception, triggered by invalid
149  * values in the index register.  Delaying the tlbp instruction until
150  * after the next branch,  plus adding an additional nop in front of
151  * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
152  * why; it's not an issue caused by the core RTL.
153  *
154  */
155 static int m4kc_tlbp_war(void)
156 {
157         return current_cpu_type() == CPU_4KC;
158 }
159 
160 /* Handle labels (which must be positive integers). */
161 enum label_id {
162         label_second_part = 1,
163         label_leave,
164         label_vmalloc,
165         label_vmalloc_done,
166         label_tlbw_hazard_0,
167         label_split = label_tlbw_hazard_0 + 8,
168         label_tlbl_goaround1,
169         label_tlbl_goaround2,
170         label_nopage_tlbl,
171         label_nopage_tlbs,
172         label_nopage_tlbm,
173         label_smp_pgtable_change,
174         label_r3000_write_probe_fail,
175         label_large_segbits_fault,
176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
177         label_tlb_huge_update,
178 #endif
179 };
180 
181 UASM_L_LA(_second_part)
182 UASM_L_LA(_leave)
183 UASM_L_LA(_vmalloc)
184 UASM_L_LA(_vmalloc_done)
185 /* _tlbw_hazard_x is handled differently.  */
186 UASM_L_LA(_split)
187 UASM_L_LA(_tlbl_goaround1)
188 UASM_L_LA(_tlbl_goaround2)
189 UASM_L_LA(_nopage_tlbl)
190 UASM_L_LA(_nopage_tlbs)
191 UASM_L_LA(_nopage_tlbm)
192 UASM_L_LA(_smp_pgtable_change)
193 UASM_L_LA(_r3000_write_probe_fail)
194 UASM_L_LA(_large_segbits_fault)
195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
196 UASM_L_LA(_tlb_huge_update)
197 #endif
198 
199 static int hazard_instance;
200 
201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
202 {
203         switch (instance) {
204         case 0 ... 7:
205                 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
206                 return;
207         default:
208                 BUG();
209         }
210 }
211 
212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
213 {
214         switch (instance) {
215         case 0 ... 7:
216                 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
217                 break;
218         default:
219                 BUG();
220         }
221 }
222 
223 /*
224  * pgtable bits are assigned dynamically depending on processor feature
225  * and statically based on kernel configuration.  This spits out the actual
226  * values the kernel is using.  Required to make sense from disassembled
227  * TLB exception handlers.
228  */
229 static void output_pgtable_bits_defines(void)
230 {
231 #define pr_define(fmt, ...)                                     \
232         pr_debug("#define " fmt, ##__VA_ARGS__)
233 
234         pr_debug("#include <asm/asm.h>\n");
235         pr_debug("#include <asm/regdef.h>\n");
236         pr_debug("\n");
237 
238         pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
239         pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
240         pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
241         pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
242         pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
244         pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
245 #endif
246 #ifdef _PAGE_NO_EXEC_SHIFT
247         if (cpu_has_rixi)
248                 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
249 #endif
250         pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
251         pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
252         pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
253         pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
254         pr_debug("\n");
255 }
256 
257 static inline void dump_handler(const char *symbol, const void *start, const void *end)
258 {
259         unsigned int count = (end - start) / sizeof(u32);
260         const u32 *handler = start;
261         int i;
262 
263         pr_debug("LEAF(%s)\n", symbol);
264 
265         pr_debug("\t.set push\n");
266         pr_debug("\t.set noreorder\n");
267 
268         for (i = 0; i < count; i++)
269                 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
270 
271         pr_debug("\t.set\tpop\n");
272 
273         pr_debug("\tEND(%s)\n", symbol);
274 }
275 
276 /* The only general purpose registers allowed in TLB handlers. */
277 #define K0              26
278 #define K1              27
279 
280 /* Some CP0 registers */
281 #define C0_INDEX        0, 0
282 #define C0_ENTRYLO0     2, 0
283 #define C0_TCBIND       2, 2
284 #define C0_ENTRYLO1     3, 0
285 #define C0_CONTEXT      4, 0
286 #define C0_PAGEMASK     5, 0
287 #define C0_PWBASE       5, 5
288 #define C0_PWFIELD      5, 6
289 #define C0_PWSIZE       5, 7
290 #define C0_PWCTL        6, 6
291 #define C0_BADVADDR     8, 0
292 #define C0_PGD          9, 7
293 #define C0_ENTRYHI      10, 0
294 #define C0_EPC          14, 0
295 #define C0_XCONTEXT     20, 0
296 
297 #ifdef CONFIG_64BIT
298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
299 #else
300 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
301 #endif
302 
303 /* The worst case length of the handler is around 18 instructions for
304  * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
305  * Maximum space available is 32 instructions for R3000 and 64
306  * instructions for R4000.
307  *
308  * We deliberately chose a buffer size of 128, so we won't scribble
309  * over anything important on overflow before we panic.
310  */
311 static u32 tlb_handler[128];
312 
313 /* simply assume worst case size for labels and relocs */
314 static struct uasm_label labels[128];
315 static struct uasm_reloc relocs[128];
316 
317 static int check_for_high_segbits;
318 static bool fill_includes_sw_bits;
319 
320 static unsigned int kscratch_used_mask;
321 
322 static inline int __maybe_unused c0_kscratch(void)
323 {
324         switch (current_cpu_type()) {
325         case CPU_XLP:
326         case CPU_XLR:
327                 return 22;
328         default:
329                 return 31;
330         }
331 }
332 
333 static int allocate_kscratch(void)
334 {
335         int r;
336         unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
337 
338         r = ffs(a);
339 
340         if (r == 0)
341                 return -1;
342 
343         r--; /* make it zero based */
344 
345         kscratch_used_mask |= (1 << r);
346 
347         return r;
348 }
349 
350 static int scratch_reg;
351 int pgd_reg;
352 EXPORT_SYMBOL_GPL(pgd_reg);
353 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
354 
355 static struct work_registers build_get_work_registers(u32 **p)
356 {
357         struct work_registers r;
358 
359         if (scratch_reg >= 0) {
360                 /* Save in CPU local C0_KScratch? */
361                 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
362                 r.r1 = K0;
363                 r.r2 = K1;
364                 r.r3 = 1;
365                 return r;
366         }
367 
368         if (num_possible_cpus() > 1) {
369                 /* Get smp_processor_id */
370                 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
371                 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
372 
373                 /* handler_reg_save index in K0 */
374                 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
375 
376                 UASM_i_LA(p, K1, (long)&handler_reg_save);
377                 UASM_i_ADDU(p, K0, K0, K1);
378         } else {
379                 UASM_i_LA(p, K0, (long)&handler_reg_save);
380         }
381         /* K0 now points to save area, save $1 and $2  */
382         UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
383         UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
384 
385         r.r1 = K1;
386         r.r2 = 1;
387         r.r3 = 2;
388         return r;
389 }
390 
391 static void build_restore_work_registers(u32 **p)
392 {
393         if (scratch_reg >= 0) {
394                 uasm_i_ehb(p);
395                 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
396                 return;
397         }
398         /* K0 already points to save area, restore $1 and $2  */
399         UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
400         UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
401 }
402 
403 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
404 
405 /*
406  * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
407  * we cannot do r3000 under these circumstances.
408  *
409  * The R3000 TLB handler is simple.
410  */
411 static void build_r3000_tlb_refill_handler(void)
412 {
413         long pgdc = (long)pgd_current;
414         u32 *p;
415 
416         memset(tlb_handler, 0, sizeof(tlb_handler));
417         p = tlb_handler;
418 
419         uasm_i_mfc0(&p, K0, C0_BADVADDR);
420         uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
421         uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
422         uasm_i_srl(&p, K0, K0, 22); /* load delay */
423         uasm_i_sll(&p, K0, K0, 2);
424         uasm_i_addu(&p, K1, K1, K0);
425         uasm_i_mfc0(&p, K0, C0_CONTEXT);
426         uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
427         uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
428         uasm_i_addu(&p, K1, K1, K0);
429         uasm_i_lw(&p, K0, 0, K1);
430         uasm_i_nop(&p); /* load delay */
431         uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
432         uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
433         uasm_i_tlbwr(&p); /* cp0 delay */
434         uasm_i_jr(&p, K1);
435         uasm_i_rfe(&p); /* branch delay */
436 
437         if (p > tlb_handler + 32)
438                 panic("TLB refill handler space exceeded");
439 
440         pr_debug("Wrote TLB refill handler (%u instructions).\n",
441                  (unsigned int)(p - tlb_handler));
442 
443         memcpy((void *)ebase, tlb_handler, 0x80);
444         local_flush_icache_range(ebase, ebase + 0x80);
445         dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80));
446 }
447 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
448 
449 /*
450  * The R4000 TLB handler is much more complicated. We have two
451  * consecutive handler areas with 32 instructions space each.
452  * Since they aren't used at the same time, we can overflow in the
453  * other one.To keep things simple, we first assume linear space,
454  * then we relocate it to the final handler layout as needed.
455  */
456 static u32 final_handler[64];
457 
458 /*
459  * Hazards
460  *
461  * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
462  * 2. A timing hazard exists for the TLBP instruction.
463  *
464  *      stalling_instruction
465  *      TLBP
466  *
467  * The JTLB is being read for the TLBP throughout the stall generated by the
468  * previous instruction. This is not really correct as the stalling instruction
469  * can modify the address used to access the JTLB.  The failure symptom is that
470  * the TLBP instruction will use an address created for the stalling instruction
471  * and not the address held in C0_ENHI and thus report the wrong results.
472  *
473  * The software work-around is to not allow the instruction preceding the TLBP
474  * to stall - make it an NOP or some other instruction guaranteed not to stall.
475  *
476  * Errata 2 will not be fixed.  This errata is also on the R5000.
477  *
478  * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
479  */
480 static void __maybe_unused build_tlb_probe_entry(u32 **p)
481 {
482         switch (current_cpu_type()) {
483         /* Found by experiment: R4600 v2.0/R4700 needs this, too.  */
484         case CPU_R4600:
485         case CPU_R4700:
486         case CPU_R5000:
487         case CPU_NEVADA:
488                 uasm_i_nop(p);
489                 uasm_i_tlbp(p);
490                 break;
491 
492         default:
493                 uasm_i_tlbp(p);
494                 break;
495         }
496 }
497 
498 void build_tlb_write_entry(u32 **p, struct uasm_label **l,
499                            struct uasm_reloc **r,
500                            enum tlb_write_entry wmode)
501 {
502         void(*tlbw)(u32 **) = NULL;
503 
504         switch (wmode) {
505         case tlb_random: tlbw = uasm_i_tlbwr; break;
506         case tlb_indexed: tlbw = uasm_i_tlbwi; break;
507         }
508 
509         if (cpu_has_mips_r2_r6) {
510                 if (cpu_has_mips_r2_exec_hazard)
511                         uasm_i_ehb(p);
512                 tlbw(p);
513                 return;
514         }
515 
516         switch (current_cpu_type()) {
517         case CPU_R4000PC:
518         case CPU_R4000SC:
519         case CPU_R4000MC:
520         case CPU_R4400PC:
521         case CPU_R4400SC:
522         case CPU_R4400MC:
523                 /*
524                  * This branch uses up a mtc0 hazard nop slot and saves
525                  * two nops after the tlbw instruction.
526                  */
527                 uasm_bgezl_hazard(p, r, hazard_instance);
528                 tlbw(p);
529                 uasm_bgezl_label(l, p, hazard_instance);
530                 hazard_instance++;
531                 uasm_i_nop(p);
532                 break;
533 
534         case CPU_R4600:
535         case CPU_R4700:
536                 uasm_i_nop(p);
537                 tlbw(p);
538                 uasm_i_nop(p);
539                 break;
540 
541         case CPU_R5000:
542         case CPU_NEVADA:
543                 uasm_i_nop(p); /* QED specifies 2 nops hazard */
544                 uasm_i_nop(p); /* QED specifies 2 nops hazard */
545                 tlbw(p);
546                 break;
547 
548         case CPU_R4300:
549         case CPU_5KC:
550         case CPU_TX49XX:
551         case CPU_PR4450:
552         case CPU_XLR:
553                 uasm_i_nop(p);
554                 tlbw(p);
555                 break;
556 
557         case CPU_R10000:
558         case CPU_R12000:
559         case CPU_R14000:
560         case CPU_R16000:
561         case CPU_4KC:
562         case CPU_4KEC:
563         case CPU_M14KC:
564         case CPU_M14KEC:
565         case CPU_SB1:
566         case CPU_SB1A:
567         case CPU_4KSC:
568         case CPU_20KC:
569         case CPU_25KF:
570         case CPU_BMIPS32:
571         case CPU_BMIPS3300:
572         case CPU_BMIPS4350:
573         case CPU_BMIPS4380:
574         case CPU_BMIPS5000:
575         case CPU_LOONGSON2:
576         case CPU_LOONGSON3:
577         case CPU_R5500:
578                 if (m4kc_tlbp_war())
579                         uasm_i_nop(p);
580                 /* fall through */
581         case CPU_ALCHEMY:
582                 tlbw(p);
583                 break;
584 
585         case CPU_RM7000:
586                 uasm_i_nop(p);
587                 uasm_i_nop(p);
588                 uasm_i_nop(p);
589                 uasm_i_nop(p);
590                 tlbw(p);
591                 break;
592 
593         case CPU_VR4111:
594         case CPU_VR4121:
595         case CPU_VR4122:
596         case CPU_VR4181:
597         case CPU_VR4181A:
598                 uasm_i_nop(p);
599                 uasm_i_nop(p);
600                 tlbw(p);
601                 uasm_i_nop(p);
602                 uasm_i_nop(p);
603                 break;
604 
605         case CPU_VR4131:
606         case CPU_VR4133:
607         case CPU_R5432:
608                 uasm_i_nop(p);
609                 uasm_i_nop(p);
610                 tlbw(p);
611                 break;
612 
613         case CPU_JZRISC:
614                 tlbw(p);
615                 uasm_i_nop(p);
616                 break;
617 
618         default:
619                 panic("No TLB refill handler yet (CPU type: %d)",
620                       current_cpu_type());
621                 break;
622         }
623 }
624 EXPORT_SYMBOL_GPL(build_tlb_write_entry);
625 
626 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
627                                                         unsigned int reg)
628 {
629         if (_PAGE_GLOBAL_SHIFT == 0) {
630                 /* pte_t is already in EntryLo format */
631                 return;
632         }
633 
634         if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
635                 if (fill_includes_sw_bits) {
636                         UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
637                 } else {
638                         UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
639                         UASM_i_ROTR(p, reg, reg,
640                                     ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
641                 }
642         } else {
643 #ifdef CONFIG_PHYS_ADDR_T_64BIT
644                 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
645 #else
646                 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
647 #endif
648         }
649 }
650 
651 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
652 
653 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
654                                    unsigned int tmp, enum label_id lid,
655                                    int restore_scratch)
656 {
657         if (restore_scratch) {
658                 /*
659                  * Ensure the MFC0 below observes the value written to the
660                  * KScratch register by the prior MTC0.
661                  */
662                 if (scratch_reg >= 0)
663                         uasm_i_ehb(p);
664 
665                 /* Reset default page size */
666                 if (PM_DEFAULT_MASK >> 16) {
667                         uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
668                         uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
669                         uasm_i_mtc0(p, tmp, C0_PAGEMASK);
670                         uasm_il_b(p, r, lid);
671                 } else if (PM_DEFAULT_MASK) {
672                         uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
673                         uasm_i_mtc0(p, tmp, C0_PAGEMASK);
674                         uasm_il_b(p, r, lid);
675                 } else {
676                         uasm_i_mtc0(p, 0, C0_PAGEMASK);
677                         uasm_il_b(p, r, lid);
678                 }
679                 if (scratch_reg >= 0)
680                         UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
681                 else
682                         UASM_i_LW(p, 1, scratchpad_offset(0), 0);
683         } else {
684                 /* Reset default page size */
685                 if (PM_DEFAULT_MASK >> 16) {
686                         uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
687                         uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
688                         uasm_il_b(p, r, lid);
689                         uasm_i_mtc0(p, tmp, C0_PAGEMASK);
690                 } else if (PM_DEFAULT_MASK) {
691                         uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
692                         uasm_il_b(p, r, lid);
693                         uasm_i_mtc0(p, tmp, C0_PAGEMASK);
694                 } else {
695                         uasm_il_b(p, r, lid);
696                         uasm_i_mtc0(p, 0, C0_PAGEMASK);
697                 }
698         }
699 }
700 
701 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
702                                        struct uasm_reloc **r,
703                                        unsigned int tmp,
704                                        enum tlb_write_entry wmode,
705                                        int restore_scratch)
706 {
707         /* Set huge page tlb entry size */
708         uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
709         uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
710         uasm_i_mtc0(p, tmp, C0_PAGEMASK);
711 
712         build_tlb_write_entry(p, l, r, wmode);
713 
714         build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
715 }
716 
717 /*
718  * Check if Huge PTE is present, if so then jump to LABEL.
719  */
720 static void
721 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
722                   unsigned int pmd, int lid)
723 {
724         UASM_i_LW(p, tmp, 0, pmd);
725         if (use_bbit_insns()) {
726                 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
727         } else {
728                 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
729                 uasm_il_bnez(p, r, tmp, lid);
730         }
731 }
732 
733 static void build_huge_update_entries(u32 **p, unsigned int pte,
734                                       unsigned int tmp)
735 {
736         int small_sequence;
737 
738         /*
739          * A huge PTE describes an area the size of the
740          * configured huge page size. This is twice the
741          * of the large TLB entry size we intend to use.
742          * A TLB entry half the size of the configured
743          * huge page size is configured into entrylo0
744          * and entrylo1 to cover the contiguous huge PTE
745          * address space.
746          */
747         small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
748 
749         /* We can clobber tmp.  It isn't used after this.*/
750         if (!small_sequence)
751                 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
752 
753         build_convert_pte_to_entrylo(p, pte);
754         UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
755         /* convert to entrylo1 */
756         if (small_sequence)
757                 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
758         else
759                 UASM_i_ADDU(p, pte, pte, tmp);
760 
761         UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
762 }
763 
764 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
765                                     struct uasm_label **l,
766                                     unsigned int pte,
767                                     unsigned int ptr,
768                                     unsigned int flush)
769 {
770 #ifdef CONFIG_SMP
771         UASM_i_SC(p, pte, 0, ptr);
772         uasm_il_beqz(p, r, pte, label_tlb_huge_update);
773         UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
774 #else
775         UASM_i_SW(p, pte, 0, ptr);
776 #endif
777         if (cpu_has_ftlb && flush) {
778                 BUG_ON(!cpu_has_tlbinv);
779 
780                 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
781                 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
782                 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
783                 build_tlb_write_entry(p, l, r, tlb_indexed);
784 
785                 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
786                 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
787                 build_huge_update_entries(p, pte, ptr);
788                 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
789 
790                 return;
791         }
792 
793         build_huge_update_entries(p, pte, ptr);
794         build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
795 }
796 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
797 
798 #ifdef CONFIG_64BIT
799 /*
800  * TMP and PTR are scratch.
801  * TMP will be clobbered, PTR will hold the pmd entry.
802  */
803 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
804                       unsigned int tmp, unsigned int ptr)
805 {
806 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
807         long pgdc = (long)pgd_current;
808 #endif
809         /*
810          * The vmalloc handling is not in the hotpath.
811          */
812         uasm_i_dmfc0(p, tmp, C0_BADVADDR);
813 
814         if (check_for_high_segbits) {
815                 /*
816                  * The kernel currently implicitely assumes that the
817                  * MIPS SEGBITS parameter for the processor is
818                  * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
819                  * allocate virtual addresses outside the maximum
820                  * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
821                  * that doesn't prevent user code from accessing the
822                  * higher xuseg addresses.  Here, we make sure that
823                  * everything but the lower xuseg addresses goes down
824                  * the module_alloc/vmalloc path.
825                  */
826                 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
827                 uasm_il_bnez(p, r, ptr, label_vmalloc);
828         } else {
829                 uasm_il_bltz(p, r, tmp, label_vmalloc);
830         }
831         /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
832 
833         if (pgd_reg != -1) {
834                 /* pgd is in pgd_reg */
835                 if (cpu_has_ldpte)
836                         UASM_i_MFC0(p, ptr, C0_PWBASE);
837                 else
838                         UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
839         } else {
840 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
841                 /*
842                  * &pgd << 11 stored in CONTEXT [23..63].
843                  */
844                 UASM_i_MFC0(p, ptr, C0_CONTEXT);
845 
846                 /* Clear lower 23 bits of context. */
847                 uasm_i_dins(p, ptr, 0, 0, 23);
848 
849                 /* 1 0  1 0 1  << 6  xkphys cached */
850                 uasm_i_ori(p, ptr, ptr, 0x540);
851                 uasm_i_drotr(p, ptr, ptr, 11);
852 #elif defined(CONFIG_SMP)
853                 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
854                 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
855                 UASM_i_LA_mostly(p, tmp, pgdc);
856                 uasm_i_daddu(p, ptr, ptr, tmp);
857                 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
858                 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
859 #else
860                 UASM_i_LA_mostly(p, ptr, pgdc);
861                 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
862 #endif
863         }
864 
865         uasm_l_vmalloc_done(l, *p);
866 
867         /* get pgd offset in bytes */
868         uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
869 
870         uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
871         uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
872 #ifndef __PAGETABLE_PUD_FOLDED
873         uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
874         uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
875         uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
876         uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
877         uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
878 #endif
879 #ifndef __PAGETABLE_PMD_FOLDED
880         uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
881         uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
882         uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
883         uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
884         uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
885 #endif
886 }
887 EXPORT_SYMBOL_GPL(build_get_pmde64);
888 
889 /*
890  * BVADDR is the faulting address, PTR is scratch.
891  * PTR will hold the pgd for vmalloc.
892  */
893 static void
894 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
895                         unsigned int bvaddr, unsigned int ptr,
896                         enum vmalloc64_mode mode)
897 {
898         long swpd = (long)swapper_pg_dir;
899         int single_insn_swpd;
900         int did_vmalloc_branch = 0;
901 
902         single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
903 
904         uasm_l_vmalloc(l, *p);
905 
906         if (mode != not_refill && check_for_high_segbits) {
907                 if (single_insn_swpd) {
908                         uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
909                         uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
910                         did_vmalloc_branch = 1;
911                         /* fall through */
912                 } else {
913                         uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
914                 }
915         }
916         if (!did_vmalloc_branch) {
917                 if (single_insn_swpd) {
918                         uasm_il_b(p, r, label_vmalloc_done);
919                         uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
920                 } else {
921                         UASM_i_LA_mostly(p, ptr, swpd);
922                         uasm_il_b(p, r, label_vmalloc_done);
923                         if (uasm_in_compat_space_p(swpd))
924                                 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
925                         else
926                                 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
927                 }
928         }
929         if (mode != not_refill && check_for_high_segbits) {
930                 uasm_l_large_segbits_fault(l, *p);
931 
932                 if (mode == refill_scratch && scratch_reg >= 0)
933                         uasm_i_ehb(p);
934 
935                 /*
936                  * We get here if we are an xsseg address, or if we are
937                  * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
938                  *
939                  * Ignoring xsseg (assume disabled so would generate
940                  * (address errors?), the only remaining possibility
941                  * is the upper xuseg addresses.  On processors with
942                  * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
943                  * addresses would have taken an address error. We try
944                  * to mimic that here by taking a load/istream page
945                  * fault.
946                  */
947                 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
948                         uasm_i_sync(p, 0);
949                 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
950                 uasm_i_jr(p, ptr);
951 
952                 if (mode == refill_scratch) {
953                         if (scratch_reg >= 0)
954                                 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
955                         else
956                                 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
957                 } else {
958                         uasm_i_nop(p);
959                 }
960         }
961 }
962 
963 #else /* !CONFIG_64BIT */
964 
965 /*
966  * TMP and PTR are scratch.
967  * TMP will be clobbered, PTR will hold the pgd entry.
968  */
969 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
970 {
971         if (pgd_reg != -1) {
972                 /* pgd is in pgd_reg */
973                 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
974                 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
975         } else {
976                 long pgdc = (long)pgd_current;
977 
978                 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
979 #ifdef CONFIG_SMP
980                 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
981                 UASM_i_LA_mostly(p, tmp, pgdc);
982                 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
983                 uasm_i_addu(p, ptr, tmp, ptr);
984 #else
985                 UASM_i_LA_mostly(p, ptr, pgdc);
986 #endif
987                 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
988                 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
989         }
990         uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
991         uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
992         uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
993 }
994 EXPORT_SYMBOL_GPL(build_get_pgde32);
995 
996 #endif /* !CONFIG_64BIT */
997 
998 static void build_adjust_context(u32 **p, unsigned int ctx)
999 {
1000         unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1001         unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1002 
1003         switch (current_cpu_type()) {
1004         case CPU_VR41XX:
1005         case CPU_VR4111:
1006         case CPU_VR4121:
1007         case CPU_VR4122:
1008         case CPU_VR4131:
1009         case CPU_VR4181:
1010         case CPU_VR4181A:
1011         case CPU_VR4133:
1012                 shift += 2;
1013                 break;
1014 
1015         default:
1016                 break;
1017         }
1018 
1019         if (shift)
1020                 UASM_i_SRL(p, ctx, ctx, shift);
1021         uasm_i_andi(p, ctx, ctx, mask);
1022 }
1023 
1024 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1025 {
1026         /*
1027          * Bug workaround for the Nevada. It seems as if under certain
1028          * circumstances the move from cp0_context might produce a
1029          * bogus result when the mfc0 instruction and its consumer are
1030          * in a different cacheline or a load instruction, probably any
1031          * memory reference, is between them.
1032          */
1033         switch (current_cpu_type()) {
1034         case CPU_NEVADA:
1035                 UASM_i_LW(p, ptr, 0, ptr);
1036                 GET_CONTEXT(p, tmp); /* get context reg */
1037                 break;
1038 
1039         default:
1040                 GET_CONTEXT(p, tmp); /* get context reg */
1041                 UASM_i_LW(p, ptr, 0, ptr);
1042                 break;
1043         }
1044 
1045         build_adjust_context(p, tmp);
1046         UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1047 }
1048 EXPORT_SYMBOL_GPL(build_get_ptep);
1049 
1050 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1051 {
1052         int pte_off_even = 0;
1053         int pte_off_odd = sizeof(pte_t);
1054 
1055 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1056         /* The low 32 bits of EntryLo is stored in pte_high */
1057         pte_off_even += offsetof(pte_t, pte_high);
1058         pte_off_odd += offsetof(pte_t, pte_high);
1059 #endif
1060 
1061         if (IS_ENABLED(CONFIG_XPA)) {
1062                 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1063                 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1064                 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1065 
1066                 if (cpu_has_xpa && !mips_xpa_disabled) {
1067                         uasm_i_lw(p, tmp, 0, ptep);
1068                         uasm_i_ext(p, tmp, tmp, 0, 24);
1069                         uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1070                 }
1071 
1072                 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1073                 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1074                 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1075 
1076                 if (cpu_has_xpa && !mips_xpa_disabled) {
1077                         uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1078                         uasm_i_ext(p, tmp, tmp, 0, 24);
1079                         uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1080                 }
1081                 return;
1082         }
1083 
1084         UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1085         UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1086         if (r45k_bvahwbug())
1087                 build_tlb_probe_entry(p);
1088         build_convert_pte_to_entrylo(p, tmp);
1089         if (r4k_250MHZhwbug())
1090                 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1091         UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1092         build_convert_pte_to_entrylo(p, ptep);
1093         if (r45k_bvahwbug())
1094                 uasm_i_mfc0(p, tmp, C0_INDEX);
1095         if (r4k_250MHZhwbug())
1096                 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1097         UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1098 }
1099 EXPORT_SYMBOL_GPL(build_update_entries);
1100 
1101 struct mips_huge_tlb_info {
1102         int huge_pte;
1103         int restore_scratch;
1104         bool need_reload_pte;
1105 };
1106 
1107 static struct mips_huge_tlb_info
1108 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1109                                struct uasm_reloc **r, unsigned int tmp,
1110                                unsigned int ptr, int c0_scratch_reg)
1111 {
1112         struct mips_huge_tlb_info rv;
1113         unsigned int even, odd;
1114         int vmalloc_branch_delay_filled = 0;
1115         const int scratch = 1; /* Our extra working register */
1116 
1117         rv.huge_pte = scratch;
1118         rv.restore_scratch = 0;
1119         rv.need_reload_pte = false;
1120 
1121         if (check_for_high_segbits) {
1122                 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1123 
1124                 if (pgd_reg != -1)
1125                         UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1126                 else
1127                         UASM_i_MFC0(p, ptr, C0_CONTEXT);
1128 
1129                 if (c0_scratch_reg >= 0)
1130                         UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1131                 else
1132                         UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1133 
1134                 uasm_i_dsrl_safe(p, scratch, tmp,
1135                                  PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1136                 uasm_il_bnez(p, r, scratch, label_vmalloc);
1137 
1138                 if (pgd_reg == -1) {
1139                         vmalloc_branch_delay_filled = 1;
1140                         /* Clear lower 23 bits of context. */
1141                         uasm_i_dins(p, ptr, 0, 0, 23);
1142                 }
1143         } else {
1144                 if (pgd_reg != -1)
1145                         UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1146                 else
1147                         UASM_i_MFC0(p, ptr, C0_CONTEXT);
1148 
1149                 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1150 
1151                 if (c0_scratch_reg >= 0)
1152                         UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1153                 else
1154                         UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1155 
1156                 if (pgd_reg == -1)
1157                         /* Clear lower 23 bits of context. */
1158                         uasm_i_dins(p, ptr, 0, 0, 23);
1159 
1160                 uasm_il_bltz(p, r, tmp, label_vmalloc);
1161         }
1162 
1163         if (pgd_reg == -1) {
1164                 vmalloc_branch_delay_filled = 1;
1165                 /* 1 0  1 0 1  << 6  xkphys cached */
1166                 uasm_i_ori(p, ptr, ptr, 0x540);
1167                 uasm_i_drotr(p, ptr, ptr, 11);
1168         }
1169 
1170 #ifdef __PAGETABLE_PMD_FOLDED
1171 #define LOC_PTEP scratch
1172 #else
1173 #define LOC_PTEP ptr
1174 #endif
1175 
1176         if (!vmalloc_branch_delay_filled)
1177                 /* get pgd offset in bytes */
1178                 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1179 
1180         uasm_l_vmalloc_done(l, *p);
1181 
1182         /*
1183          *                         tmp          ptr
1184          * fall-through case =   badvaddr  *pgd_current
1185          * vmalloc case      =   badvaddr  swapper_pg_dir
1186          */
1187 
1188         if (vmalloc_branch_delay_filled)
1189                 /* get pgd offset in bytes */
1190                 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1191 
1192 #ifdef __PAGETABLE_PMD_FOLDED
1193         GET_CONTEXT(p, tmp); /* get context reg */
1194 #endif
1195         uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1196 
1197         if (use_lwx_insns()) {
1198                 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1199         } else {
1200                 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1201                 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1202         }
1203 
1204 #ifndef __PAGETABLE_PUD_FOLDED
1205         /* get pud offset in bytes */
1206         uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
1207         uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
1208 
1209         if (use_lwx_insns()) {
1210                 UASM_i_LWX(p, ptr, scratch, ptr);
1211         } else {
1212                 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1213                 UASM_i_LW(p, ptr, 0, ptr);
1214         }
1215         /* ptr contains a pointer to PMD entry */
1216         /* tmp contains the address */
1217 #endif
1218 
1219 #ifndef __PAGETABLE_PMD_FOLDED
1220         /* get pmd offset in bytes */
1221         uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1222         uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1223         GET_CONTEXT(p, tmp); /* get context reg */
1224 
1225         if (use_lwx_insns()) {
1226                 UASM_i_LWX(p, scratch, scratch, ptr);
1227         } else {
1228                 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1229                 UASM_i_LW(p, scratch, 0, ptr);
1230         }
1231 #endif
1232         /* Adjust the context during the load latency. */
1233         build_adjust_context(p, tmp);
1234 
1235 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1236         uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1237         /*
1238          * The in the LWX case we don't want to do the load in the
1239          * delay slot.  It cannot issue in the same cycle and may be
1240          * speculative and unneeded.
1241          */
1242         if (use_lwx_insns())
1243                 uasm_i_nop(p);
1244 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1245 
1246 
1247         /* build_update_entries */
1248         if (use_lwx_insns()) {
1249                 even = ptr;
1250                 odd = tmp;
1251                 UASM_i_LWX(p, even, scratch, tmp);
1252                 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1253                 UASM_i_LWX(p, odd, scratch, tmp);
1254         } else {
1255                 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1256                 even = tmp;
1257                 odd = ptr;
1258                 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1259                 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1260         }
1261         if (cpu_has_rixi) {
1262                 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1263                 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1264                 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1265         } else {
1266                 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1267                 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1268                 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1269         }
1270         UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1271 
1272         if (c0_scratch_reg >= 0) {
1273                 uasm_i_ehb(p);
1274                 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1275                 build_tlb_write_entry(p, l, r, tlb_random);
1276                 uasm_l_leave(l, *p);
1277                 rv.restore_scratch = 1;
1278         } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13)  {
1279                 build_tlb_write_entry(p, l, r, tlb_random);
1280                 uasm_l_leave(l, *p);
1281                 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1282         } else {
1283                 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1284                 build_tlb_write_entry(p, l, r, tlb_random);
1285                 uasm_l_leave(l, *p);
1286                 rv.restore_scratch = 1;
1287         }
1288 
1289         uasm_i_eret(p); /* return from trap */
1290 
1291         return rv;
1292 }
1293 
1294 /*
1295  * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1296  * because EXL == 0.  If we wrap, we can also use the 32 instruction
1297  * slots before the XTLB refill exception handler which belong to the
1298  * unused TLB refill exception.
1299  */
1300 #define MIPS64_REFILL_INSNS 32
1301 
1302 static void build_r4000_tlb_refill_handler(void)
1303 {
1304         u32 *p = tlb_handler;
1305         struct uasm_label *l = labels;
1306         struct uasm_reloc *r = relocs;
1307         u32 *f;
1308         unsigned int final_len;
1309         struct mips_huge_tlb_info htlb_info __maybe_unused;
1310         enum vmalloc64_mode vmalloc_mode __maybe_unused;
1311 
1312         memset(tlb_handler, 0, sizeof(tlb_handler));
1313         memset(labels, 0, sizeof(labels));
1314         memset(relocs, 0, sizeof(relocs));
1315         memset(final_handler, 0, sizeof(final_handler));
1316 
1317         if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1318                 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1319                                                           scratch_reg);
1320                 vmalloc_mode = refill_scratch;
1321         } else {
1322                 htlb_info.huge_pte = K0;
1323                 htlb_info.restore_scratch = 0;
1324                 htlb_info.need_reload_pte = true;
1325                 vmalloc_mode = refill_noscratch;
1326                 /*
1327                  * create the plain linear handler
1328                  */
1329                 if (bcm1250_m3_war()) {
1330                         unsigned int segbits = 44;
1331 
1332                         uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1333                         uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1334                         uasm_i_xor(&p, K0, K0, K1);
1335                         uasm_i_dsrl_safe(&p, K1, K0, 62);
1336                         uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1337                         uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1338                         uasm_i_or(&p, K0, K0, K1);
1339                         uasm_il_bnez(&p, &r, K0, label_leave);
1340                         /* No need for uasm_i_nop */
1341                 }
1342 
1343 #ifdef CONFIG_64BIT
1344                 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1345 #else
1346                 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1347 #endif
1348 
1349 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1350                 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1351 #endif
1352 
1353                 build_get_ptep(&p, K0, K1);
1354                 build_update_entries(&p, K0, K1);
1355                 build_tlb_write_entry(&p, &l, &r, tlb_random);
1356                 uasm_l_leave(&l, p);
1357                 uasm_i_eret(&p); /* return from trap */
1358         }
1359 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1360         uasm_l_tlb_huge_update(&l, p);
1361         if (htlb_info.need_reload_pte)
1362                 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1363         build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1364         build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1365                                    htlb_info.restore_scratch);
1366 #endif
1367 
1368 #ifdef CONFIG_64BIT
1369         build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1370 #endif
1371 
1372         /*
1373          * Overflow check: For the 64bit handler, we need at least one
1374          * free instruction slot for the wrap-around branch. In worst
1375          * case, if the intended insertion point is a delay slot, we
1376          * need three, with the second nop'ed and the third being
1377          * unused.
1378          */
1379         switch (boot_cpu_type()) {
1380         default:
1381                 if (sizeof(long) == 4) {
1382         case CPU_LOONGSON2:
1383                 /* Loongson2 ebase is different than r4k, we have more space */
1384                         if ((p - tlb_handler) > 64)
1385                                 panic("TLB refill handler space exceeded");
1386                         /*
1387                          * Now fold the handler in the TLB refill handler space.
1388                          */
1389                         f = final_handler;
1390                         /* Simplest case, just copy the handler. */
1391                         uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1392                         final_len = p - tlb_handler;
1393                         break;
1394                 } else {
1395                         if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1396                             || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1397                                 && uasm_insn_has_bdelay(relocs,
1398                                                         tlb_handler + MIPS64_REFILL_INSNS - 3)))
1399                                 panic("TLB refill handler space exceeded");
1400                         /*
1401                          * Now fold the handler in the TLB refill handler space.
1402                          */
1403                         f = final_handler + MIPS64_REFILL_INSNS;
1404                         if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1405                                 /* Just copy the handler. */
1406                                 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1407                                 final_len = p - tlb_handler;
1408                         } else {
1409 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1410                                 const enum label_id ls = label_tlb_huge_update;
1411 #else
1412                                 const enum label_id ls = label_vmalloc;
1413 #endif
1414                                 u32 *split;
1415                                 int ov = 0;
1416                                 int i;
1417 
1418                                 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1419                                         ;
1420                                 BUG_ON(i == ARRAY_SIZE(labels));
1421                                 split = labels[i].addr;
1422 
1423                                 /*
1424                                  * See if we have overflown one way or the other.
1425                                  */
1426                                 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1427                                     split < p - MIPS64_REFILL_INSNS)
1428                                         ov = 1;
1429 
1430                                 if (ov) {
1431                                         /*
1432                                          * Split two instructions before the end.  One
1433                                          * for the branch and one for the instruction
1434                                          * in the delay slot.
1435                                          */
1436                                         split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1437 
1438                                         /*
1439                                          * If the branch would fall in a delay slot,
1440                                          * we must back up an additional instruction
1441                                          * so that it is no longer in a delay slot.
1442                                          */
1443                                         if (uasm_insn_has_bdelay(relocs, split - 1))
1444                                                 split--;
1445                                 }
1446                                 /* Copy first part of the handler. */
1447                                 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1448                                 f += split - tlb_handler;
1449 
1450                                 if (ov) {
1451                                         /* Insert branch. */
1452                                         uasm_l_split(&l, final_handler);
1453                                         uasm_il_b(&f, &r, label_split);
1454                                         if (uasm_insn_has_bdelay(relocs, split))
1455                                                 uasm_i_nop(&f);
1456                                         else {
1457                                                 uasm_copy_handler(relocs, labels,
1458                                                                   split, split + 1, f);
1459                                                 uasm_move_labels(labels, f, f + 1, -1);
1460                                                 f++;
1461                                                 split++;
1462                                         }
1463                                 }
1464 
1465                                 /* Copy the rest of the handler. */
1466                                 uasm_copy_handler(relocs, labels, split, p, final_handler);
1467                                 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1468                                             (p - split);
1469                         }
1470                 }
1471                 break;
1472         }
1473 
1474         uasm_resolve_relocs(relocs, labels);
1475         pr_debug("Wrote TLB refill handler (%u instructions).\n",
1476                  final_len);
1477 
1478         memcpy((void *)ebase, final_handler, 0x100);
1479         local_flush_icache_range(ebase, ebase + 0x100);
1480         dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100));
1481 }
1482 
1483 static void setup_pw(void)
1484 {
1485         unsigned long pgd_i, pgd_w;
1486 #ifndef __PAGETABLE_PMD_FOLDED
1487         unsigned long pmd_i, pmd_w;
1488 #endif
1489         unsigned long pt_i, pt_w;
1490         unsigned long pte_i, pte_w;
1491 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1492         unsigned long psn;
1493 
1494         psn = ilog2(_PAGE_HUGE);     /* bit used to indicate huge page */
1495 #endif
1496         pgd_i = PGDIR_SHIFT;  /* 1st level PGD */
1497 #ifndef __PAGETABLE_PMD_FOLDED
1498         pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1499 
1500         pmd_i = PMD_SHIFT;    /* 2nd level PMD */
1501         pmd_w = PMD_SHIFT - PAGE_SHIFT;
1502 #else
1503         pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1504 #endif
1505 
1506         pt_i  = PAGE_SHIFT;    /* 3rd level PTE */
1507         pt_w  = PAGE_SHIFT - 3;
1508 
1509         pte_i = ilog2(_PAGE_GLOBAL);
1510         pte_w = 0;
1511 
1512 #ifndef __PAGETABLE_PMD_FOLDED
1513         write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1514         write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1515 #else
1516         write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1517         write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1518 #endif
1519 
1520 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1521         write_c0_pwctl(1 << 6 | psn);
1522 #endif
1523         write_c0_kpgd((long)swapper_pg_dir);
1524         kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1525 }
1526 
1527 static void build_loongson3_tlb_refill_handler(void)
1528 {
1529         u32 *p = tlb_handler;
1530         struct uasm_label *l = labels;
1531         struct uasm_reloc *r = relocs;
1532 
1533         memset(labels, 0, sizeof(labels));
1534         memset(relocs, 0, sizeof(relocs));
1535         memset(tlb_handler, 0, sizeof(tlb_handler));
1536 
1537         if (check_for_high_segbits) {
1538                 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1539                 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1540                 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1541                 uasm_i_nop(&p);
1542 
1543                 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1544                 uasm_i_nop(&p);
1545                 uasm_l_vmalloc(&l, p);
1546         }
1547 
1548         uasm_i_dmfc0(&p, K1, C0_PGD);
1549 
1550         uasm_i_lddir(&p, K0, K1, 3);  /* global page dir */
1551 #ifndef __PAGETABLE_PMD_FOLDED
1552         uasm_i_lddir(&p, K1, K0, 1);  /* middle page dir */
1553 #endif
1554         uasm_i_ldpte(&p, K1, 0);      /* even */
1555         uasm_i_ldpte(&p, K1, 1);      /* odd */
1556         uasm_i_tlbwr(&p);
1557 
1558         /* restore page mask */
1559         if (PM_DEFAULT_MASK >> 16) {
1560                 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1561                 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1562                 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1563         } else if (PM_DEFAULT_MASK) {
1564                 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1565                 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1566         } else {
1567                 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1568         }
1569 
1570         uasm_i_eret(&p);
1571 
1572         if (check_for_high_segbits) {
1573                 uasm_l_large_segbits_fault(&l, p);
1574                 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1575                 uasm_i_jr(&p, K1);
1576                 uasm_i_nop(&p);
1577         }
1578 
1579         uasm_resolve_relocs(relocs, labels);
1580         memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1581         local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1582         dump_handler("loongson3_tlb_refill",
1583                      (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100));
1584 }
1585 
1586 static void build_setup_pgd(void)
1587 {
1588         const int a0 = 4;
1589         const int __maybe_unused a1 = 5;
1590         const int __maybe_unused a2 = 6;
1591         u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd);
1592 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1593         long pgdc = (long)pgd_current;
1594 #endif
1595 
1596         memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p);
1597         memset(labels, 0, sizeof(labels));
1598         memset(relocs, 0, sizeof(relocs));
1599         pgd_reg = allocate_kscratch();
1600 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1601         if (pgd_reg == -1) {
1602                 struct uasm_label *l = labels;
1603                 struct uasm_reloc *r = relocs;
1604 
1605                 /* PGD << 11 in c0_Context */
1606                 /*
1607                  * If it is a ckseg0 address, convert to a physical
1608                  * address.  Shifting right by 29 and adding 4 will
1609                  * result in zero for these addresses.
1610                  *
1611                  */
1612                 UASM_i_SRA(&p, a1, a0, 29);
1613                 UASM_i_ADDIU(&p, a1, a1, 4);
1614                 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1615                 uasm_i_nop(&p);
1616                 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1617                 uasm_l_tlbl_goaround1(&l, p);
1618                 UASM_i_SLL(&p, a0, a0, 11);
1619                 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1620                 uasm_i_jr(&p, 31);
1621                 uasm_i_ehb(&p);
1622         } else {
1623                 /* PGD in c0_KScratch */
1624                 if (cpu_has_ldpte)
1625                         UASM_i_MTC0(&p, a0, C0_PWBASE);
1626                 else
1627                         UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1628                 uasm_i_jr(&p, 31);
1629                 uasm_i_ehb(&p);
1630         }
1631 #else
1632 #ifdef CONFIG_SMP
1633         /* Save PGD to pgd_current[smp_processor_id()] */
1634         UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1635         UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1636         UASM_i_LA_mostly(&p, a2, pgdc);
1637         UASM_i_ADDU(&p, a2, a2, a1);
1638         UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1639 #else
1640         UASM_i_LA_mostly(&p, a2, pgdc);
1641         UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1642 #endif /* SMP */
1643 
1644         /* if pgd_reg is allocated, save PGD also to scratch register */
1645         if (pgd_reg != -1) {
1646                 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1647                 uasm_i_jr(&p, 31);
1648                 uasm_i_ehb(&p);
1649         } else {
1650                 uasm_i_jr(&p, 31);
1651                 uasm_i_nop(&p);
1652         }
1653 #endif
1654         if (p >= (u32 *)tlbmiss_handler_setup_pgd_end)
1655                 panic("tlbmiss_handler_setup_pgd space exceeded");
1656 
1657         uasm_resolve_relocs(relocs, labels);
1658         pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1659                  (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd));
1660 
1661         dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1662                                         tlbmiss_handler_setup_pgd_end);
1663 }
1664 
1665 static void
1666 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1667 {
1668 #ifdef CONFIG_SMP
1669         if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
1670                 uasm_i_sync(p, 0);
1671 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1672         if (cpu_has_64bits)
1673                 uasm_i_lld(p, pte, 0, ptr);
1674         else
1675 # endif
1676                 UASM_i_LL(p, pte, 0, ptr);
1677 #else
1678 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1679         if (cpu_has_64bits)
1680                 uasm_i_ld(p, pte, 0, ptr);
1681         else
1682 # endif
1683                 UASM_i_LW(p, pte, 0, ptr);
1684 #endif
1685 }
1686 
1687 static void
1688 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1689         unsigned int mode, unsigned int scratch)
1690 {
1691         unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1692         unsigned int swmode = mode & ~hwmode;
1693 
1694         if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
1695                 uasm_i_lui(p, scratch, swmode >> 16);
1696                 uasm_i_or(p, pte, pte, scratch);
1697                 BUG_ON(swmode & 0xffff);
1698         } else {
1699                 uasm_i_ori(p, pte, pte, mode);
1700         }
1701 
1702 #ifdef CONFIG_SMP
1703 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1704         if (cpu_has_64bits)
1705                 uasm_i_scd(p, pte, 0, ptr);
1706         else
1707 # endif
1708                 UASM_i_SC(p, pte, 0, ptr);
1709 
1710         if (r10000_llsc_war())
1711                 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1712         else
1713                 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1714 
1715 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1716         if (!cpu_has_64bits) {
1717                 /* no uasm_i_nop needed */
1718                 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1719                 uasm_i_ori(p, pte, pte, hwmode);
1720                 BUG_ON(hwmode & ~0xffff);
1721                 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1722                 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1723                 /* no uasm_i_nop needed */
1724                 uasm_i_lw(p, pte, 0, ptr);
1725         } else
1726                 uasm_i_nop(p);
1727 # else
1728         uasm_i_nop(p);
1729 # endif
1730 #else
1731 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1732         if (cpu_has_64bits)
1733                 uasm_i_sd(p, pte, 0, ptr);
1734         else
1735 # endif
1736                 UASM_i_SW(p, pte, 0, ptr);
1737 
1738 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1739         if (!cpu_has_64bits) {
1740                 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1741                 uasm_i_ori(p, pte, pte, hwmode);
1742                 BUG_ON(hwmode & ~0xffff);
1743                 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1744                 uasm_i_lw(p, pte, 0, ptr);
1745         }
1746 # endif
1747 #endif
1748 }
1749 
1750 /*
1751  * Check if PTE is present, if not then jump to LABEL. PTR points to
1752  * the page table where this PTE is located, PTE will be re-loaded
1753  * with it's original value.
1754  */
1755 static void
1756 build_pte_present(u32 **p, struct uasm_reloc **r,
1757                   int pte, int ptr, int scratch, enum label_id lid)
1758 {
1759         int t = scratch >= 0 ? scratch : pte;
1760         int cur = pte;
1761 
1762         if (cpu_has_rixi) {
1763                 if (use_bbit_insns()) {
1764                         uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1765                         uasm_i_nop(p);
1766                 } else {
1767                         if (_PAGE_PRESENT_SHIFT) {
1768                                 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1769                                 cur = t;
1770                         }
1771                         uasm_i_andi(p, t, cur, 1);
1772                         uasm_il_beqz(p, r, t, lid);
1773                         if (pte == t)
1774                                 /* You lose the SMP race :-(*/
1775                                 iPTE_LW(p, pte, ptr);
1776                 }
1777         } else {
1778                 if (_PAGE_PRESENT_SHIFT) {
1779                         uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1780                         cur = t;
1781                 }
1782                 uasm_i_andi(p, t, cur,
1783                         (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1784                 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
1785                 uasm_il_bnez(p, r, t, lid);
1786                 if (pte == t)
1787                         /* You lose the SMP race :-(*/
1788                         iPTE_LW(p, pte, ptr);
1789         }
1790 }
1791 
1792 /* Make PTE valid, store result in PTR. */
1793 static void
1794 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1795                  unsigned int ptr, unsigned int scratch)
1796 {
1797         unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1798 
1799         iPTE_SW(p, r, pte, ptr, mode, scratch);
1800 }
1801 
1802 /*
1803  * Check if PTE can be written to, if not branch to LABEL. Regardless
1804  * restore PTE with value from PTR when done.
1805  */
1806 static void
1807 build_pte_writable(u32 **p, struct uasm_reloc **r,
1808                    unsigned int pte, unsigned int ptr, int scratch,
1809                    enum label_id lid)
1810 {
1811         int t = scratch >= 0 ? scratch : pte;
1812         int cur = pte;
1813 
1814         if (_PAGE_PRESENT_SHIFT) {
1815                 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1816                 cur = t;
1817         }
1818         uasm_i_andi(p, t, cur,
1819                     (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1820         uasm_i_xori(p, t, t,
1821                     (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1822         uasm_il_bnez(p, r, t, lid);
1823         if (pte == t)
1824                 /* You lose the SMP race :-(*/
1825                 iPTE_LW(p, pte, ptr);
1826         else
1827                 uasm_i_nop(p);
1828 }
1829 
1830 /* Make PTE writable, update software status bits as well, then store
1831  * at PTR.
1832  */
1833 static void
1834 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1835                  unsigned int ptr, unsigned int scratch)
1836 {
1837         unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1838                              | _PAGE_DIRTY);
1839 
1840         iPTE_SW(p, r, pte, ptr, mode, scratch);
1841 }
1842 
1843 /*
1844  * Check if PTE can be modified, if not branch to LABEL. Regardless
1845  * restore PTE with value from PTR when done.
1846  */
1847 static void
1848 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1849                      unsigned int pte, unsigned int ptr, int scratch,
1850                      enum label_id lid)
1851 {
1852         if (use_bbit_insns()) {
1853                 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1854                 uasm_i_nop(p);
1855         } else {
1856                 int t = scratch >= 0 ? scratch : pte;
1857                 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1858                 uasm_i_andi(p, t, t, 1);
1859                 uasm_il_beqz(p, r, t, lid);
1860                 if (pte == t)
1861                         /* You lose the SMP race :-(*/
1862                         iPTE_LW(p, pte, ptr);
1863         }
1864 }
1865 
1866 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1867 
1868 
1869 /*
1870  * R3000 style TLB load/store/modify handlers.
1871  */
1872 
1873 /*
1874  * This places the pte into ENTRYLO0 and writes it with tlbwi.
1875  * Then it returns.
1876  */
1877 static void
1878 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1879 {
1880         uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1881         uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1882         uasm_i_tlbwi(p);
1883         uasm_i_jr(p, tmp);
1884         uasm_i_rfe(p); /* branch delay */
1885 }
1886 
1887 /*
1888  * This places the pte into ENTRYLO0 and writes it with tlbwi
1889  * or tlbwr as appropriate.  This is because the index register
1890  * may have the probe fail bit set as a result of a trap on a
1891  * kseg2 access, i.e. without refill.  Then it returns.
1892  */
1893 static void
1894 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1895                              struct uasm_reloc **r, unsigned int pte,
1896                              unsigned int tmp)
1897 {
1898         uasm_i_mfc0(p, tmp, C0_INDEX);
1899         uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1900         uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1901         uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1902         uasm_i_tlbwi(p); /* cp0 delay */
1903         uasm_i_jr(p, tmp);
1904         uasm_i_rfe(p); /* branch delay */
1905         uasm_l_r3000_write_probe_fail(l, *p);
1906         uasm_i_tlbwr(p); /* cp0 delay */
1907         uasm_i_jr(p, tmp);
1908         uasm_i_rfe(p); /* branch delay */
1909 }
1910 
1911 static void
1912 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1913                                    unsigned int ptr)
1914 {
1915         long pgdc = (long)pgd_current;
1916 
1917         uasm_i_mfc0(p, pte, C0_BADVADDR);
1918         uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1919         uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1920         uasm_i_srl(p, pte, pte, 22); /* load delay */
1921         uasm_i_sll(p, pte, pte, 2);
1922         uasm_i_addu(p, ptr, ptr, pte);
1923         uasm_i_mfc0(p, pte, C0_CONTEXT);
1924         uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1925         uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1926         uasm_i_addu(p, ptr, ptr, pte);
1927         uasm_i_lw(p, pte, 0, ptr);
1928         uasm_i_tlbp(p); /* load delay */
1929 }
1930 
1931 static void build_r3000_tlb_load_handler(void)
1932 {
1933         u32 *p = (u32 *)handle_tlbl;
1934         struct uasm_label *l = labels;
1935         struct uasm_reloc *r = relocs;
1936 
1937         memset(p, 0, handle_tlbl_end - (char *)p);
1938         memset(labels, 0, sizeof(labels));
1939         memset(relocs, 0, sizeof(relocs));
1940 
1941         build_r3000_tlbchange_handler_head(&p, K0, K1);
1942         build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1943         uasm_i_nop(&p); /* load delay */
1944         build_make_valid(&p, &r, K0, K1, -1);
1945         build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1946 
1947         uasm_l_nopage_tlbl(&l, p);
1948         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1949         uasm_i_nop(&p);
1950 
1951         if (p >= (u32 *)handle_tlbl_end)
1952                 panic("TLB load handler fastpath space exceeded");
1953 
1954         uasm_resolve_relocs(relocs, labels);
1955         pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1956                  (unsigned int)(p - (u32 *)handle_tlbl));
1957 
1958         dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end);
1959 }
1960 
1961 static void build_r3000_tlb_store_handler(void)
1962 {
1963         u32 *p = (u32 *)handle_tlbs;
1964         struct uasm_label *l = labels;
1965         struct uasm_reloc *r = relocs;
1966 
1967         memset(p, 0, handle_tlbs_end - (char *)p);
1968         memset(labels, 0, sizeof(labels));
1969         memset(relocs, 0, sizeof(relocs));
1970 
1971         build_r3000_tlbchange_handler_head(&p, K0, K1);
1972         build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1973         uasm_i_nop(&p); /* load delay */
1974         build_make_write(&p, &r, K0, K1, -1);
1975         build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1976 
1977         uasm_l_nopage_tlbs(&l, p);
1978         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1979         uasm_i_nop(&p);
1980 
1981         if (p >= (u32 *)handle_tlbs_end)
1982                 panic("TLB store handler fastpath space exceeded");
1983 
1984         uasm_resolve_relocs(relocs, labels);
1985         pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1986                  (unsigned int)(p - (u32 *)handle_tlbs));
1987 
1988         dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end);
1989 }
1990 
1991 static void build_r3000_tlb_modify_handler(void)
1992 {
1993         u32 *p = (u32 *)handle_tlbm;
1994         struct uasm_label *l = labels;
1995         struct uasm_reloc *r = relocs;
1996 
1997         memset(p, 0, handle_tlbm_end - (char *)p);
1998         memset(labels, 0, sizeof(labels));
1999         memset(relocs, 0, sizeof(relocs));
2000 
2001         build_r3000_tlbchange_handler_head(&p, K0, K1);
2002         build_pte_modifiable(&p, &r, K0, K1,  -1, label_nopage_tlbm);
2003         uasm_i_nop(&p); /* load delay */
2004         build_make_write(&p, &r, K0, K1, -1);
2005         build_r3000_pte_reload_tlbwi(&p, K0, K1);
2006 
2007         uasm_l_nopage_tlbm(&l, p);
2008         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2009         uasm_i_nop(&p);
2010 
2011         if (p >= (u32 *)handle_tlbm_end)
2012                 panic("TLB modify handler fastpath space exceeded");
2013 
2014         uasm_resolve_relocs(relocs, labels);
2015         pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2016                  (unsigned int)(p - (u32 *)handle_tlbm));
2017 
2018         dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end);
2019 }
2020 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
2021 
2022 static bool cpu_has_tlbex_tlbp_race(void)
2023 {
2024         /*
2025          * When a Hardware Table Walker is running it can replace TLB entries
2026          * at any time, leading to a race between it & the CPU.
2027          */
2028         if (cpu_has_htw)
2029                 return true;
2030 
2031         /*
2032          * If the CPU shares FTLB RAM with its siblings then our entry may be
2033          * replaced at any time by a sibling performing a write to the FTLB.
2034          */
2035         if (cpu_has_shared_ftlb_ram)
2036                 return true;
2037 
2038         /* In all other cases there ought to be no race condition to handle */
2039         return false;
2040 }
2041 
2042 /*
2043  * R4000 style TLB load/store/modify handlers.
2044  */
2045 static struct work_registers
2046 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
2047                                    struct uasm_reloc **r)
2048 {
2049         struct work_registers wr = build_get_work_registers(p);
2050 
2051 #ifdef CONFIG_64BIT
2052         build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
2053 #else
2054         build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
2055 #endif
2056 
2057 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2058         /*
2059          * For huge tlb entries, pmd doesn't contain an address but
2060          * instead contains the tlb pte. Check the PAGE_HUGE bit and
2061          * see if we need to jump to huge tlb processing.
2062          */
2063         build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
2064 #endif
2065 
2066         UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2067         UASM_i_LW(p, wr.r2, 0, wr.r2);
2068         UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2069         uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2070         UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
2071 
2072 #ifdef CONFIG_SMP
2073         uasm_l_smp_pgtable_change(l, *p);
2074 #endif
2075         iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2076         if (!m4kc_tlbp_war()) {
2077                 build_tlb_probe_entry(p);
2078                 if (cpu_has_tlbex_tlbp_race()) {
2079                         /* race condition happens, leaving */
2080                         uasm_i_ehb(p);
2081                         uasm_i_mfc0(p, wr.r3, C0_INDEX);
2082                         uasm_il_bltz(p, r, wr.r3, label_leave);
2083                         uasm_i_nop(p);
2084                 }
2085         }
2086         return wr;
2087 }
2088 
2089 static void
2090 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2091                                    struct uasm_reloc **r, unsigned int tmp,
2092                                    unsigned int ptr)
2093 {
2094         uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2095         uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
2096         build_update_entries(p, tmp, ptr);
2097         build_tlb_write_entry(p, l, r, tlb_indexed);
2098         uasm_l_leave(l, *p);
2099         build_restore_work_registers(p);
2100         uasm_i_eret(p); /* return from trap */
2101 
2102 #ifdef CONFIG_64BIT
2103         build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
2104 #endif
2105 }
2106 
2107 static void build_r4000_tlb_load_handler(void)
2108 {
2109         u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
2110         struct uasm_label *l = labels;
2111         struct uasm_reloc *r = relocs;
2112         struct work_registers wr;
2113 
2114         memset(p, 0, handle_tlbl_end - (char *)p);
2115         memset(labels, 0, sizeof(labels));
2116         memset(relocs, 0, sizeof(relocs));
2117 
2118         if (bcm1250_m3_war()) {
2119                 unsigned int segbits = 44;
2120 
2121                 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2122                 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
2123                 uasm_i_xor(&p, K0, K0, K1);
2124                 uasm_i_dsrl_safe(&p, K1, K0, 62);
2125                 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2126                 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
2127                 uasm_i_or(&p, K0, K0, K1);
2128                 uasm_il_bnez(&p, &r, K0, label_leave);
2129                 /* No need for uasm_i_nop */
2130         }
2131 
2132         wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2133         build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2134         if (m4kc_tlbp_war())
2135                 build_tlb_probe_entry(&p);
2136 
2137         if (cpu_has_rixi && !cpu_has_rixiex) {
2138                 /*
2139                  * If the page is not _PAGE_VALID, RI or XI could not
2140                  * have triggered it.  Skip the expensive test..
2141                  */
2142                 if (use_bbit_insns()) {
2143                         uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2144                                       label_tlbl_goaround1);
2145                 } else {
2146                         uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2147                         uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
2148                 }
2149                 uasm_i_nop(&p);
2150 
2151                 /*
2152                  * Warn if something may race with us & replace the TLB entry
2153                  * before we read it here. Everything with such races should
2154                  * also have dedicated RiXi exception handlers, so this
2155                  * shouldn't be hit.
2156                  */
2157                 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2158 
2159                 uasm_i_tlbr(&p);
2160 
2161                 switch (current_cpu_type()) {
2162                 default:
2163                         if (cpu_has_mips_r2_exec_hazard) {
2164                                 uasm_i_ehb(&p);
2165 
2166                 case CPU_CAVIUM_OCTEON:
2167                 case CPU_CAVIUM_OCTEON_PLUS:
2168                 case CPU_CAVIUM_OCTEON2:
2169                                 break;
2170                         }
2171                 }
2172 
2173                 /* Examine  entrylo 0 or 1 based on ptr. */
2174                 if (use_bbit_insns()) {
2175                         uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2176                 } else {
2177                         uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2178                         uasm_i_beqz(&p, wr.r3, 8);
2179                 }
2180                 /* load it in the delay slot*/
2181                 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2182                 /* load it if ptr is odd */
2183                 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2184                 /*
2185                  * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2186                  * XI must have triggered it.
2187                  */
2188                 if (use_bbit_insns()) {
2189                         uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2190                         uasm_i_nop(&p);
2191                         uasm_l_tlbl_goaround1(&l, p);
2192                 } else {
2193                         uasm_i_andi(&p, wr.r3, wr.r3, 2);
2194                         uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2195                         uasm_i_nop(&p);
2196                 }
2197                 uasm_l_tlbl_goaround1(&l, p);
2198         }
2199         build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
2200         build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2201 
2202 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2203         /*
2204          * This is the entry point when build_r4000_tlbchange_handler_head
2205          * spots a huge page.
2206          */
2207         uasm_l_tlb_huge_update(&l, p);
2208         iPTE_LW(&p, wr.r1, wr.r2);
2209         build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2210         build_tlb_probe_entry(&p);
2211 
2212         if (cpu_has_rixi && !cpu_has_rixiex) {
2213                 /*
2214                  * If the page is not _PAGE_VALID, RI or XI could not
2215                  * have triggered it.  Skip the expensive test..
2216                  */
2217                 if (use_bbit_insns()) {
2218                         uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2219                                       label_tlbl_goaround2);
2220                 } else {
2221                         uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2222                         uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2223                 }
2224                 uasm_i_nop(&p);
2225 
2226                 /*
2227                  * Warn if something may race with us & replace the TLB entry
2228                  * before we read it here. Everything with such races should
2229                  * also have dedicated RiXi exception handlers, so this
2230                  * shouldn't be hit.
2231                  */
2232                 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2233 
2234                 uasm_i_tlbr(&p);
2235 
2236                 switch (current_cpu_type()) {
2237                 default:
2238                         if (cpu_has_mips_r2_exec_hazard) {
2239                                 uasm_i_ehb(&p);
2240 
2241                 case CPU_CAVIUM_OCTEON:
2242                 case CPU_CAVIUM_OCTEON_PLUS:
2243                 case CPU_CAVIUM_OCTEON2:
2244                                 break;
2245                         }
2246                 }
2247 
2248                 /* Examine  entrylo 0 or 1 based on ptr. */
2249                 if (use_bbit_insns()) {
2250                         uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2251                 } else {
2252                         uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2253                         uasm_i_beqz(&p, wr.r3, 8);
2254                 }
2255                 /* load it in the delay slot*/
2256                 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2257                 /* load it if ptr is odd */
2258                 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2259                 /*
2260                  * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2261                  * XI must have triggered it.
2262                  */
2263                 if (use_bbit_insns()) {
2264                         uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2265                 } else {
2266                         uasm_i_andi(&p, wr.r3, wr.r3, 2);
2267                         uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2268                 }
2269                 if (PM_DEFAULT_MASK == 0)
2270                         uasm_i_nop(&p);
2271                 /*
2272                  * We clobbered C0_PAGEMASK, restore it.  On the other branch
2273                  * it is restored in build_huge_tlb_write_entry.
2274                  */
2275                 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2276 
2277                 uasm_l_tlbl_goaround2(&l, p);
2278         }
2279         uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2280         build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2281 #endif
2282 
2283         uasm_l_nopage_tlbl(&l, p);
2284         if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2285                 uasm_i_sync(&p, 0);
2286         build_restore_work_registers(&p);
2287 #ifdef CONFIG_CPU_MICROMIPS
2288         if ((unsigned long)tlb_do_page_fault_0 & 1) {
2289                 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2290                 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2291                 uasm_i_jr(&p, K0);
2292         } else
2293 #endif
2294         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2295         uasm_i_nop(&p);
2296 
2297         if (p >= (u32 *)handle_tlbl_end)
2298                 panic("TLB load handler fastpath space exceeded");
2299 
2300         uasm_resolve_relocs(relocs, labels);
2301         pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2302                  (unsigned int)(p - (u32 *)handle_tlbl));
2303 
2304         dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end);
2305 }
2306 
2307 static void build_r4000_tlb_store_handler(void)
2308 {
2309         u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
2310         struct uasm_label *l = labels;
2311         struct uasm_reloc *r = relocs;
2312         struct work_registers wr;
2313 
2314         memset(p, 0, handle_tlbs_end - (char *)p);
2315         memset(labels, 0, sizeof(labels));
2316         memset(relocs, 0, sizeof(relocs));
2317 
2318         wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2319         build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2320         if (m4kc_tlbp_war())
2321                 build_tlb_probe_entry(&p);
2322         build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2323         build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2324 
2325 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2326         /*
2327          * This is the entry point when
2328          * build_r4000_tlbchange_handler_head spots a huge page.
2329          */
2330         uasm_l_tlb_huge_update(&l, p);
2331         iPTE_LW(&p, wr.r1, wr.r2);
2332         build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2333         build_tlb_probe_entry(&p);
2334         uasm_i_ori(&p, wr.r1, wr.r1,
2335                    _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2336         build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2337 #endif
2338 
2339         uasm_l_nopage_tlbs(&l, p);
2340         if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2341                 uasm_i_sync(&p, 0);
2342         build_restore_work_registers(&p);
2343 #ifdef CONFIG_CPU_MICROMIPS
2344         if ((unsigned long)tlb_do_page_fault_1 & 1) {
2345                 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2346                 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2347                 uasm_i_jr(&p, K0);
2348         } else
2349 #endif
2350         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2351         uasm_i_nop(&p);
2352 
2353         if (p >= (u32 *)handle_tlbs_end)
2354                 panic("TLB store handler fastpath space exceeded");
2355 
2356         uasm_resolve_relocs(relocs, labels);
2357         pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2358                  (unsigned int)(p - (u32 *)handle_tlbs));
2359 
2360         dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end);
2361 }
2362 
2363 static void build_r4000_tlb_modify_handler(void)
2364 {
2365         u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
2366         struct uasm_label *l = labels;
2367         struct uasm_reloc *r = relocs;
2368         struct work_registers wr;
2369 
2370         memset(p, 0, handle_tlbm_end - (char *)p);
2371         memset(labels, 0, sizeof(labels));
2372         memset(relocs, 0, sizeof(relocs));
2373 
2374         wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2375         build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2376         if (m4kc_tlbp_war())
2377                 build_tlb_probe_entry(&p);
2378         /* Present and writable bits set, set accessed and dirty bits. */
2379         build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2380         build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2381 
2382 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2383         /*
2384          * This is the entry point when
2385          * build_r4000_tlbchange_handler_head spots a huge page.
2386          */
2387         uasm_l_tlb_huge_update(&l, p);
2388         iPTE_LW(&p, wr.r1, wr.r2);
2389         build_pte_modifiable(&p, &r, wr.r1, wr.r2,  wr.r3, label_nopage_tlbm);
2390         build_tlb_probe_entry(&p);
2391         uasm_i_ori(&p, wr.r1, wr.r1,
2392                    _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2393         build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
2394 #endif
2395 
2396         uasm_l_nopage_tlbm(&l, p);
2397         if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
2398                 uasm_i_sync(&p, 0);
2399         build_restore_work_registers(&p);
2400 #ifdef CONFIG_CPU_MICROMIPS
2401         if ((unsigned long)tlb_do_page_fault_1 & 1) {
2402                 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2403                 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2404                 uasm_i_jr(&p, K0);
2405         } else
2406 #endif
2407         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2408         uasm_i_nop(&p);
2409 
2410         if (p >= (u32 *)handle_tlbm_end)
2411                 panic("TLB modify handler fastpath space exceeded");
2412 
2413         uasm_resolve_relocs(relocs, labels);
2414         pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2415                  (unsigned int)(p - (u32 *)handle_tlbm));
2416 
2417         dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end);
2418 }
2419 
2420 static void flush_tlb_handlers(void)
2421 {
2422         local_flush_icache_range((unsigned long)handle_tlbl,
2423                            (unsigned long)handle_tlbl_end);
2424         local_flush_icache_range((unsigned long)handle_tlbs,
2425                            (unsigned long)handle_tlbs_end);
2426         local_flush_icache_range((unsigned long)handle_tlbm,
2427                            (unsigned long)handle_tlbm_end);
2428         local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2429                            (unsigned long)tlbmiss_handler_setup_pgd_end);
2430 }
2431 
2432 static void print_htw_config(void)
2433 {
2434         unsigned long config;
2435         unsigned int pwctl;
2436         const int field = 2 * sizeof(unsigned long);
2437 
2438         config = read_c0_pwfield();
2439         pr_debug("PWField (0x%0*lx): GDI: 0x%02lx  UDI: 0x%02lx  MDI: 0x%02lx  PTI: 0x%02lx  PTEI: 0x%02lx\n",
2440                 field, config,
2441                 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2442                 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2443                 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2444                 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2445                 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2446 
2447         config = read_c0_pwsize();
2448         pr_debug("PWSize  (0x%0*lx): PS: 0x%lx  GDW: 0x%02lx  UDW: 0x%02lx  MDW: 0x%02lx  PTW: 0x%02lx  PTEW: 0x%02lx\n",
2449                 field, config,
2450                 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2451                 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2452                 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2453                 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2454                 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2455                 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2456 
2457         pwctl = read_c0_pwctl();
2458         pr_debug("PWCtl   (0x%x): PWEn: 0x%x  XK: 0x%x  XS: 0x%x  XU: 0x%x  DPH: 0x%x  HugePg: 0x%x  Psn: 0x%x\n",
2459                 pwctl,
2460                 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2461                 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2462                 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2463                 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2464                 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2465                 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2466                 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2467 }
2468 
2469 static void config_htw_params(void)
2470 {
2471         unsigned long pwfield, pwsize, ptei;
2472         unsigned int config;
2473 
2474         /*
2475          * We are using 2-level page tables, so we only need to
2476          * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2477          * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2478          * write values less than 0xc in these fields because the entire
2479          * write will be dropped. As a result of which, we must preserve
2480          * the original reset values and overwrite only what we really want.
2481          */
2482 
2483         pwfield = read_c0_pwfield();
2484         /* re-initialize the GDI field */
2485         pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2486         pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2487         /* re-initialize the PTI field including the even/odd bit */
2488         pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2489         pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2490         if (CONFIG_PGTABLE_LEVELS >= 3) {
2491                 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2492                 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2493         }
2494         /* Set the PTEI right shift */
2495         ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2496         pwfield |= ptei;
2497         write_c0_pwfield(pwfield);
2498         /* Check whether the PTEI value is supported */
2499         back_to_back_c0_hazard();
2500         pwfield = read_c0_pwfield();
2501         if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2502                 != ptei) {
2503                 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2504                         ptei);
2505                 /*
2506                  * Drop option to avoid HTW being enabled via another path
2507                  * (eg htw_reset())
2508                  */
2509                 current_cpu_data.options &= ~MIPS_CPU_HTW;
2510                 return;
2511         }
2512 
2513         pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2514         pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2515         if (CONFIG_PGTABLE_LEVELS >= 3)
2516                 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2517 
2518         /* Set pointer size to size of directory pointers */
2519         if (IS_ENABLED(CONFIG_64BIT))
2520                 pwsize |= MIPS_PWSIZE_PS_MASK;
2521         /* PTEs may be multiple pointers long (e.g. with XPA) */
2522         pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2523                         & MIPS_PWSIZE_PTEW_MASK;
2524 
2525         write_c0_pwsize(pwsize);
2526 
2527         /* Make sure everything is set before we enable the HTW */
2528         back_to_back_c0_hazard();
2529 
2530         /*
2531          * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2532          * the pwctl fields.
2533          */
2534         config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2535         if (IS_ENABLED(CONFIG_64BIT))
2536                 config |= MIPS_PWCTL_XU_MASK;
2537         write_c0_pwctl(config);
2538         pr_info("Hardware Page Table Walker enabled\n");
2539 
2540         print_htw_config();
2541 }
2542 
2543 static void config_xpa_params(void)
2544 {
2545 #ifdef CONFIG_XPA
2546         unsigned int pagegrain;
2547 
2548         if (mips_xpa_disabled) {
2549                 pr_info("Extended Physical Addressing (XPA) disabled\n");
2550                 return;
2551         }
2552 
2553         pagegrain = read_c0_pagegrain();
2554         write_c0_pagegrain(pagegrain | PG_ELPA);
2555         back_to_back_c0_hazard();
2556         pagegrain = read_c0_pagegrain();
2557 
2558         if (pagegrain & PG_ELPA)
2559                 pr_info("Extended Physical Addressing (XPA) enabled\n");
2560         else
2561                 panic("Extended Physical Addressing (XPA) disabled");
2562 #endif
2563 }
2564 
2565 static void check_pabits(void)
2566 {
2567         unsigned long entry;
2568         unsigned pabits, fillbits;
2569 
2570         if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2571                 /*
2572                  * We'll only be making use of the fact that we can rotate bits
2573                  * into the fill if the CPU supports RIXI, so don't bother
2574                  * probing this for CPUs which don't.
2575                  */
2576                 return;
2577         }
2578 
2579         write_c0_entrylo0(~0ul);
2580         back_to_back_c0_hazard();
2581         entry = read_c0_entrylo0();
2582 
2583         /* clear all non-PFN bits */
2584         entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2585         entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2586 
2587         /* find a lower bound on PABITS, and upper bound on fill bits */
2588         pabits = fls_long(entry) + 6;
2589         fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2590 
2591         /* minus the RI & XI bits */
2592         fillbits -= min_t(unsigned, fillbits, 2);
2593 
2594         if (fillbits >= ilog2(_PAGE_NO_EXEC))
2595                 fill_includes_sw_bits = true;
2596 
2597         pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2598 }
2599 
2600 void build_tlb_refill_handler(void)
2601 {
2602         /*
2603          * The refill handler is generated per-CPU, multi-node systems
2604          * may have local storage for it. The other handlers are only
2605          * needed once.
2606          */
2607         static int run_once = 0;
2608 
2609         if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
2610                 panic("Kernels supporting XPA currently require CPUs with RIXI");
2611 
2612         output_pgtable_bits_defines();
2613         check_pabits();
2614 
2615 #ifdef CONFIG_64BIT
2616         check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2617 #endif
2618 
2619         switch (current_cpu_type()) {
2620         case CPU_R2000:
2621         case CPU_R3000:
2622         case CPU_R3000A:
2623         case CPU_R3081E:
2624         case CPU_TX3912:
2625         case CPU_TX3922:
2626         case CPU_TX3927:
2627 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2628                 if (cpu_has_local_ebase)
2629                         build_r3000_tlb_refill_handler();
2630                 if (!run_once) {
2631                         if (!cpu_has_local_ebase)
2632                                 build_r3000_tlb_refill_handler();
2633                         build_setup_pgd();
2634                         build_r3000_tlb_load_handler();
2635                         build_r3000_tlb_store_handler();
2636                         build_r3000_tlb_modify_handler();
2637                         flush_tlb_handlers();
2638                         run_once++;
2639                 }
2640 #else
2641                 panic("No R3000 TLB refill handler");
2642 #endif
2643                 break;
2644 
2645         case CPU_R8000:
2646                 panic("No R8000 TLB refill handler yet");
2647                 break;
2648 
2649         default:
2650                 if (cpu_has_ldpte)
2651                         setup_pw();
2652 
2653                 if (!run_once) {
2654                         scratch_reg = allocate_kscratch();
2655                         build_setup_pgd();
2656                         build_r4000_tlb_load_handler();
2657                         build_r4000_tlb_store_handler();
2658                         build_r4000_tlb_modify_handler();
2659                         if (cpu_has_ldpte)
2660                                 build_loongson3_tlb_refill_handler();
2661                         else if (!cpu_has_local_ebase)
2662                                 build_r4000_tlb_refill_handler();
2663                         flush_tlb_handlers();
2664                         run_once++;
2665                 }
2666                 if (cpu_has_local_ebase)
2667                         build_r4000_tlb_refill_handler();
2668                 if (cpu_has_xpa)
2669                         config_xpa_params();
2670                 if (cpu_has_htw)
2671                         config_htw_params();
2672         }
2673 }
2674 

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