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Linux/arch/mips/netlogic/xlp/wakeup.c

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  1 /*
  2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3  * reserved.
  4  *
  5  * This software is available to you under a choice of one of two
  6  * licenses.  You may choose to be licensed under the terms of the GNU
  7  * General Public License (GPL) Version 2, available from the file
  8  * COPYING in the main directory of this source tree, or the NetLogic
  9  * license below:
 10  *
 11  * Redistribution and use in source and binary forms, with or without
 12  * modification, are permitted provided that the following conditions
 13  * are met:
 14  *
 15  * 1. Redistributions of source code must retain the above copyright
 16  *    notice, this list of conditions and the following disclaimer.
 17  * 2. Redistributions in binary form must reproduce the above copyright
 18  *    notice, this list of conditions and the following disclaimer in
 19  *    the documentation and/or other materials provided with the
 20  *    distribution.
 21  *
 22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33  */
 34 
 35 #include <linux/kernel.h>
 36 #include <linux/threads.h>
 37 
 38 #include <asm/asm.h>
 39 #include <asm/asm-offsets.h>
 40 #include <asm/mipsregs.h>
 41 #include <asm/addrspace.h>
 42 #include <asm/string.h>
 43 
 44 #include <asm/netlogic/haldefs.h>
 45 #include <asm/netlogic/common.h>
 46 #include <asm/netlogic/mips-extns.h>
 47 
 48 #include <asm/netlogic/xlp-hal/iomap.h>
 49 #include <asm/netlogic/xlp-hal/xlp.h>
 50 #include <asm/netlogic/xlp-hal/pic.h>
 51 #include <asm/netlogic/xlp-hal/sys.h>
 52 
 53 static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
 54 {
 55         uint32_t coremask, value;
 56         int count, resetreg;
 57 
 58         coremask = (1 << core);
 59 
 60         /* Enable CPU clock in case of 8xx/3xx */
 61         if (!cpu_is_xlpii()) {
 62                 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
 63                 value &= ~coremask;
 64                 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
 65         }
 66 
 67         /* On 9XX, mark coherent first */
 68         if (cpu_is_xlp9xx()) {
 69                 value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
 70                 value &= ~coremask;
 71                 nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
 72         }
 73 
 74         /* Remove CPU Reset */
 75         resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
 76         value = nlm_read_sys_reg(sysbase, resetreg);
 77         value &= ~coremask;
 78         nlm_write_sys_reg(sysbase, resetreg, value);
 79 
 80         /* We are done on 9XX */
 81         if (cpu_is_xlp9xx())
 82                 return 1;
 83 
 84         /* Poll for CPU to mark itself coherent on other type of XLP */
 85         count = 100000;
 86         do {
 87                 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
 88         } while ((value & coremask) != 0 && --count > 0);
 89 
 90         return count != 0;
 91 }
 92 
 93 static int wait_for_cpus(int cpu, int bootcpu)
 94 {
 95         volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
 96         int i, count, notready;
 97 
 98         count = 0x800000;
 99         do {
100                 notready = nlm_threads_per_core;
101                 for (i = 0; i < nlm_threads_per_core; i++)
102                         if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
103                                 --notready;
104         } while (notready != 0 && --count > 0);
105 
106         return count != 0;
107 }
108 
109 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
110 {
111         struct nlm_soc_info *nodep;
112         uint64_t syspcibase, fusebase;
113         uint32_t syscoremask, mask, fusemask;
114         int core, n, cpu, ncores;
115 
116         for (n = 0; n < NLM_NR_NODES; n++) {
117                 if (n != 0) {
118                         /* check if node exists and is online */
119                         if (cpu_is_xlp9xx()) {
120                                 int b = xlp9xx_get_socbus(n);
121                                 pr_info("Node %d SoC PCI bus %d.\n", n, b);
122                                 if (b == 0)
123                                         break;
124                         } else {
125                                 syspcibase = nlm_get_sys_pcibase(n);
126                                 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
127                                         break;
128                         }
129                         nlm_node_init(n);
130                 }
131 
132                 /* read cores in reset from SYS */
133                 nodep = nlm_get_node(n);
134 
135                 if (cpu_is_xlp9xx()) {
136                         fusebase = nlm_get_fuse_regbase(n);
137                         fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
138                         switch (read_c0_prid() & PRID_IMP_MASK) {
139                         case PRID_IMP_NETLOGIC_XLP5XX:
140                                 mask = 0xff;
141                                 break;
142                         case PRID_IMP_NETLOGIC_XLP9XX:
143                         default:
144                                 mask = 0xfffff;
145                                 break;
146                         }
147                 } else {
148                         fusemask = nlm_read_sys_reg(nodep->sysbase,
149                                                 SYS_EFUSE_DEVICE_CFG_STATUS0);
150                         switch (read_c0_prid() & PRID_IMP_MASK) {
151                         case PRID_IMP_NETLOGIC_XLP3XX:
152                                 mask = 0xf;
153                                 break;
154                         case PRID_IMP_NETLOGIC_XLP2XX:
155                                 mask = 0x3;
156                                 break;
157                         case PRID_IMP_NETLOGIC_XLP8XX:
158                         default:
159                                 mask = 0xff;
160                                 break;
161                         }
162                 }
163 
164                 /*
165                  * Fused out cores are set in the fusemask, and the remaining
166                  * cores are renumbered to range 0 .. nactive-1
167                  */
168                 syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
169 
170                 pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
171                 ncores = nlm_cores_per_node();
172                 for (core = 0; core < ncores; core++) {
173                         /* we will be on node 0 core 0 */
174                         if (n == 0 && core == 0)
175                                 continue;
176 
177                         /* see if the core exists */
178                         if ((syscoremask & (1 << core)) == 0)
179                                 continue;
180 
181                         /* see if at least the first hw thread is enabled */
182                         cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
183                         if (!cpumask_test_cpu(cpu, wakeup_mask))
184                                 continue;
185 
186                         /* wake up the core */
187                         if (!xlp_wakeup_core(nodep->sysbase, n, core))
188                                 continue;
189 
190                         /* core is up */
191                         nodep->coremask |= 1u << core;
192 
193                         /* spin until the hw threads sets their ready */
194                         if (!wait_for_cpus(cpu, 0))
195                                 pr_err("Node %d : timeout core %d\n", n, core);
196                 }
197         }
198 }
199 
200 void xlp_wakeup_secondary_cpus(void)
201 {
202         /*
203          * In case of u-boot, the secondaries are in reset
204          * first wakeup core 0 threads
205          */
206         xlp_boot_core0_siblings();
207         if (!wait_for_cpus(0, 0))
208                 pr_err("Node 0 : timeout core 0\n");
209 
210         /* now get other cores out of reset */
211         xlp_enable_secondary_cores(&nlm_cpumask);
212 }
213 

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