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Linux/arch/mips/netlogic/xlr/platform-flash.c

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  1 /*
  2  * Copyright 2011, Netlogic Microsystems.
  3  * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  4  *
  5  * This file is licensed under the terms of the GNU General Public
  6  * License version 2.  This program is licensed "as is" without any
  7  * warranty of any kind, whether express or implied.
  8  */
  9 
 10 #include <linux/device.h>
 11 #include <linux/platform_device.h>
 12 #include <linux/kernel.h>
 13 #include <linux/init.h>
 14 #include <linux/io.h>
 15 #include <linux/delay.h>
 16 #include <linux/ioport.h>
 17 #include <linux/resource.h>
 18 #include <linux/spi/flash.h>
 19 
 20 #include <linux/mtd/mtd.h>
 21 #include <linux/mtd/physmap.h>
 22 #include <linux/mtd/nand.h>
 23 #include <linux/mtd/partitions.h>
 24 
 25 #include <asm/netlogic/haldefs.h>
 26 #include <asm/netlogic/xlr/iomap.h>
 27 #include <asm/netlogic/xlr/flash.h>
 28 #include <asm/netlogic/xlr/bridge.h>
 29 #include <asm/netlogic/xlr/gpio.h>
 30 #include <asm/netlogic/xlr/xlr.h>
 31 
 32 /*
 33  * Default NOR partition layout
 34  */
 35 static struct mtd_partition xlr_nor_parts[] = {
 36         {
 37                 .name = "User FS",
 38                 .offset = 0x800000,
 39                 .size   = MTDPART_SIZ_FULL,
 40         }
 41 };
 42 
 43 /*
 44  * Default NAND partition layout
 45  */
 46 static struct mtd_partition xlr_nand_parts[] = {
 47         {
 48                 .name   = "Root Filesystem",
 49                 .offset = 64 * 64 * 2048,
 50                 .size   = 432 * 64 * 2048,
 51         },
 52         {
 53                 .name   = "Home Filesystem",
 54                 .offset = MTDPART_OFS_APPEND,
 55                 .size   = MTDPART_SIZ_FULL,
 56         },
 57 };
 58 
 59 /* Use PHYSMAP flash for NOR */
 60 struct physmap_flash_data xlr_nor_data = {
 61         .width          = 2,
 62         .parts          = xlr_nor_parts,
 63         .nr_parts       = ARRAY_SIZE(xlr_nor_parts),
 64 };
 65 
 66 static struct resource xlr_nor_res[] = {
 67         {
 68                 .flags  = IORESOURCE_MEM,
 69         },
 70 };
 71 
 72 static struct platform_device xlr_nor_dev = {
 73         .name   = "physmap-flash",
 74         .dev    = {
 75                 .platform_data  = &xlr_nor_data,
 76         },
 77         .num_resources  = ARRAY_SIZE(xlr_nor_res),
 78         .resource       = xlr_nor_res,
 79 };
 80 
 81 /*
 82  * Use "gen_nand" driver for NAND flash
 83  *
 84  * There seems to be no way to store a private pointer containing
 85  * platform specific info in gen_nand drivier. We will use a global
 86  * struct for now, since we currently have only one NAND chip per board.
 87  */
 88 struct xlr_nand_flash_priv {
 89         int cs;
 90         uint64_t flash_mmio;
 91 };
 92 
 93 static struct xlr_nand_flash_priv nand_priv;
 94 
 95 static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
 96                 unsigned int ctrl)
 97 {
 98         if (ctrl & NAND_CLE)
 99                 nlm_write_reg(nand_priv.flash_mmio,
100                         FLASH_NAND_CLE(nand_priv.cs), cmd);
101         else if (ctrl & NAND_ALE)
102                 nlm_write_reg(nand_priv.flash_mmio,
103                         FLASH_NAND_ALE(nand_priv.cs), cmd);
104 }
105 
106 struct platform_nand_data xlr_nand_data = {
107         .chip = {
108                 .nr_chips       = 1,
109                 .nr_partitions  = ARRAY_SIZE(xlr_nand_parts),
110                 .chip_delay     = 50,
111                 .partitions     = xlr_nand_parts,
112         },
113         .ctrl = {
114                 .cmd_ctrl       = xlr_nand_ctrl,
115         },
116 };
117 
118 static struct resource xlr_nand_res[] = {
119         {
120                 .flags          = IORESOURCE_MEM,
121         },
122 };
123 
124 static struct platform_device xlr_nand_dev = {
125         .name           = "gen_nand",
126         .id             = -1,
127         .num_resources  = ARRAY_SIZE(xlr_nand_res),
128         .resource       = xlr_nand_res,
129         .dev            = {
130                 .platform_data  = &xlr_nand_data,
131         }
132 };
133 
134 /*
135  * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
136  * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
137  * flash devices.
138  * Under this, each flash device has an offset and size given by the
139  * CSBASE_ADDR and CSBASE_MASK registers for the device.
140  *
141  * The CSBASE_ registers are expected to be setup by the bootloader.
142  */
143 static void setup_flash_resource(uint64_t flash_mmio,
144         uint64_t flash_map_base, int cs, struct resource *res)
145 {
146         u32 base, mask;
147 
148         base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
149         mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
150 
151         res->start = flash_map_base + ((unsigned long)base << 16);
152         res->end = res->start + (mask + 1) * 64 * 1024;
153 }
154 
155 static int __init xlr_flash_init(void)
156 {
157         uint64_t gpio_mmio, flash_mmio, flash_map_base;
158         u32 gpio_resetcfg, flash_bar;
159         int cs, boot_nand, boot_nor;
160 
161         /* Flash address bits 39:24 is in bridge flash BAR */
162         flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
163         flash_map_base = (flash_bar & 0xffff0000) << 8;
164 
165         gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
166         flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
167 
168         /* Get the chip reset config */
169         gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
170 
171         /* Check for boot flash type */
172         boot_nor = boot_nand = 0;
173         if (nlm_chip_is_xls()) {
174                 /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
175                 if (gpio_resetcfg & (1 << 16))
176                         boot_nand = 1;
177 
178                 /* check boot from PCMCIA, (GPIO reset reg bit 15 */
179                 if ((gpio_resetcfg & (1 << 15)) == 0)
180                         boot_nor = 1;   /* not set, booted from NOR */
181         } else { /* XLR */
182                 /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
183                 if ((gpio_resetcfg & (1 << 16)) == 0)
184                         boot_nor = 1;   /* not set, booted from NOR */
185         }
186 
187         /* boot flash at chip select 0 */
188         cs = 0;
189 
190         if (boot_nand) {
191                 nand_priv.cs = cs;
192                 nand_priv.flash_mmio = flash_mmio;
193                 setup_flash_resource(flash_mmio, flash_map_base, cs,
194                          xlr_nand_res);
195 
196                 /* Initialize NAND flash at CS 0 */
197                 nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
198                                 FLASH_NAND_CSDEV_PARAM);
199                 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
200                                 FLASH_NAND_CSTIME_PARAMA);
201                 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
202                                 FLASH_NAND_CSTIME_PARAMB);
203 
204                 pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
205                 return platform_device_register(&xlr_nand_dev);
206         }
207 
208         if (boot_nor) {
209                 setup_flash_resource(flash_mmio, flash_map_base, cs,
210                         xlr_nor_res);
211                 pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
212                 return platform_device_register(&xlr_nor_dev);
213         }
214         return 0;
215 }
216 
217 arch_initcall(xlr_flash_init);
218 

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