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TOMOYO Linux Cross Reference
Linux/arch/mips/pci/pci-octeon.c

Version: ~ [ linux-4.14 ] ~ [ linux-4.13.12 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.61 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.97 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.46 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.80 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.50 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.95 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.27.62 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2005-2009 Cavium Networks
  7  */
  8 #include <linux/kernel.h>
  9 #include <linux/init.h>
 10 #include <linux/pci.h>
 11 #include <linux/interrupt.h>
 12 #include <linux/time.h>
 13 #include <linux/delay.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/swiotlb.h>
 16 
 17 #include <asm/time.h>
 18 
 19 #include <asm/octeon/octeon.h>
 20 #include <asm/octeon/cvmx-npi-defs.h>
 21 #include <asm/octeon/cvmx-pci-defs.h>
 22 #include <asm/octeon/pci-octeon.h>
 23 
 24 #include <dma-coherence.h>
 25 
 26 #define USE_OCTEON_INTERNAL_ARBITER
 27 
 28 /*
 29  * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
 30  * addresses. Use PCI endian swapping 1 so no address swapping is
 31  * necessary. The Linux io routines will endian swap the data.
 32  */
 33 #define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
 34 #define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
 35 
 36 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 37 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
 38 
 39 u64 octeon_bar1_pci_phys;
 40 
 41 /**
 42  * This is the bit decoding used for the Octeon PCI controller addresses
 43  */
 44 union octeon_pci_address {
 45         uint64_t u64;
 46         struct {
 47                 uint64_t upper:2;
 48                 uint64_t reserved:13;
 49                 uint64_t io:1;
 50                 uint64_t did:5;
 51                 uint64_t subdid:3;
 52                 uint64_t reserved2:4;
 53                 uint64_t endian_swap:2;
 54                 uint64_t reserved3:10;
 55                 uint64_t bus:8;
 56                 uint64_t dev:5;
 57                 uint64_t func:3;
 58                 uint64_t reg:8;
 59         } s;
 60 };
 61 
 62 int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
 63 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
 64 
 65 /**
 66  * Map a PCI device to the appropriate interrupt line
 67  *
 68  * @dev:    The Linux PCI device structure for the device to map
 69  * @slot:   The slot number for this device on __BUS 0__. Linux
 70  *               enumerates through all the bridges and figures out the
 71  *               slot on Bus 0 where this device eventually hooks to.
 72  * @pin:    The PCI interrupt pin read from the device, then swizzled
 73  *               as it goes through each bridge.
 74  * Returns Interrupt number for the device
 75  */
 76 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 77 {
 78         if (octeon_pcibios_map_irq)
 79                 return octeon_pcibios_map_irq(dev, slot, pin);
 80         else
 81                 panic("octeon_pcibios_map_irq not set.");
 82 }
 83 
 84 
 85 /*
 86  * Called to perform platform specific PCI setup
 87  */
 88 int pcibios_plat_dev_init(struct pci_dev *dev)
 89 {
 90         uint16_t config;
 91         uint32_t dconfig;
 92         int pos;
 93         /*
 94          * Force the Cache line setting to 64 bytes. The standard
 95          * Linux bus scan doesn't seem to set it. Octeon really has
 96          * 128 byte lines, but Intel bridges get really upset if you
 97          * try and set values above 64 bytes. Value is specified in
 98          * 32bit words.
 99          */
100         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
101         /* Set latency timers for all devices */
102         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
103 
104         /* Enable reporting System errors and parity errors on all devices */
105         /* Enable parity checking and error reporting */
106         pci_read_config_word(dev, PCI_COMMAND, &config);
107         config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
108         pci_write_config_word(dev, PCI_COMMAND, config);
109 
110         if (dev->subordinate) {
111                 /* Set latency timers on sub bridges */
112                 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
113                 /* More bridge error detection */
114                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
115                 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
116                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
117         }
118 
119         /* Enable the PCIe normal error reporting */
120         config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
121         config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
122         config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
123         config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
124         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
125 
126         /* Find the Advanced Error Reporting capability */
127         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
128         if (pos) {
129                 /* Clear Uncorrectable Error Status */
130                 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
131                                       &dconfig);
132                 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
133                                        dconfig);
134                 /* Enable reporting of all uncorrectable errors */
135                 /* Uncorrectable Error Mask - turned on bits disable errors */
136                 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
137                 /*
138                  * Leave severity at HW default. This only controls if
139                  * errors are reported as uncorrectable or
140                  * correctable, not if the error is reported.
141                  */
142                 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
143                 /* Clear Correctable Error Status */
144                 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
145                 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
146                 /* Enable reporting of all correctable errors */
147                 /* Correctable Error Mask - turned on bits disable errors */
148                 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
149                 /* Advanced Error Capabilities */
150                 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
151                 /* ECRC Generation Enable */
152                 if (config & PCI_ERR_CAP_ECRC_GENC)
153                         config |= PCI_ERR_CAP_ECRC_GENE;
154                 /* ECRC Check Enable */
155                 if (config & PCI_ERR_CAP_ECRC_CHKC)
156                         config |= PCI_ERR_CAP_ECRC_CHKE;
157                 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
158                 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
159                 /* Report all errors to the root complex */
160                 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
161                                        PCI_ERR_ROOT_CMD_COR_EN |
162                                        PCI_ERR_ROOT_CMD_NONFATAL_EN |
163                                        PCI_ERR_ROOT_CMD_FATAL_EN);
164                 /* Clear the Root status register */
165                 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
166                 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
167         }
168 
169         dev->dev.dma_ops = octeon_pci_dma_map_ops;
170 
171         return 0;
172 }
173 
174 /**
175  * Return the mapping of PCI device number to IRQ line. Each
176  * character in the return string represents the interrupt
177  * line for the device at that position. Device 1 maps to the
178  * first character, etc. The characters A-D are used for PCI
179  * interrupts.
180  *
181  * Returns PCI interrupt mapping
182  */
183 const char *octeon_get_pci_interrupts(void)
184 {
185         /*
186          * Returning an empty string causes the interrupts to be
187          * routed based on the PCI specification. From the PCI spec:
188          *
189          * INTA# of Device Number 0 is connected to IRQW on the system
190          * board.  (Device Number has no significance regarding being
191          * located on the system board or in a connector.) INTA# of
192          * Device Number 1 is connected to IRQX on the system
193          * board. INTA# of Device Number 2 is connected to IRQY on the
194          * system board. INTA# of Device Number 3 is connected to IRQZ
195          * on the system board. The table below describes how each
196          * agent's INTx# lines are connected to the system board
197          * interrupt lines. The following equation can be used to
198          * determine to which INTx# signal on the system board a given
199          * device's INTx# line(s) is connected.
200          *
201          * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
202          * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
203          * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
204          * INTD# = 3)
205          */
206         if (of_machine_is_compatible("dlink,dsr-500n"))
207                 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
208         switch (octeon_bootinfo->board_type) {
209         case CVMX_BOARD_TYPE_NAO38:
210                 /* This is really the NAC38 */
211                 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
212         case CVMX_BOARD_TYPE_EBH3100:
213         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
214         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
215                 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
216         case CVMX_BOARD_TYPE_BBGW_REF:
217                 return "AABCD";
218         case CVMX_BOARD_TYPE_CUST_DSR1000N:
219                 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
220         case CVMX_BOARD_TYPE_THUNDER:
221         case CVMX_BOARD_TYPE_EBH3000:
222         default:
223                 return "";
224         }
225 }
226 
227 /**
228  * Map a PCI device to the appropriate interrupt line
229  *
230  * @dev:    The Linux PCI device structure for the device to map
231  * @slot:   The slot number for this device on __BUS 0__. Linux
232  *               enumerates through all the bridges and figures out the
233  *               slot on Bus 0 where this device eventually hooks to.
234  * @pin:    The PCI interrupt pin read from the device, then swizzled
235  *               as it goes through each bridge.
236  * Returns Interrupt number for the device
237  */
238 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
239                                       u8 slot, u8 pin)
240 {
241         int irq_num;
242         const char *interrupts;
243         int dev_num;
244 
245         /* Get the board specific interrupt mapping */
246         interrupts = octeon_get_pci_interrupts();
247 
248         dev_num = dev->devfn >> 3;
249         if (dev_num < strlen(interrupts))
250                 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
251                         OCTEON_IRQ_PCI_INT0;
252         else
253                 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
254         return irq_num;
255 }
256 
257 
258 /*
259  * Read a value from configuration space
260  */
261 static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
262                               int reg, int size, u32 *val)
263 {
264         union octeon_pci_address pci_addr;
265 
266         pci_addr.u64 = 0;
267         pci_addr.s.upper = 2;
268         pci_addr.s.io = 1;
269         pci_addr.s.did = 3;
270         pci_addr.s.subdid = 1;
271         pci_addr.s.endian_swap = 1;
272         pci_addr.s.bus = bus->number;
273         pci_addr.s.dev = devfn >> 3;
274         pci_addr.s.func = devfn & 0x7;
275         pci_addr.s.reg = reg;
276 
277         switch (size) {
278         case 4:
279                 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
280                 return PCIBIOS_SUCCESSFUL;
281         case 2:
282                 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
283                 return PCIBIOS_SUCCESSFUL;
284         case 1:
285                 *val = cvmx_read64_uint8(pci_addr.u64);
286                 return PCIBIOS_SUCCESSFUL;
287         }
288         return PCIBIOS_FUNC_NOT_SUPPORTED;
289 }
290 
291 
292 /*
293  * Write a value to PCI configuration space
294  */
295 static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
296                                int reg, int size, u32 val)
297 {
298         union octeon_pci_address pci_addr;
299 
300         pci_addr.u64 = 0;
301         pci_addr.s.upper = 2;
302         pci_addr.s.io = 1;
303         pci_addr.s.did = 3;
304         pci_addr.s.subdid = 1;
305         pci_addr.s.endian_swap = 1;
306         pci_addr.s.bus = bus->number;
307         pci_addr.s.dev = devfn >> 3;
308         pci_addr.s.func = devfn & 0x7;
309         pci_addr.s.reg = reg;
310 
311         switch (size) {
312         case 4:
313                 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
314                 return PCIBIOS_SUCCESSFUL;
315         case 2:
316                 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
317                 return PCIBIOS_SUCCESSFUL;
318         case 1:
319                 cvmx_write64_uint8(pci_addr.u64, val);
320                 return PCIBIOS_SUCCESSFUL;
321         }
322         return PCIBIOS_FUNC_NOT_SUPPORTED;
323 }
324 
325 
326 static struct pci_ops octeon_pci_ops = {
327         .read   = octeon_read_config,
328         .write  = octeon_write_config,
329 };
330 
331 static struct resource octeon_pci_mem_resource = {
332         .start = 0,
333         .end = 0,
334         .name = "Octeon PCI MEM",
335         .flags = IORESOURCE_MEM,
336 };
337 
338 /*
339  * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
340  * bridge
341  */
342 static struct resource octeon_pci_io_resource = {
343         .start = 0x4000,
344         .end = OCTEON_PCI_IOSPACE_SIZE - 1,
345         .name = "Octeon PCI IO",
346         .flags = IORESOURCE_IO,
347 };
348 
349 static struct pci_controller octeon_pci_controller = {
350         .pci_ops = &octeon_pci_ops,
351         .mem_resource = &octeon_pci_mem_resource,
352         .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
353         .io_resource = &octeon_pci_io_resource,
354         .io_offset = 0,
355         .io_map_base = OCTEON_PCI_IOSPACE_BASE,
356 };
357 
358 
359 /*
360  * Low level initialize the Octeon PCI controller
361  */
362 static void octeon_pci_initialize(void)
363 {
364         union cvmx_pci_cfg01 cfg01;
365         union cvmx_npi_ctl_status ctl_status;
366         union cvmx_pci_ctl_status_2 ctl_status_2;
367         union cvmx_pci_cfg19 cfg19;
368         union cvmx_pci_cfg16 cfg16;
369         union cvmx_pci_cfg22 cfg22;
370         union cvmx_pci_cfg56 cfg56;
371 
372         /* Reset the PCI Bus */
373         cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
374         cvmx_read_csr(CVMX_CIU_SOFT_PRST);
375 
376         udelay(2000);           /* Hold PCI reset for 2 ms */
377 
378         ctl_status.u64 = 0;     /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
379         ctl_status.s.max_word = 1;
380         ctl_status.s.timer = 1;
381         cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
382 
383         /* Deassert PCI reset and advertize PCX Host Mode Device Capability
384            (64b) */
385         cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
386         cvmx_read_csr(CVMX_CIU_SOFT_PRST);
387 
388         udelay(2000);           /* Wait 2 ms after deasserting PCI reset */
389 
390         ctl_status_2.u32 = 0;
391         ctl_status_2.s.tsr_hwm = 1;     /* Initializes to 0.  Must be set
392                                            before any PCI reads. */
393         ctl_status_2.s.bar2pres = 1;    /* Enable BAR2 */
394         ctl_status_2.s.bar2_enb = 1;
395         ctl_status_2.s.bar2_cax = 1;    /* Don't use L2 */
396         ctl_status_2.s.bar2_esx = 1;
397         ctl_status_2.s.pmo_amod = 1;    /* Round robin priority */
398         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
399                 /* BAR1 hole */
400                 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
401                 ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
402                 ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
403                 ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */
404                 ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
405                 ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
406         }
407 
408         octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
409         udelay(2000);           /* Wait 2 ms before doing PCI reads */
410 
411         ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
412         pr_notice("PCI Status: %s %s-bit\n",
413                   ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
414                   ctl_status_2.s.ap_64ad ? "64" : "32");
415 
416         if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
417                 union cvmx_pci_cnt_reg cnt_reg_start;
418                 union cvmx_pci_cnt_reg cnt_reg_end;
419                 unsigned long cycles, pci_clock;
420 
421                 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
422                 cycles = read_c0_cvmcount();
423                 udelay(1000);
424                 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
425                 cycles = read_c0_cvmcount() - cycles;
426                 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
427                             (cycles / (mips_hpt_frequency / 1000000));
428                 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
429         }
430 
431         /*
432          * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
433          * in PCI-X mode to allow four outstanding splits. Otherwise,
434          * should not change from its reset value. Don't write PCI_CFG19
435          * in PCI mode (0x82000001 reset value), write it to 0x82000004
436          * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
437          * MRBCM -> must be one.
438          */
439         if (ctl_status_2.s.ap_pcix) {
440                 cfg19.u32 = 0;
441                 /*
442                  * Target Delayed/Split request outstanding maximum
443                  * count. [1..31] and 0=32.  NOTE: If the user
444                  * programs these bits beyond the Designed Maximum
445                  * outstanding count, then the designed maximum table
446                  * depth will be used instead.  No additional
447                  * Deferred/Split transactions will be accepted if
448                  * this outstanding maximum count is
449                  * reached. Furthermore, no additional deferred/split
450                  * transactions will be accepted if the I/O delay/ I/O
451                  * Split Request outstanding maximum is reached.
452                  */
453                 cfg19.s.tdomc = 4;
454                 /*
455                  * Master Deferred Read Request Outstanding Max Count
456                  * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
457                  * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
458                  * 5 2 110 6 3 111 7 3 For example, if these bits are
459                  * programmed to 100, the core can support 2 DAC
460                  * cycles, 4 SAC cycles or a combination of 1 DAC and
461                  * 2 SAC cycles. NOTE: For the PCI-X maximum
462                  * outstanding split transactions, refer to
463                  * CRE0[22:20].
464                  */
465                 cfg19.s.mdrrmc = 2;
466                 /*
467                  * Master Request (Memory Read) Byte Count/Byte Enable
468                  * select. 0 = Byte Enables valid. In PCI mode, a
469                  * burst transaction cannot be performed using Memory
470                  * Read command=4?h6. 1 = DWORD Byte Count valid
471                  * (default). In PCI Mode, the memory read byte
472                  * enables are automatically generated by the
473                  * core. Note: N3 Master Request transaction sizes are
474                  * always determined through the
475                  * am_attr[<35:32>|<7:0>] field.
476                  */
477                 cfg19.s.mrbcm = 1;
478                 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
479         }
480 
481 
482         cfg01.u32 = 0;
483         cfg01.s.msae = 1;       /* Memory Space Access Enable */
484         cfg01.s.me = 1;         /* Master Enable */
485         cfg01.s.pee = 1;        /* PERR# Enable */
486         cfg01.s.see = 1;        /* System Error Enable */
487         cfg01.s.fbbe = 1;       /* Fast Back to Back Transaction Enable */
488 
489         octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
490 
491 #ifdef USE_OCTEON_INTERNAL_ARBITER
492         /*
493          * When OCTEON is a PCI host, most systems will use OCTEON's
494          * internal arbiter, so must enable it before any PCI/PCI-X
495          * traffic can occur.
496          */
497         {
498                 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
499 
500                 pci_int_arb_cfg.u64 = 0;
501                 pci_int_arb_cfg.s.en = 1;       /* Internal arbiter enable */
502                 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
503         }
504 #endif  /* USE_OCTEON_INTERNAL_ARBITER */
505 
506         /*
507          * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
508          * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
509          * 1..7.
510          */
511         cfg16.u32 = 0;
512         cfg16.s.mltd = 1;       /* Master Latency Timer Disable */
513         octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
514 
515         /*
516          * Should be written to 0x4ff00. MTTV -> must be zero.
517          * FLUSH -> must be 1. MRV -> should be 0xFF.
518          */
519         cfg22.u32 = 0;
520         /* Master Retry Value [1..255] and 0=infinite */
521         cfg22.s.mrv = 0xff;
522         /*
523          * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
524          * N3K operation.
525          */
526         cfg22.s.flush = 1;
527         octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
528 
529         /*
530          * MOST Indicates the maximum number of outstanding splits (in -1
531          * notation) when OCTEON is in PCI-X mode.  PCI-X performance is
532          * affected by the MOST selection.  Should generally be written
533          * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
534          * depending on the desired MOST of 3, 2, 1, or 0, respectively.
535          */
536         cfg56.u32 = 0;
537         cfg56.s.pxcid = 7;      /* RO - PCI-X Capability ID */
538         cfg56.s.ncp = 0xe8;     /* RO - Next Capability Pointer */
539         cfg56.s.dpere = 1;      /* Data Parity Error Recovery Enable */
540         cfg56.s.roe = 1;        /* Relaxed Ordering Enable */
541         cfg56.s.mmbc = 1;       /* Maximum Memory Byte Count
542                                    [0=512B,1=1024B,2=2048B,3=4096B] */
543         cfg56.s.most = 3;       /* Maximum outstanding Split transactions [0=1
544                                    .. 7=32] */
545 
546         octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
547 
548         /*
549          * Affects PCI performance when OCTEON services reads to its
550          * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
551          * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
552          * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
553          * these values need to be changed so they won't possibly prefetch off
554          * of the end of memory if PCI is DMAing a buffer at the end of
555          * memory. Note that these values differ from their reset values.
556          */
557         octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
558         octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
559         octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
560 }
561 
562 
563 /*
564  * Initialize the Octeon PCI controller
565  */
566 static int __init octeon_pci_setup(void)
567 {
568         union cvmx_npi_mem_access_subidx mem_access;
569         int index;
570 
571         /* Only these chips have PCI */
572         if (octeon_has_feature(OCTEON_FEATURE_PCIE))
573                 return 0;
574 
575         /* Point pcibios_map_irq() to the PCI version of it */
576         octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
577 
578         /* Only use the big bars on chips that support it */
579         if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
580             OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
581             OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
582                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
583         else
584                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
585 
586         if (!octeon_is_pci_host()) {
587                 pr_notice("Not in host mode, PCI Controller not initialized\n");
588                 return 0;
589         }
590 
591         /* PCI I/O and PCI MEM values */
592         set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
593         ioport_resource.start = 0;
594         ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
595 
596         pr_notice("%s Octeon big bar support\n",
597                   (octeon_dma_bar_type ==
598                   OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
599 
600         octeon_pci_initialize();
601 
602         mem_access.u64 = 0;
603         mem_access.s.esr = 1;   /* Endian-Swap on read. */
604         mem_access.s.esw = 1;   /* Endian-Swap on write. */
605         mem_access.s.nsr = 0;   /* No-Snoop on read. */
606         mem_access.s.nsw = 0;   /* No-Snoop on write. */
607         mem_access.s.ror = 0;   /* Relax Read on read. */
608         mem_access.s.row = 0;   /* Relax Order on write. */
609         mem_access.s.ba = 0;    /* PCI Address bits [63:36]. */
610         cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
611 
612         /*
613          * Remap the Octeon BAR 2 above all 32 bit devices
614          * (0x8000000000ul).  This is done here so it is remapped
615          * before the readl()'s below. We don't want BAR2 overlapping
616          * with BAR0/BAR1 during these reads.
617          */
618         octeon_npi_write32(CVMX_NPI_PCI_CFG08,
619                            (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
620         octeon_npi_write32(CVMX_NPI_PCI_CFG09,
621                            (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
622 
623         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
624                 /* Remap the Octeon BAR 0 to 0-2GB */
625                 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
626                 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
627 
628                 /*
629                  * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
630                  * BAR 1 hole).
631                  */
632                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
633                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
634 
635                 /* BAR1 movable mappings set for identity mapping */
636                 octeon_bar1_pci_phys = 0x80000000ull;
637                 for (index = 0; index < 32; index++) {
638                         union cvmx_pci_bar1_indexx bar1_index;
639 
640                         bar1_index.u32 = 0;
641                         /* Address bits[35:22] sent to L2C */
642                         bar1_index.s.addr_idx =
643                                 (octeon_bar1_pci_phys >> 22) + index;
644                         /* Don't put PCI accesses in L2. */
645                         bar1_index.s.ca = 1;
646                         /* Endian Swap Mode */
647                         bar1_index.s.end_swp = 1;
648                         /* Set '1' when the selected address range is valid. */
649                         bar1_index.s.addr_v = 1;
650                         octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
651                                            bar1_index.u32);
652                 }
653 
654                 /* Devices go after BAR1 */
655                 octeon_pci_mem_resource.start =
656                         OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
657                         (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
658                 octeon_pci_mem_resource.end =
659                         octeon_pci_mem_resource.start + (1ul << 30);
660         } else {
661                 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
662                 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
663                 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
664 
665                 /* Remap the Octeon BAR 1 to map 0-128MB */
666                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
667                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
668 
669                 /* BAR1 movable regions contiguous to cover the swiotlb */
670                 octeon_bar1_pci_phys =
671                         virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
672 
673                 for (index = 0; index < 32; index++) {
674                         union cvmx_pci_bar1_indexx bar1_index;
675 
676                         bar1_index.u32 = 0;
677                         /* Address bits[35:22] sent to L2C */
678                         bar1_index.s.addr_idx =
679                                 (octeon_bar1_pci_phys >> 22) + index;
680                         /* Don't put PCI accesses in L2. */
681                         bar1_index.s.ca = 1;
682                         /* Endian Swap Mode */
683                         bar1_index.s.end_swp = 1;
684                         /* Set '1' when the selected address range is valid. */
685                         bar1_index.s.addr_v = 1;
686                         octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
687                                            bar1_index.u32);
688                 }
689 
690                 /* Devices go after BAR0 */
691                 octeon_pci_mem_resource.start =
692                         OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
693                         (4ul << 10);
694                 octeon_pci_mem_resource.end =
695                         octeon_pci_mem_resource.start + (1ul << 30);
696         }
697 
698         register_pci_controller(&octeon_pci_controller);
699 
700         /*
701          * Clear any errors that might be pending from before the bus
702          * was setup properly.
703          */
704         cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
705 
706         if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
707                                                    -1, NULL, 0)))
708                 pr_err("Registration of co_pci_edac failed!\n");
709 
710         octeon_pci_dma_init();
711 
712         return 0;
713 }
714 
715 arch_initcall(octeon_pci_setup);
716 

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