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TOMOYO Linux Cross Reference
Linux/arch/mips/pci/pcie-octeon.c

Version: ~ [ linux-4.18-rc5 ] ~ [ linux-4.17.6 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.55 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.112 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.140 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.115 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.57 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.27.62 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
  7  */
  8 #include <linux/kernel.h>
  9 #include <linux/init.h>
 10 #include <linux/pci.h>
 11 #include <linux/interrupt.h>
 12 #include <linux/time.h>
 13 #include <linux/delay.h>
 14 #include <linux/moduleparam.h>
 15 
 16 #include <asm/octeon/octeon.h>
 17 #include <asm/octeon/cvmx-npei-defs.h>
 18 #include <asm/octeon/cvmx-pciercx-defs.h>
 19 #include <asm/octeon/cvmx-pescx-defs.h>
 20 #include <asm/octeon/cvmx-pexp-defs.h>
 21 #include <asm/octeon/cvmx-pemx-defs.h>
 22 #include <asm/octeon/cvmx-dpi-defs.h>
 23 #include <asm/octeon/cvmx-sli-defs.h>
 24 #include <asm/octeon/cvmx-sriox-defs.h>
 25 #include <asm/octeon/cvmx-helper-errata.h>
 26 #include <asm/octeon/pci-octeon.h>
 27 
 28 #define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
 29 #define MPS_CN5XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
 30 #define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
 31 #define MPS_CN6XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
 32 
 33 /* Module parameter to disable PCI probing */
 34 static int pcie_disable;
 35 module_param(pcie_disable, int, S_IRUGO);
 36 
 37 static int enable_pcie_14459_war;
 38 static int enable_pcie_bus_num_war[2];
 39 
 40 union cvmx_pcie_address {
 41         uint64_t u64;
 42         struct {
 43                 uint64_t upper:2;       /* Normally 2 for XKPHYS */
 44                 uint64_t reserved_49_61:13;     /* Must be zero */
 45                 uint64_t io:1;  /* 1 for IO space access */
 46                 uint64_t did:5; /* PCIe DID = 3 */
 47                 uint64_t subdid:3;      /* PCIe SubDID = 1 */
 48                 uint64_t reserved_36_39:4;      /* Must be zero */
 49                 uint64_t es:2;  /* Endian swap = 1 */
 50                 uint64_t port:2;        /* PCIe port 0,1 */
 51                 uint64_t reserved_29_31:3;      /* Must be zero */
 52                 /*
 53                  * Selects the type of the configuration request (0 = type 0,
 54                  * 1 = type 1).
 55                  */
 56                 uint64_t ty:1;
 57                 /* Target bus number sent in the ID in the request. */
 58                 uint64_t bus:8;
 59                 /*
 60                  * Target device number sent in the ID in the
 61                  * request. Note that Dev must be zero for type 0
 62                  * configuration requests.
 63                  */
 64                 uint64_t dev:5;
 65                 /* Target function number sent in the ID in the request. */
 66                 uint64_t func:3;
 67                 /*
 68                  * Selects a register in the configuration space of
 69                  * the target.
 70                  */
 71                 uint64_t reg:12;
 72         } config;
 73         struct {
 74                 uint64_t upper:2;       /* Normally 2 for XKPHYS */
 75                 uint64_t reserved_49_61:13;     /* Must be zero */
 76                 uint64_t io:1;  /* 1 for IO space access */
 77                 uint64_t did:5; /* PCIe DID = 3 */
 78                 uint64_t subdid:3;      /* PCIe SubDID = 2 */
 79                 uint64_t reserved_36_39:4;      /* Must be zero */
 80                 uint64_t es:2;  /* Endian swap = 1 */
 81                 uint64_t port:2;        /* PCIe port 0,1 */
 82                 uint64_t address:32;    /* PCIe IO address */
 83         } io;
 84         struct {
 85                 uint64_t upper:2;       /* Normally 2 for XKPHYS */
 86                 uint64_t reserved_49_61:13;     /* Must be zero */
 87                 uint64_t io:1;  /* 1 for IO space access */
 88                 uint64_t did:5; /* PCIe DID = 3 */
 89                 uint64_t subdid:3;      /* PCIe SubDID = 3-6 */
 90                 uint64_t reserved_36_39:4;      /* Must be zero */
 91                 uint64_t address:36;    /* PCIe Mem address */
 92         } mem;
 93 };
 94 
 95 static int cvmx_pcie_rc_initialize(int pcie_port);
 96 
 97 #include <dma-coherence.h>
 98 
 99 /**
100  * Return the Core virtual base address for PCIe IO access. IOs are
101  * read/written as an offset from this address.
102  *
103  * @pcie_port: PCIe port the IO is for
104  *
105  * Returns 64bit Octeon IO base address for read/write
106  */
107 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
108 {
109         union cvmx_pcie_address pcie_addr;
110         pcie_addr.u64 = 0;
111         pcie_addr.io.upper = 0;
112         pcie_addr.io.io = 1;
113         pcie_addr.io.did = 3;
114         pcie_addr.io.subdid = 2;
115         pcie_addr.io.es = 1;
116         pcie_addr.io.port = pcie_port;
117         return pcie_addr.u64;
118 }
119 
120 /**
121  * Size of the IO address region returned at address
122  * cvmx_pcie_get_io_base_address()
123  *
124  * @pcie_port: PCIe port the IO is for
125  *
126  * Returns Size of the IO window
127  */
128 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
129 {
130         return 1ull << 32;
131 }
132 
133 /**
134  * Return the Core virtual base address for PCIe MEM access. Memory is
135  * read/written as an offset from this address.
136  *
137  * @pcie_port: PCIe port the IO is for
138  *
139  * Returns 64bit Octeon IO base address for read/write
140  */
141 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
142 {
143         union cvmx_pcie_address pcie_addr;
144         pcie_addr.u64 = 0;
145         pcie_addr.mem.upper = 0;
146         pcie_addr.mem.io = 1;
147         pcie_addr.mem.did = 3;
148         pcie_addr.mem.subdid = 3 + pcie_port;
149         return pcie_addr.u64;
150 }
151 
152 /**
153  * Size of the Mem address region returned at address
154  * cvmx_pcie_get_mem_base_address()
155  *
156  * @pcie_port: PCIe port the IO is for
157  *
158  * Returns Size of the Mem window
159  */
160 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
161 {
162         return 1ull << 36;
163 }
164 
165 /**
166  * Read a PCIe config space register indirectly. This is used for
167  * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
168  *
169  * @pcie_port:  PCIe port to read from
170  * @cfg_offset: Address to read
171  *
172  * Returns Value read
173  */
174 static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
175 {
176         if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
177                 union cvmx_pescx_cfg_rd pescx_cfg_rd;
178                 pescx_cfg_rd.u64 = 0;
179                 pescx_cfg_rd.s.addr = cfg_offset;
180                 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
181                 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
182                 return pescx_cfg_rd.s.data;
183         } else {
184                 union cvmx_pemx_cfg_rd pemx_cfg_rd;
185                 pemx_cfg_rd.u64 = 0;
186                 pemx_cfg_rd.s.addr = cfg_offset;
187                 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
188                 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
189                 return pemx_cfg_rd.s.data;
190         }
191 }
192 
193 /**
194  * Write a PCIe config space register indirectly. This is used for
195  * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
196  *
197  * @pcie_port:  PCIe port to write to
198  * @cfg_offset: Address to write
199  * @val:        Value to write
200  */
201 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
202                                  uint32_t val)
203 {
204         if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
205                 union cvmx_pescx_cfg_wr pescx_cfg_wr;
206                 pescx_cfg_wr.u64 = 0;
207                 pescx_cfg_wr.s.addr = cfg_offset;
208                 pescx_cfg_wr.s.data = val;
209                 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
210         } else {
211                 union cvmx_pemx_cfg_wr pemx_cfg_wr;
212                 pemx_cfg_wr.u64 = 0;
213                 pemx_cfg_wr.s.addr = cfg_offset;
214                 pemx_cfg_wr.s.data = val;
215                 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
216         }
217 }
218 
219 /**
220  * Build a PCIe config space request address for a device
221  *
222  * @pcie_port: PCIe port to access
223  * @bus:       Sub bus
224  * @dev:       Device ID
225  * @fn:        Device sub function
226  * @reg:       Register to access
227  *
228  * Returns 64bit Octeon IO address
229  */
230 static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
231                                                      int dev, int fn, int reg)
232 {
233         union cvmx_pcie_address pcie_addr;
234         union cvmx_pciercx_cfg006 pciercx_cfg006;
235 
236         pciercx_cfg006.u32 =
237             cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
238         if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
239                 return 0;
240 
241         pcie_addr.u64 = 0;
242         pcie_addr.config.upper = 2;
243         pcie_addr.config.io = 1;
244         pcie_addr.config.did = 3;
245         pcie_addr.config.subdid = 1;
246         pcie_addr.config.es = 1;
247         pcie_addr.config.port = pcie_port;
248         pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
249         pcie_addr.config.bus = bus;
250         pcie_addr.config.dev = dev;
251         pcie_addr.config.func = fn;
252         pcie_addr.config.reg = reg;
253         return pcie_addr.u64;
254 }
255 
256 /**
257  * Read 8bits from a Device's config space
258  *
259  * @pcie_port: PCIe port the device is on
260  * @bus:       Sub bus
261  * @dev:       Device ID
262  * @fn:        Device sub function
263  * @reg:       Register to access
264  *
265  * Returns Result of the read
266  */
267 static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
268                                       int fn, int reg)
269 {
270         uint64_t address =
271             __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
272         if (address)
273                 return cvmx_read64_uint8(address);
274         else
275                 return 0xff;
276 }
277 
278 /**
279  * Read 16bits from a Device's config space
280  *
281  * @pcie_port: PCIe port the device is on
282  * @bus:       Sub bus
283  * @dev:       Device ID
284  * @fn:        Device sub function
285  * @reg:       Register to access
286  *
287  * Returns Result of the read
288  */
289 static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
290                                         int fn, int reg)
291 {
292         uint64_t address =
293             __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
294         if (address)
295                 return le16_to_cpu(cvmx_read64_uint16(address));
296         else
297                 return 0xffff;
298 }
299 
300 /**
301  * Read 32bits from a Device's config space
302  *
303  * @pcie_port: PCIe port the device is on
304  * @bus:       Sub bus
305  * @dev:       Device ID
306  * @fn:        Device sub function
307  * @reg:       Register to access
308  *
309  * Returns Result of the read
310  */
311 static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
312                                         int fn, int reg)
313 {
314         uint64_t address =
315             __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
316         if (address)
317                 return le32_to_cpu(cvmx_read64_uint32(address));
318         else
319                 return 0xffffffff;
320 }
321 
322 /**
323  * Write 8bits to a Device's config space
324  *
325  * @pcie_port: PCIe port the device is on
326  * @bus:       Sub bus
327  * @dev:       Device ID
328  * @fn:        Device sub function
329  * @reg:       Register to access
330  * @val:       Value to write
331  */
332 static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
333                                     int reg, uint8_t val)
334 {
335         uint64_t address =
336             __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
337         if (address)
338                 cvmx_write64_uint8(address, val);
339 }
340 
341 /**
342  * Write 16bits to a Device's config space
343  *
344  * @pcie_port: PCIe port the device is on
345  * @bus:       Sub bus
346  * @dev:       Device ID
347  * @fn:        Device sub function
348  * @reg:       Register to access
349  * @val:       Value to write
350  */
351 static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
352                                      int reg, uint16_t val)
353 {
354         uint64_t address =
355             __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
356         if (address)
357                 cvmx_write64_uint16(address, cpu_to_le16(val));
358 }
359 
360 /**
361  * Write 32bits to a Device's config space
362  *
363  * @pcie_port: PCIe port the device is on
364  * @bus:       Sub bus
365  * @dev:       Device ID
366  * @fn:        Device sub function
367  * @reg:       Register to access
368  * @val:       Value to write
369  */
370 static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
371                                      int reg, uint32_t val)
372 {
373         uint64_t address =
374             __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
375         if (address)
376                 cvmx_write64_uint32(address, cpu_to_le32(val));
377 }
378 
379 /**
380  * Initialize the RC config space CSRs
381  *
382  * @pcie_port: PCIe port to initialize
383  */
384 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
385 {
386         union cvmx_pciercx_cfg030 pciercx_cfg030;
387         union cvmx_pciercx_cfg070 pciercx_cfg070;
388         union cvmx_pciercx_cfg001 pciercx_cfg001;
389         union cvmx_pciercx_cfg032 pciercx_cfg032;
390         union cvmx_pciercx_cfg006 pciercx_cfg006;
391         union cvmx_pciercx_cfg008 pciercx_cfg008;
392         union cvmx_pciercx_cfg009 pciercx_cfg009;
393         union cvmx_pciercx_cfg010 pciercx_cfg010;
394         union cvmx_pciercx_cfg011 pciercx_cfg011;
395         union cvmx_pciercx_cfg035 pciercx_cfg035;
396         union cvmx_pciercx_cfg075 pciercx_cfg075;
397         union cvmx_pciercx_cfg034 pciercx_cfg034;
398 
399         /* Max Payload Size (PCIE*_CFG030[MPS]) */
400         /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
401         /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
402         /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
403 
404         pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
405         if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
406                 pciercx_cfg030.s.mps = MPS_CN5XXX;
407                 pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
408         } else {
409                 pciercx_cfg030.s.mps = MPS_CN6XXX;
410                 pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
411         }
412         /*
413          * Enable relaxed order processing. This will allow devices to
414          * affect read response ordering.
415          */
416         pciercx_cfg030.s.ro_en = 1;
417         /* Enable no snoop processing. Not used by Octeon */
418         pciercx_cfg030.s.ns_en = 1;
419         /* Correctable error reporting enable. */
420         pciercx_cfg030.s.ce_en = 1;
421         /* Non-fatal error reporting enable. */
422         pciercx_cfg030.s.nfe_en = 1;
423         /* Fatal error reporting enable. */
424         pciercx_cfg030.s.fe_en = 1;
425         /* Unsupported request reporting enable. */
426         pciercx_cfg030.s.ur_en = 1;
427         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
428 
429 
430         if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
431                 union cvmx_npei_ctl_status2 npei_ctl_status2;
432                 /*
433                  * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
434                  * PCIE*_CFG030[MPS].  Max Read Request Size
435                  * (NPEI_CTL_STATUS2[MRRS]) must not exceed
436                  * PCIE*_CFG030[MRRS]
437                  */
438                 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
439                 /* Max payload size = 128 bytes for best Octeon DMA performance */
440                 npei_ctl_status2.s.mps = MPS_CN5XXX;
441                 /* Max read request size = 128 bytes for best Octeon DMA performance */
442                 npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
443                 if (pcie_port)
444                         npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
445                 else
446                         npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
447 
448                 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
449         } else {
450                 /*
451                  * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
452                  * PCIE*_CFG030[MPS].  Max Read Request Size
453                  * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
454                  * PCIE*_CFG030[MRRS].
455                  */
456                 union cvmx_dpi_sli_prtx_cfg prt_cfg;
457                 union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
458                 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
459                 prt_cfg.s.mps = MPS_CN6XXX;
460                 prt_cfg.s.mrrs = MRRS_CN6XXX;
461                 /* Max outstanding load request. */
462                 prt_cfg.s.molr = 32;
463                 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
464 
465                 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
466                 sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
467                 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
468         }
469 
470         /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
471         pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
472         pciercx_cfg070.s.ge = 1;        /* ECRC generation enable. */
473         pciercx_cfg070.s.ce = 1;        /* ECRC check enable. */
474         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
475 
476         /*
477          * Access Enables (PCIE*_CFG001[MSAE,ME])
478          * ME and MSAE should always be set.
479          * Interrupt Disable (PCIE*_CFG001[I_DIS])
480          * System Error Message Enable (PCIE*_CFG001[SEE])
481          */
482         pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
483         pciercx_cfg001.s.msae = 1;      /* Memory space enable. */
484         pciercx_cfg001.s.me = 1;        /* Bus master enable. */
485         pciercx_cfg001.s.i_dis = 1;     /* INTx assertion disable. */
486         pciercx_cfg001.s.see = 1;       /* SERR# enable */
487         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
488 
489         /* Advanced Error Recovery Message Enables */
490         /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
491         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
492         /* Use CVMX_PCIERCX_CFG067 hardware default */
493         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
494 
495 
496         /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
497         pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
498         pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
499         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
500 
501         /*
502          * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
503          * cvmx_pcie_rc_initialize_link()
504          *
505          * Primary Bus Number (PCIERCn_CFG006[PBNUM])
506          *
507          * We set the primary bus number to 1 so IDT bridges are
508          * happy. They don't like zero.
509          */
510         pciercx_cfg006.u32 = 0;
511         pciercx_cfg006.s.pbnum = 1;
512         pciercx_cfg006.s.sbnum = 1;
513         pciercx_cfg006.s.subbnum = 1;
514         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
515 
516 
517         /*
518          * Memory-mapped I/O BAR (PCIERCn_CFG008)
519          * Most applications should disable the memory-mapped I/O BAR by
520          * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
521          */
522         pciercx_cfg008.u32 = 0;
523         pciercx_cfg008.s.mb_addr = 0x100;
524         pciercx_cfg008.s.ml_addr = 0;
525         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
526 
527 
528         /*
529          * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
530          * Most applications should disable the prefetchable BAR by setting
531          * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
532          * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
533          */
534         pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
535         pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
536         pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
537         pciercx_cfg009.s.lmem_base = 0x100;
538         pciercx_cfg009.s.lmem_limit = 0;
539         pciercx_cfg010.s.umem_base = 0x100;
540         pciercx_cfg011.s.umem_limit = 0;
541         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
542         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
543         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
544 
545         /*
546          * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
547          * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
548         */
549         pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
550         pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
551         pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
552         pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
553         pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
554         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
555 
556         /*
557          * Advanced Error Recovery Interrupt Enables
558          * (PCIERCn_CFG075[CERE,NFERE,FERE])
559          */
560         pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
561         pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
562         pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
563         pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
564         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
565 
566         /*
567          * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
568          * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
569          */
570         pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
571         pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
572         pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
573         pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
574         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
575 }
576 
577 /**
578  * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
579  * port from reset to a link up state. Software can then begin
580  * configuring the rest of the link.
581  *
582  * @pcie_port: PCIe port to initialize
583  *
584  * Returns Zero on success
585  */
586 static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
587 {
588         uint64_t start_cycle;
589         union cvmx_pescx_ctl_status pescx_ctl_status;
590         union cvmx_pciercx_cfg452 pciercx_cfg452;
591         union cvmx_pciercx_cfg032 pciercx_cfg032;
592         union cvmx_pciercx_cfg448 pciercx_cfg448;
593 
594         /* Set the lane width */
595         pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
596         pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
597         if (pescx_ctl_status.s.qlm_cfg == 0)
598                 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
599                 pciercx_cfg452.s.lme = 0xf;
600         else
601                 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
602                 pciercx_cfg452.s.lme = 0x7;
603         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
604 
605         /*
606          * CN52XX pass 1.x has an errata where length mismatches on UR
607          * responses can cause bus errors on 64bit memory
608          * reads. Turning off length error checking fixes this.
609          */
610         if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
611                 union cvmx_pciercx_cfg455 pciercx_cfg455;
612                 pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
613                 pciercx_cfg455.s.m_cpl_len_err = 1;
614                 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
615         }
616 
617         /* Lane swap needs to be manually enabled for CN52XX */
618         if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
619                 pescx_ctl_status.s.lane_swp = 1;
620                 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
621         }
622 
623         /* Bring up the link */
624         pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
625         pescx_ctl_status.s.lnk_enb = 1;
626         cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
627 
628         /*
629          * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
630          * be disabled.
631          */
632         if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
633                 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
634 
635         /* Wait for the link to come up */
636         start_cycle = cvmx_get_cycle();
637         do {
638                 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
639                         cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
640                         return -1;
641                 }
642                 __delay(10000);
643                 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
644         } while (pciercx_cfg032.s.dlla == 0);
645 
646         /* Clear all pending errors */
647         cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
648 
649         /*
650          * Update the Replay Time Limit. Empirically, some PCIe
651          * devices take a little longer to respond than expected under
652          * load. As a workaround for this we configure the Replay Time
653          * Limit to the value expected for a 512 byte MPS instead of
654          * our actual 256 byte MPS. The numbers below are directly
655          * from the PCIe spec table 3-4.
656          */
657         pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
658         switch (pciercx_cfg032.s.nlw) {
659         case 1:         /* 1 lane */
660                 pciercx_cfg448.s.rtl = 1677;
661                 break;
662         case 2:         /* 2 lanes */
663                 pciercx_cfg448.s.rtl = 867;
664                 break;
665         case 4:         /* 4 lanes */
666                 pciercx_cfg448.s.rtl = 462;
667                 break;
668         case 8:         /* 8 lanes */
669                 pciercx_cfg448.s.rtl = 258;
670                 break;
671         }
672         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
673 
674         return 0;
675 }
676 
677 static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
678 {
679         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
680                 pmas->cn68xx.ba++;
681         else
682                 pmas->s.ba++;
683 }
684 
685 /**
686  * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
687  * enumerate the bus.
688  *
689  * @pcie_port: PCIe port to initialize
690  *
691  * Returns Zero on success
692  */
693 static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
694 {
695         int i;
696         int base;
697         u64 addr_swizzle;
698         union cvmx_ciu_soft_prst ciu_soft_prst;
699         union cvmx_pescx_bist_status pescx_bist_status;
700         union cvmx_pescx_bist_status2 pescx_bist_status2;
701         union cvmx_npei_ctl_status npei_ctl_status;
702         union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
703         union cvmx_npei_mem_access_subidx mem_access_subid;
704         union cvmx_npei_dbg_data npei_dbg_data;
705         union cvmx_pescx_ctl_status2 pescx_ctl_status2;
706         union cvmx_pciercx_cfg032 pciercx_cfg032;
707         union cvmx_npei_bar1_indexx bar1_index;
708 
709 retry:
710         /*
711          * Make sure we aren't trying to setup a target mode interface
712          * in host mode.
713          */
714         npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
715         if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
716                 cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
717                 return -1;
718         }
719 
720         /*
721          * Make sure a CN52XX isn't trying to bring up port 1 when it
722          * is disabled.
723          */
724         if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
725                 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
726                 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
727                         cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
728                         return -1;
729                 }
730         }
731 
732         /*
733          * PCIe switch arbitration mode. '' == fixed priority NPEI,
734          * PCIe0, then PCIe1. '1' == round robin.
735          */
736         npei_ctl_status.s.arb = 1;
737         /* Allow up to 0x20 config retries */
738         npei_ctl_status.s.cfg_rtry = 0x20;
739         /*
740          * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
741          * don't reset.
742          */
743         if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
744                 npei_ctl_status.s.p0_ntags = 0x20;
745                 npei_ctl_status.s.p1_ntags = 0x20;
746         }
747         cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
748 
749         /* Bring the PCIe out of reset */
750         if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
751                 /*
752                  * The EBH5200 board swapped the PCIe reset lines on
753                  * the board. As a workaround for this bug, we bring
754                  * both PCIe ports out of reset at the same time
755                  * instead of on separate calls. So for port 0, we
756                  * bring both out of reset and do nothing on port 1
757                  */
758                 if (pcie_port == 0) {
759                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
760                         /*
761                          * After a chip reset the PCIe will also be in
762                          * reset. If it isn't, most likely someone is
763                          * trying to init it again without a proper
764                          * PCIe reset.
765                          */
766                         if (ciu_soft_prst.s.soft_prst == 0) {
767                                 /* Reset the ports */
768                                 ciu_soft_prst.s.soft_prst = 1;
769                                 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
770                                 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
771                                 ciu_soft_prst.s.soft_prst = 1;
772                                 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
773                                 /* Wait until pcie resets the ports. */
774                                 udelay(2000);
775                         }
776                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
777                         ciu_soft_prst.s.soft_prst = 0;
778                         cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
779                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
780                         ciu_soft_prst.s.soft_prst = 0;
781                         cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
782                 }
783         } else {
784                 /*
785                  * The normal case: The PCIe ports are completely
786                  * separate and can be brought out of reset
787                  * independently.
788                  */
789                 if (pcie_port)
790                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
791                 else
792                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
793                 /*
794                  * After a chip reset the PCIe will also be in
795                  * reset. If it isn't, most likely someone is trying
796                  * to init it again without a proper PCIe reset.
797                  */
798                 if (ciu_soft_prst.s.soft_prst == 0) {
799                         /* Reset the port */
800                         ciu_soft_prst.s.soft_prst = 1;
801                         if (pcie_port)
802                                 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
803                         else
804                                 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
805                         /* Wait until pcie resets the ports. */
806                         udelay(2000);
807                 }
808                 if (pcie_port) {
809                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
810                         ciu_soft_prst.s.soft_prst = 0;
811                         cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
812                 } else {
813                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
814                         ciu_soft_prst.s.soft_prst = 0;
815                         cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
816                 }
817         }
818 
819         /*
820          * Wait for PCIe reset to complete. Due to errata PCIE-700, we
821          * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
822          * fixed number of cycles.
823          */
824         __delay(400000);
825 
826         /*
827          * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
828          * CN56XX and CN52XX, so we only probe it on newer chips
829          */
830         if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
831                 /* Clear PCLK_RUN so we can check if the clock is running */
832                 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
833                 pescx_ctl_status2.s.pclk_run = 1;
834                 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
835                 /* Now that we cleared PCLK_RUN, wait for it to be set
836                  * again telling us the clock is running
837                  */
838                 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
839                                           union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
840                         cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
841                         return -1;
842                 }
843         }
844 
845         /*
846          * Check and make sure PCIe came out of reset. If it doesn't
847          * the board probably hasn't wired the clocks up and the
848          * interface should be skipped.
849          */
850         pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
851         if (pescx_ctl_status2.s.pcierst) {
852                 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
853                 return -1;
854         }
855 
856         /*
857          * Check BIST2 status. If any bits are set skip this
858          * interface. This is an attempt to catch PCIE-813 on pass 1
859          * parts.
860          */
861         pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
862         if (pescx_bist_status2.u64) {
863                 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
864                              pcie_port);
865                 return -1;
866         }
867 
868         /* Check BIST status */
869         pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
870         if (pescx_bist_status.u64)
871                 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
872                              pcie_port, CAST64(pescx_bist_status.u64));
873 
874         /* Initialize the config space CSRs */
875         __cvmx_pcie_rc_initialize_config_space(pcie_port);
876 
877         /* Bring the link up */
878         if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
879                 cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
880                              pcie_port);
881                 return -1;
882         }
883 
884         /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
885         npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
886         npei_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
887         npei_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
888         cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
889 
890         /* Setup Mem access SubDIDs */
891         mem_access_subid.u64 = 0;
892         mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
893         mem_access_subid.s.nmerge = 1;  /* Due to an errata on pass 1 chips, no merging is allowed. */
894         mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
895         mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
896         mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
897         mem_access_subid.s.nsw = 0;     /* Enable Snoop for Writes. */
898         mem_access_subid.s.ror = 0;     /* Disable Relaxed Ordering for Reads. */
899         mem_access_subid.s.row = 0;     /* Disable Relaxed Ordering for Writes. */
900         mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
901 
902         /*
903          * Setup mem access 12-15 for port 0, 16-19 for port 1,
904          * supplying 36 bits of address space.
905          */
906         for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
907                 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
908                 mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
909         }
910 
911         /*
912          * Disable the peer to peer forwarding register. This must be
913          * setup by the OS after it enumerates the bus and assigns
914          * addresses to the PCIe busses.
915          */
916         for (i = 0; i < 4; i++) {
917                 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
918                 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
919         }
920 
921         /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
922         cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
923 
924         /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
925         cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
926 
927         bar1_index.u32 = 0;
928         bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
929         bar1_index.s.ca = 1;       /* Not Cached */
930         bar1_index.s.end_swp = 1;  /* Endian Swap mode */
931         bar1_index.s.addr_v = 1;   /* Valid entry */
932 
933         base = pcie_port ? 16 : 0;
934 
935         /* Big endian swizzle for 32-bit PEXP_NCB register. */
936 #ifdef __MIPSEB__
937         addr_swizzle = 4;
938 #else
939         addr_swizzle = 0;
940 #endif
941         for (i = 0; i < 16; i++) {
942                 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
943                                     bar1_index.u32);
944                 base++;
945                 /* 256MB / 16 >> 22 == 4 */
946                 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
947         }
948 
949         /*
950          * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
951          * precedence where they overlap. It also overlaps with the
952          * device addresses, so make sure the peer to peer forwarding
953          * is set right.
954          */
955         cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
956 
957         /*
958          * Setup BAR2 attributes
959          *
960          * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
961          * - PTLP_RO,CTLP_RO should normally be set (except for debug).
962          * - WAIT_COM=0 will likely work for all applications.
963          *
964          * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
965          */
966         if (pcie_port) {
967                 union cvmx_npei_ctl_port1 npei_ctl_port;
968                 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
969                 npei_ctl_port.s.bar2_enb = 1;
970                 npei_ctl_port.s.bar2_esx = 1;
971                 npei_ctl_port.s.bar2_cax = 0;
972                 npei_ctl_port.s.ptlp_ro = 1;
973                 npei_ctl_port.s.ctlp_ro = 1;
974                 npei_ctl_port.s.wait_com = 0;
975                 npei_ctl_port.s.waitl_com = 0;
976                 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
977         } else {
978                 union cvmx_npei_ctl_port0 npei_ctl_port;
979                 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
980                 npei_ctl_port.s.bar2_enb = 1;
981                 npei_ctl_port.s.bar2_esx = 1;
982                 npei_ctl_port.s.bar2_cax = 0;
983                 npei_ctl_port.s.ptlp_ro = 1;
984                 npei_ctl_port.s.ctlp_ro = 1;
985                 npei_ctl_port.s.wait_com = 0;
986                 npei_ctl_port.s.waitl_com = 0;
987                 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
988         }
989 
990         /*
991          * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
992          * that causes TLP ordering to not be preserved after multiple
993          * PCIe port resets. This code detects this fault and corrects
994          * it by aligning the TLP counters properly. Another link
995          * reset is then performed. See PCIE-13340
996          */
997         if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
998             OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
999             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
1000             OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1001                 union cvmx_npei_dbg_data dbg_data;
1002                 int old_in_fif_p_count;
1003                 int in_fif_p_count;
1004                 int out_p_count;
1005                 int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
1006                 int i;
1007 
1008                 /*
1009                  * Choose a write address of 1MB. It should be
1010                  * harmless as all bars haven't been setup.
1011                  */
1012                 uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
1013 
1014                 /*
1015                  * Make sure at least in_p_offset have been executed before we try and
1016                  * read in_fif_p_count
1017                  */
1018                 i = in_p_offset;
1019                 while (i--) {
1020                         cvmx_write64_uint32(write_address, 0);
1021                         __delay(10000);
1022                 }
1023 
1024                 /*
1025                  * Read the IN_FIF_P_COUNT from the debug
1026                  * select. IN_FIF_P_COUNT can be unstable sometimes so
1027                  * read it twice with a write between the reads.  This
1028                  * way we can tell the value is good as it will
1029                  * increment by one due to the write
1030                  */
1031                 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
1032                 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1033                 do {
1034                         dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1035                         old_in_fif_p_count = dbg_data.s.data & 0xff;
1036                         cvmx_write64_uint32(write_address, 0);
1037                         __delay(10000);
1038                         dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1039                         in_fif_p_count = dbg_data.s.data & 0xff;
1040                 } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
1041 
1042                 /* Update in_fif_p_count for it's offset with respect to out_p_count */
1043                 in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
1044 
1045                 /* Read the OUT_P_COUNT from the debug select */
1046                 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
1047                 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1048                 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1049                 out_p_count = (dbg_data.s.data>>1) & 0xff;
1050 
1051                 /* Check that the two counters are aligned */
1052                 if (out_p_count != in_fif_p_count) {
1053                         cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
1054                         while (in_fif_p_count != 0) {
1055                                 cvmx_write64_uint32(write_address, 0);
1056                                 __delay(10000);
1057                                 in_fif_p_count = (in_fif_p_count + 1) & 0xff;
1058                         }
1059                         /*
1060                          * The EBH5200 board swapped the PCIe reset
1061                          * lines on the board. This means we must
1062                          * bring both links down and up, which will
1063                          * cause the PCIe0 to need alignment
1064                          * again. Lots of messages will be displayed,
1065                          * but everything should work
1066                          */
1067                         if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
1068                                 (pcie_port == 1))
1069                                 cvmx_pcie_rc_initialize(0);
1070                         /* Rety bringing this port up */
1071                         goto retry;
1072                 }
1073         }
1074 
1075         /* Display the link status */
1076         pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1077         cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
1078 
1079         return 0;
1080 }
1081 
1082 /**
1083   * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1084  * port from reset to a link up state. Software can then begin
1085  * configuring the rest of the link.
1086  *
1087  * @pcie_port: PCIe port to initialize
1088  *
1089  * Return Zero on success.
1090  */
1091 static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
1092 {
1093         uint64_t start_cycle;
1094         union cvmx_pemx_ctl_status pem_ctl_status;
1095         union cvmx_pciercx_cfg032 pciercx_cfg032;
1096         union cvmx_pciercx_cfg448 pciercx_cfg448;
1097 
1098         /* Bring up the link */
1099         pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1100         pem_ctl_status.s.lnk_enb = 1;
1101         cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
1102 
1103         /* Wait for the link to come up */
1104         start_cycle = cvmx_get_cycle();
1105         do {
1106                 if (cvmx_get_cycle() - start_cycle >  octeon_get_clock_rate())
1107                         return -1;
1108                 __delay(10000);
1109                 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1110         } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
1111 
1112         /*
1113          * Update the Replay Time Limit. Empirically, some PCIe
1114          * devices take a little longer to respond than expected under
1115          * load. As a workaround for this we configure the Replay Time
1116          * Limit to the value expected for a 512 byte MPS instead of
1117          * our actual 256 byte MPS. The numbers below are directly
1118          * from the PCIe spec table 3-4
1119          */
1120         pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1121         switch (pciercx_cfg032.s.nlw) {
1122         case 1: /* 1 lane */
1123                 pciercx_cfg448.s.rtl = 1677;
1124                 break;
1125         case 2: /* 2 lanes */
1126                 pciercx_cfg448.s.rtl = 867;
1127                 break;
1128         case 4: /* 4 lanes */
1129                 pciercx_cfg448.s.rtl = 462;
1130                 break;
1131         case 8: /* 8 lanes */
1132                 pciercx_cfg448.s.rtl = 258;
1133                 break;
1134         }
1135         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
1136 
1137         return 0;
1138 }
1139 
1140 
1141 /**
1142  * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1143  * the bus.
1144  *
1145  * @pcie_port: PCIe port to initialize
1146  *
1147  * Returns Zero on success.
1148  */
1149 static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1150 {
1151         int i;
1152         union cvmx_ciu_soft_prst ciu_soft_prst;
1153         union cvmx_mio_rst_ctlx mio_rst_ctl;
1154         union cvmx_pemx_bar_ctl pemx_bar_ctl;
1155         union cvmx_pemx_ctl_status pemx_ctl_status;
1156         union cvmx_pemx_bist_status pemx_bist_status;
1157         union cvmx_pemx_bist_status2 pemx_bist_status2;
1158         union cvmx_pciercx_cfg032 pciercx_cfg032;
1159         union cvmx_pciercx_cfg515 pciercx_cfg515;
1160         union cvmx_sli_ctl_portx sli_ctl_portx;
1161         union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
1162         union cvmx_sli_mem_access_subidx mem_access_subid;
1163         union cvmx_sriox_status_reg sriox_status_reg;
1164         union cvmx_pemx_bar1_indexx bar1_index;
1165 
1166         if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
1167                 /* Make sure this interface isn't SRIO */
1168                 if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
1169                         /*
1170                          * The CN66XX requires reading the
1171                          * MIO_QLMX_CFG register to figure out the
1172                          * port type.
1173                          */
1174                         union cvmx_mio_qlmx_cfg qlmx_cfg;
1175                         qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
1176 
1177                         if (qlmx_cfg.s.qlm_spd == 15) {
1178                                 pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
1179                                 return -1;
1180                         }
1181 
1182                         switch (qlmx_cfg.s.qlm_spd) {
1183                         case 0x1: /* SRIO 1x4 short */
1184                         case 0x3: /* SRIO 1x4 long */
1185                         case 0x4: /* SRIO 2x2 short */
1186                         case 0x6: /* SRIO 2x2 long */
1187                                 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1188                                 return -1;
1189                         case 0x9: /* SGMII */
1190                                 pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
1191                                 return -1;
1192                         case 0xb: /* XAUI */
1193                                 pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
1194                                 return -1;
1195                         case 0x0: /* PCIE gen2 */
1196                         case 0x8: /* PCIE gen2 (alias) */
1197                         case 0x2: /* PCIE gen1 */
1198                         case 0xa: /* PCIE gen1 (alias) */
1199                                 break;
1200                         default:
1201                                 pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
1202                                 return -1;
1203                         }
1204                 } else {
1205                         sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
1206                         if (sriox_status_reg.s.srio) {
1207                                 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1208                                 return -1;
1209                         }
1210                 }
1211         }
1212 
1213 #if 0
1214     /* This code is so that the PCIe analyzer is able to see 63XX traffic */
1215         pr_notice("PCIE : init for pcie analyzer.\n");
1216         cvmx_helper_qlm_jtag_init();
1217         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1218         cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1219         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1220         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1221         cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1222         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1223         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1224         cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1225         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1226         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1227         cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1228         cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1229         cvmx_helper_qlm_jtag_update(pcie_port);
1230 #endif
1231 
1232         /* Make sure we aren't trying to setup a target mode interface in host mode */
1233         mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
1234         if (!mio_rst_ctl.s.host_mode) {
1235                 pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
1236                 return -1;
1237         }
1238 
1239         /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
1240         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
1241                 if (pcie_port) {
1242                         union cvmx_ciu_qlm1 ciu_qlm;
1243                         ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
1244                         ciu_qlm.s.txbypass = 1;
1245                         ciu_qlm.s.txdeemph = 5;
1246                         ciu_qlm.s.txmargin = 0x17;
1247                         cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
1248                 } else {
1249                         union cvmx_ciu_qlm0 ciu_qlm;
1250                         ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
1251                         ciu_qlm.s.txbypass = 1;
1252                         ciu_qlm.s.txdeemph = 5;
1253                         ciu_qlm.s.txmargin = 0x17;
1254                         cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
1255                 }
1256         }
1257         /* Bring the PCIe out of reset */
1258         if (pcie_port)
1259                 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1260         else
1261                 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1262         /*
1263          * After a chip reset the PCIe will also be in reset. If it
1264          * isn't, most likely someone is trying to init it again
1265          * without a proper PCIe reset
1266          */
1267         if (ciu_soft_prst.s.soft_prst == 0) {
1268                 /* Reset the port */
1269                 ciu_soft_prst.s.soft_prst = 1;
1270                 if (pcie_port)
1271                         cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1272                 else
1273                         cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1274                 /* Wait until pcie resets the ports. */
1275                 udelay(2000);
1276         }
1277         if (pcie_port) {
1278                 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1279                 ciu_soft_prst.s.soft_prst = 0;
1280                 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1281         } else {
1282                 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1283                 ciu_soft_prst.s.soft_prst = 0;
1284                 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1285         }
1286 
1287         /* Wait for PCIe reset to complete */
1288         udelay(1000);
1289 
1290         /*
1291          * Check and make sure PCIe came out of reset. If it doesn't
1292          * the board probably hasn't wired the clocks up and the
1293          * interface should be skipped.
1294          */
1295         if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
1296                 pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
1297                 return -1;
1298         }
1299 
1300         /* Check BIST status */
1301         pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
1302         if (pemx_bist_status.u64)
1303                 pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
1304         pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
1305         /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
1306         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
1307                 pemx_bist_status2.u64 &= ~0x3full;
1308         if (pemx_bist_status2.u64)
1309                 pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
1310 
1311         /* Initialize the config space CSRs */
1312         __cvmx_pcie_rc_initialize_config_space(pcie_port);
1313 
1314         /* Enable gen2 speed selection */
1315         pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1316         pciercx_cfg515.s.dsc = 1;
1317         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1318 
1319         /* Bring the link up */
1320         if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1321                 /*
1322                  * Some gen1 devices don't handle the gen 2 training
1323                  * correctly. Disable gen2 and try again with only
1324                  * gen1
1325                  */
1326                 union cvmx_pciercx_cfg031 pciercx_cfg031;
1327                 pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
1328                 pciercx_cfg031.s.mls = 1;
1329                 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
1330                 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1331                         pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
1332                         return -1;
1333                 }
1334         }
1335 
1336         /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1337         sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
1338         sli_mem_access_ctl.s.max_word = 0;      /* Allow 16 words to combine */
1339         sli_mem_access_ctl.s.timer = 127;       /* Wait up to 127 cycles for more data */
1340         cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
1341 
1342         /* Setup Mem access SubDIDs */
1343         mem_access_subid.u64 = 0;
1344         mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1345         mem_access_subid.s.nmerge = 0;  /* Allow merging as it works on CN6XXX. */
1346         mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
1347         mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
1348         mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
1349         mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
1350         /* PCIe Adddress Bits <63:34>. */
1351         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1352                 mem_access_subid.cn68xx.ba = 0;
1353         else
1354                 mem_access_subid.s.ba = 0;
1355 
1356         /*
1357          * Setup mem access 12-15 for port 0, 16-19 for port 1,
1358          * supplying 36 bits of address space.
1359          */
1360         for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1361                 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1362                 /* Set each SUBID to extend the addressable range */
1363                 __cvmx_increment_ba(&mem_access_subid);
1364         }
1365 
1366         /*
1367          * Disable the peer to peer forwarding register. This must be
1368          * setup by the OS after it enumerates the bus and assigns
1369          * addresses to the PCIe busses.
1370          */
1371         for (i = 0; i < 4; i++) {
1372                 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1373                 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1374         }
1375 
1376         /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1377         cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
1378 
1379         /*
1380          * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
1381          * precedence where they overlap. It also overlaps with the
1382          * device addresses, so make sure the peer to peer forwarding
1383          * is set right.
1384          */
1385         cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
1386 
1387         /*
1388          * Setup BAR2 attributes
1389          * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
1390          * - PTLP_RO,CTLP_RO should normally be set (except for debug).
1391          * - WAIT_COM=0 will likely work for all applications.
1392          * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
1393          */
1394         pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
1395         pemx_bar_ctl.s.bar1_siz = 3;  /* 256MB BAR1*/
1396         pemx_bar_ctl.s.bar2_enb = 1;
1397         pemx_bar_ctl.s.bar2_esx = 1;
1398         pemx_bar_ctl.s.bar2_cax = 0;
1399         cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
1400         sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
1401         sli_ctl_portx.s.ptlp_ro = 1;
1402         sli_ctl_portx.s.ctlp_ro = 1;
1403         sli_ctl_portx.s.wait_com = 0;
1404         sli_ctl_portx.s.waitl_com = 0;
1405         cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
1406 
1407         /* BAR1 follows BAR2 */
1408         cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
1409 
1410         bar1_index.u64 = 0;
1411         bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1412         bar1_index.s.ca = 1;       /* Not Cached */
1413         bar1_index.s.end_swp = 1;  /* Endian Swap mode */
1414         bar1_index.s.addr_v = 1;   /* Valid entry */
1415 
1416         for (i = 0; i < 16; i++) {
1417                 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1418                 /* 256MB / 16 >> 22 == 4 */
1419                 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1420         }
1421 
1422         /*
1423          * Allow config retries for 250ms. Count is based off the 5Ghz
1424          * SERDES clock.
1425          */
1426         pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1427         pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
1428         cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
1429 
1430         /* Display the link status */
1431         pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1432         pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
1433 
1434         return 0;
1435 }
1436 
1437 /**
1438  * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
1439  *
1440  * @pcie_port: PCIe port to initialize
1441  *
1442  * Returns Zero on success
1443  */
1444 static int cvmx_pcie_rc_initialize(int pcie_port)
1445 {
1446         int result;
1447         if (octeon_has_feature(OCTEON_FEATURE_NPEI))
1448                 result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
1449         else
1450                 result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
1451         return result;
1452 }
1453 
1454 /* Above was cvmx-pcie.c, below original pcie.c */
1455 
1456 /**
1457  * Map a PCI device to the appropriate interrupt line
1458  *
1459  * @dev:    The Linux PCI device structure for the device to map
1460  * @slot:   The slot number for this device on __BUS 0__. Linux
1461  *               enumerates through all the bridges and figures out the
1462  *               slot on Bus 0 where this device eventually hooks to.
1463  * @pin:    The PCI interrupt pin read from the device, then swizzled
1464  *               as it goes through each bridge.
1465  * Returns Interrupt number for the device
1466  */
1467 int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1468 {
1469         /*
1470          * The EBH5600 board with the PCI to PCIe bridge mistakenly
1471          * wires the first slot for both device id 2 and interrupt
1472          * A. According to the PCI spec, device id 2 should be C. The
1473          * following kludge attempts to fix this.
1474          */
1475         if (strstr(octeon_board_type_string(), "EBH5600") &&
1476             dev->bus && dev->bus->parent) {
1477                 /*
1478                  * Iterate all the way up the device chain and find
1479                  * the root bus.
1480                  */
1481                 while (dev->bus && dev->bus->parent)
1482                         dev = to_pci_dev(dev->bus->bridge);
1483                 /*
1484                  * If the root bus is number 0 and the PEX 8114 is the
1485                  * root, assume we are behind the miswired bus. We
1486                  * need to correct the swizzle level by two. Yuck.
1487                  */
1488                 if ((dev->bus->number == 1) &&
1489                     (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1490                         /*
1491                          * The pin field is one based, not zero. We
1492                          * need to swizzle it by minus two.
1493                          */
1494                         pin = ((pin - 3) & 3) + 1;
1495                 }
1496         }
1497         /*
1498          * The -1 is because pin starts with one, not zero. It might
1499          * be that this equation needs to include the slot number, but
1500          * I don't have hardware to check that against.
1501          */
1502         return pin - 1 + OCTEON_IRQ_PCI_INT0;
1503 }
1504 
1505 static  void set_cfg_read_retry(u32 retry_cnt)
1506 {
1507         union cvmx_pemx_ctl_status pemx_ctl;
1508         pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1509         pemx_ctl.s.cfg_rtry = retry_cnt;
1510         cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1511 }
1512 
1513 
1514 static u32 disable_cfg_read_retry(void)
1515 {
1516         u32 retry_cnt;
1517 
1518         union cvmx_pemx_ctl_status pemx_ctl;
1519         pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1520         retry_cnt =  pemx_ctl.s.cfg_rtry;
1521         pemx_ctl.s.cfg_rtry = 0;
1522         cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1523         return retry_cnt;
1524 }
1525 
1526 static int is_cfg_retry(void)
1527 {
1528         union cvmx_pemx_int_sum pemx_int_sum;
1529         pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
1530         if (pemx_int_sum.s.crs_dr)
1531                 return 1;
1532         return 0;
1533 }
1534 
1535 /*
1536  * Read a value from configuration space
1537  *
1538  */
1539 static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
1540                                    unsigned int devfn, int reg, int size,
1541                                    u32 *val)
1542 {
1543         union octeon_cvmemctl cvmmemctl;
1544         union octeon_cvmemctl cvmmemctl_save;
1545         int bus_number = bus->number;
1546         int cfg_retry = 0;
1547         int retry_cnt = 0;
1548         int max_retry_cnt = 10;
1549         u32 cfg_retry_cnt = 0;
1550 
1551         cvmmemctl_save.u64 = 0;
1552         BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1553         /*
1554          * For the top level bus make sure our hardware bus number
1555          * matches the software one
1556          */
1557         if (bus->parent == NULL) {
1558                 if (enable_pcie_bus_num_war[pcie_port])
1559                         bus_number = 0;
1560                 else {
1561                         union cvmx_pciercx_cfg006 pciercx_cfg006;
1562                         pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1563                                              CVMX_PCIERCX_CFG006(pcie_port));
1564                         if (pciercx_cfg006.s.pbnum != bus_number) {
1565                                 pciercx_cfg006.s.pbnum = bus_number;
1566                                 pciercx_cfg006.s.sbnum = bus_number;
1567                                 pciercx_cfg006.s.subbnum = bus_number;
1568                                 cvmx_pcie_cfgx_write(pcie_port,
1569                                             CVMX_PCIERCX_CFG006(pcie_port),
1570                                             pciercx_cfg006.u32);
1571                         }
1572                 }
1573         }
1574 
1575         /*
1576          * PCIe only has a single device connected to Octeon. It is
1577          * always device ID 0. Don't bother doing reads for other
1578          * device IDs on the first segment.
1579          */
1580         if ((bus->parent == NULL) && (devfn >> 3 != 0))
1581                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1582 
1583         /*
1584          * The following is a workaround for the CN57XX, CN56XX,
1585          * CN55XX, and CN54XX errata with PCIe config reads from non
1586          * existent devices.  These chips will hang the PCIe link if a
1587          * config read is performed that causes a UR response.
1588          */
1589         if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1590             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1591                 /*
1592                  * For our EBH5600 board, port 0 has a bridge with two
1593                  * PCI-X slots. We need a new special checks to make
1594                  * sure we only probe valid stuff.  The PCIe->PCI-X
1595                  * bridge only respondes to device ID 0, function
1596                  * 0-1
1597                  */
1598                 if ((bus->parent == NULL) && (devfn >= 2))
1599                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1600                 /*
1601                  * The PCI-X slots are device ID 2,3. Choose one of
1602                  * the below "if" blocks based on what is plugged into
1603                  * the board.
1604                  */
1605 #if 1
1606                 /* Use this option if you aren't using either slot */
1607                 if (bus_number == 2)
1608                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1609 #elif 0
1610                 /*
1611                  * Use this option if you are using the first slot but
1612                  * not the second.
1613                  */
1614                 if ((bus_number == 2) && (devfn >> 3 != 2))
1615                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1616 #elif 0
1617                 /*
1618                  * Use this option if you are using the second slot
1619                  * but not the first.
1620                  */
1621                 if ((bus_number == 2) && (devfn >> 3 != 3))
1622                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1623 #elif 0
1624                 /* Use this opion if you are using both slots */
1625                 if ((bus_number == 2) &&
1626                     !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1627                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1628 #endif
1629 
1630                 /* The following #if gives a more complicated example. This is
1631                    the required checks for running a Nitrox CN16XX-NHBX in the
1632                    slot of the EBH5600. This card has a PLX PCIe bridge with
1633                    four Nitrox PLX parts behind it */
1634 #if 0
1635                 /* PLX bridge with 4 ports */
1636                 if ((bus_number == 4) &&
1637                     !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
1638                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1639                 /* Nitrox behind PLX 1 */
1640                 if ((bus_number == 5) && (devfn >> 3 != 0))
1641                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1642                 /* Nitrox behind PLX 2 */
1643                 if ((bus_number == 6) && (devfn >> 3 != 0))
1644                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1645                 /* Nitrox behind PLX 3 */
1646                 if ((bus_number == 7) && (devfn >> 3 != 0))
1647                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1648                 /* Nitrox behind PLX 4 */
1649                 if ((bus_number == 8) && (devfn >> 3 != 0))
1650                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1651 #endif
1652 
1653                 /*
1654                  * Shorten the DID timeout so bus errors for PCIe
1655                  * config reads from non existent devices happen
1656                  * faster. This allows us to continue booting even if
1657                  * the above "if" checks are wrong.  Once one of these
1658                  * errors happens, the PCIe port is dead.
1659                  */
1660                 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1661                 cvmmemctl.u64 = cvmmemctl_save.u64;
1662                 cvmmemctl.s.didtto = 2;
1663                 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1664         }
1665 
1666         if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1667                 cfg_retry_cnt = disable_cfg_read_retry();
1668 
1669         pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
1670                  " size=%d ", pcie_port, bus_number, devfn, reg, size);
1671         do {
1672                 switch (size) {
1673                 case 4:
1674                         *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1675                                 devfn >> 3, devfn & 0x7, reg);
1676                 break;
1677                 case 2:
1678                         *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1679                                 devfn >> 3, devfn & 0x7, reg);
1680                 break;
1681                 case 1:
1682                         *val = cvmx_pcie_config_read8(pcie_port, bus_number,
1683                                 devfn >> 3, devfn & 0x7, reg);
1684                 break;
1685                 default:
1686                         if (OCTEON_IS_MODEL(OCTEON_CN63XX))
1687                                 set_cfg_read_retry(cfg_retry_cnt);
1688                         return PCIBIOS_FUNC_NOT_SUPPORTED;
1689                 }
1690                 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
1691                         (enable_pcie_14459_war)) {
1692                         cfg_retry = is_cfg_retry();
1693                         retry_cnt++;
1694                         if (retry_cnt > max_retry_cnt) {
1695                                 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
1696                                        retry_cnt);
1697                                 cfg_retry = 0;
1698                         }
1699                 }
1700         } while (cfg_retry);
1701 
1702         if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1703                 set_cfg_read_retry(cfg_retry_cnt);
1704         pr_debug("val=%08x  : tries=%02d\n", *val, retry_cnt);
1705         if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1706             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1707                 write_c0_cvmmemctl(cvmmemctl_save.u64);
1708         return PCIBIOS_SUCCESSFUL;
1709 }
1710 
1711 static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1712                                     int reg, int size, u32 *val)
1713 {
1714         return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1715 }
1716 
1717 static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1718                                     int reg, int size, u32 *val)
1719 {
1720         return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1721 }
1722 
1723 static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
1724                                     int reg, int size, u32 *val)
1725 {
1726         return PCIBIOS_FUNC_NOT_SUPPORTED;
1727 }
1728 
1729 /*
1730  * Write a value to PCI configuration space
1731  */
1732 static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
1733                                     unsigned int devfn, int reg,
1734                                     int size, u32 val)
1735 {
1736         int bus_number = bus->number;
1737 
1738         BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1739 
1740         if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
1741                 bus_number = 0;
1742 
1743         pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
1744                  " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
1745                  reg, size, val);
1746 
1747 
1748         switch (size) {
1749         case 4:
1750                 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1751                                          devfn & 0x7, reg, val);
1752                 break;
1753         case 2:
1754                 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1755                                          devfn & 0x7, reg, val);
1756                 break;
1757         case 1:
1758                 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1759                                         devfn & 0x7, reg, val);
1760                 break;
1761         default:
1762                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1763         }
1764         return PCIBIOS_SUCCESSFUL;
1765 }
1766 
1767 static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1768                                      int reg, int size, u32 val)
1769 {
1770         return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1771 }
1772 
1773 static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1774                                      int reg, int size, u32 val)
1775 {
1776         return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1777 }
1778 
1779 static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
1780                                      int reg, int size, u32 val)
1781 {
1782         return PCIBIOS_FUNC_NOT_SUPPORTED;
1783 }
1784 
1785 static struct pci_ops octeon_pcie0_ops = {
1786         .read   = octeon_pcie0_read_config,
1787         .write  = octeon_pcie0_write_config,
1788 };
1789 
1790 static struct resource octeon_pcie0_mem_resource = {
1791         .name = "Octeon PCIe0 MEM",
1792         .flags = IORESOURCE_MEM,
1793 };
1794 
1795 static struct resource octeon_pcie0_io_resource = {
1796         .name = "Octeon PCIe0 IO",
1797         .flags = IORESOURCE_IO,
1798 };
1799 
1800 static struct pci_controller octeon_pcie0_controller = {
1801         .pci_ops = &octeon_pcie0_ops,
1802         .mem_resource = &octeon_pcie0_mem_resource,
1803         .io_resource = &octeon_pcie0_io_resource,
1804 };
1805 
1806 static struct pci_ops octeon_pcie1_ops = {
1807         .read   = octeon_pcie1_read_config,
1808         .write  = octeon_pcie1_write_config,
1809 };
1810 
1811 static struct resource octeon_pcie1_mem_resource = {
1812         .name = "Octeon PCIe1 MEM",
1813         .flags = IORESOURCE_MEM,
1814 };
1815 
1816 static struct resource octeon_pcie1_io_resource = {
1817         .name = "Octeon PCIe1 IO",
1818         .flags = IORESOURCE_IO,
1819 };
1820 
1821 static struct pci_controller octeon_pcie1_controller = {
1822         .pci_ops = &octeon_pcie1_ops,
1823         .mem_resource = &octeon_pcie1_mem_resource,
1824         .io_resource = &octeon_pcie1_io_resource,
1825 };
1826 
1827 static struct pci_ops octeon_dummy_ops = {
1828         .read   = octeon_dummy_read_config,
1829         .write  = octeon_dummy_write_config,
1830 };
1831 
1832 static struct resource octeon_dummy_mem_resource = {
1833         .name = "Virtual PCIe MEM",
1834         .flags = IORESOURCE_MEM,
1835 };
1836 
1837 static struct resource octeon_dummy_io_resource = {
1838         .name = "Virtual PCIe IO",
1839         .flags = IORESOURCE_IO,
1840 };
1841 
1842 static struct pci_controller octeon_dummy_controller = {
1843         .pci_ops = &octeon_dummy_ops,
1844         .mem_resource = &octeon_dummy_mem_resource,
1845         .io_resource = &octeon_dummy_io_resource,
1846 };
1847 
1848 static int device_needs_bus_num_war(uint32_t deviceid)
1849 {
1850 #define IDT_VENDOR_ID 0x111d
1851 
1852         if ((deviceid  & 0xffff) == IDT_VENDOR_ID)
1853                 return 1;
1854         return 0;
1855 }
1856 
1857 /**
1858  * Initialize the Octeon PCIe controllers
1859  *
1860  * Returns
1861  */
1862 static int __init octeon_pcie_setup(void)
1863 {
1864         int result;
1865         int host_mode;
1866         int srio_war15205 = 0, port;
1867         union cvmx_sli_ctl_portx sli_ctl_portx;
1868         union cvmx_sriox_status_reg sriox_status_reg;
1869 
1870         /* These chips don't have PCIe */
1871         if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1872                 return 0;
1873 
1874         /* No PCIe simulation */
1875         if (octeon_is_simulation())
1876                 return 0;
1877 
1878         /* Disable PCI if instructed on the command line */
1879         if (pcie_disable)
1880                 return 0;
1881 
1882         /* Point pcibios_map_irq() to the PCIe version of it */
1883         octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1884 
1885         /*
1886          * PCIe I/O range. It is based on port 0 but includes up until
1887          * port 1's end.
1888          */
1889         set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1890         ioport_resource.start = 0;
1891         ioport_resource.end =
1892                 cvmx_pcie_get_io_base_address(1) -
1893                 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1894 
1895         /*
1896          * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
1897          * don't work if the primary bus number is zero. Here we add a fake
1898          * PCIe controller that the kernel will give bus 0. This allows
1899          * us to not change the normal kernel bus enumeration
1900          */
1901         octeon_dummy_controller.io_map_base = -1;
1902         octeon_dummy_controller.mem_resource->start = (1ull<<48);
1903         octeon_dummy_controller.mem_resource->end = (1ull<<48);
1904         register_pci_controller(&octeon_dummy_controller);
1905 
1906         if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1907                 union cvmx_npei_ctl_status npei_ctl_status;
1908                 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1909                 host_mode = npei_ctl_status.s.host_mode;
1910                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1911         } else {
1912                 union cvmx_mio_rst_ctlx mio_rst_ctl;
1913                 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
1914                 host_mode = mio_rst_ctl.s.host_mode;
1915                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
1916         }
1917 
1918         if (host_mode) {
1919                 pr_notice("PCIe: Initializing port 0\n");
1920                 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1921                 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1922                         OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1923                         sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
1924                         if (sriox_status_reg.s.srio) {
1925                                 srio_war15205 += 1;      /* Port is SRIO */
1926                                 port = 0;
1927                         }
1928                 }
1929                 result = cvmx_pcie_rc_initialize(0);
1930                 if (result == 0) {
1931                         uint32_t device0;
1932                         /* Memory offsets are physical addresses */
1933                         octeon_pcie0_controller.mem_offset =
1934                                 cvmx_pcie_get_mem_base_address(0);
1935                         /* IO offsets are Mips virtual addresses */
1936                         octeon_pcie0_controller.io_map_base =
1937                                 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1938                                                 (0));
1939                         octeon_pcie0_controller.io_offset = 0;
1940                         /*
1941                          * To keep things similar to PCI, we start
1942                          * device addresses at the same place as PCI
1943                          * uisng big bar support. This normally
1944                          * translates to 4GB-256MB, which is the same
1945                          * as most x86 PCs.
1946                          */
1947                         octeon_pcie0_controller.mem_resource->start =
1948                                 cvmx_pcie_get_mem_base_address(0) +
1949                                 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1950                         octeon_pcie0_controller.mem_resource->end =
1951                                 cvmx_pcie_get_mem_base_address(0) +
1952                                 cvmx_pcie_get_mem_size(0) - 1;
1953                         /*
1954                          * Ports must be above 16KB for the ISA bus
1955                          * filtering in the PCI-X to PCI bridge.
1956                          */
1957                         octeon_pcie0_controller.io_resource->start = 4 << 10;
1958                         octeon_pcie0_controller.io_resource->end =
1959                                 cvmx_pcie_get_io_size(0) - 1;
1960                         msleep(100); /* Some devices need extra time */
1961                         register_pci_controller(&octeon_pcie0_controller);
1962                         device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
1963                         enable_pcie_bus_num_war[0] =
1964                                 device_needs_bus_num_war(device0);
1965                 }
1966         } else {
1967                 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1968                 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1969                 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1970                         OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1971                         srio_war15205 += 1;
1972                         port = 0;
1973                 }
1974         }
1975 
1976         if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1977                 host_mode = 1;
1978                 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1979                 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1980                         union cvmx_npei_dbg_data dbg_data;
1981                         dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1982                         if (dbg_data.cn52xx.qlm0_link_width)
1983                                 host_mode = 0;
1984                 }
1985         } else {
1986                 union cvmx_mio_rst_ctlx mio_rst_ctl;
1987                 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
1988                 host_mode = mio_rst_ctl.s.host_mode;
1989         }
1990 
1991         if (host_mode) {
1992                 pr_notice("PCIe: Initializing port 1\n");
1993                 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1994                 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1995                         OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1996                         sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
1997                         if (sriox_status_reg.s.srio) {
1998                                 srio_war15205 += 1;      /* Port is SRIO */
1999                                 port = 1;
2000                         }
2001                 }
2002                 result = cvmx_pcie_rc_initialize(1);
2003                 if (result == 0) {
2004                         uint32_t device0;
2005                         /* Memory offsets are physical addresses */
2006                         octeon_pcie1_controller.mem_offset =
2007                                 cvmx_pcie_get_mem_base_address(1);
2008                         /*
2009                          * To calculate the address for accessing the 2nd PCIe device,
2010                          * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
2011                          * (ioport_map()) value is added to
2012                          * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
2013                          * only once based on first PCIe. Also changing 'io_map_base'
2014                          * based on first slot's value so that both the routines will
2015                          * work properly.
2016                          */
2017                         octeon_pcie1_controller.io_map_base =
2018                                 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
2019                         /* IO offsets are Mips virtual addresses */
2020                         octeon_pcie1_controller.io_offset =
2021                                 cvmx_pcie_get_io_base_address(1) -
2022                                 cvmx_pcie_get_io_base_address(0);
2023                         /*
2024                          * To keep things similar to PCI, we start device
2025                          * addresses at the same place as PCI uisng big bar
2026                          * support. This normally translates to 4GB-256MB,
2027                          * which is the same as most x86 PCs.
2028                          */
2029                         octeon_pcie1_controller.mem_resource->start =
2030                                 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
2031                                 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
2032                         octeon_pcie1_controller.mem_resource->end =
2033                                 cvmx_pcie_get_mem_base_address(1) +
2034                                 cvmx_pcie_get_mem_size(1) - 1;
2035                         /*
2036                          * Ports must be above 16KB for the ISA bus filtering
2037                          * in the PCI-X to PCI bridge.
2038                          */
2039                         octeon_pcie1_controller.io_resource->start =
2040                                 cvmx_pcie_get_io_base_address(1) -
2041                                 cvmx_pcie_get_io_base_address(0);
2042                         octeon_pcie1_controller.io_resource->end =
2043                                 octeon_pcie1_controller.io_resource->start +
2044                                 cvmx_pcie_get_io_size(1) - 1;
2045                         msleep(100); /* Some devices need extra time */
2046                         register_pci_controller(&octeon_pcie1_controller);
2047                         device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
2048                         enable_pcie_bus_num_war[1] =
2049                                 device_needs_bus_num_war(device0);
2050                 }
2051         } else {
2052                 pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
2053                 /* CN63XX pass 1_x/2.0 errata PCIe-15205  */
2054                 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2055                         OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2056                         srio_war15205 += 1;
2057                         port = 1;
2058                 }
2059         }
2060 
2061         /*
2062          * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
2063          * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
2064          * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
2065          * from the previous set values
2066          */
2067         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2068                 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2069                 if (srio_war15205 == 1) {
2070                         sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
2071                         sli_ctl_portx.s.inta_map = 1;
2072                         sli_ctl_portx.s.intb_map = 1;
2073                         sli_ctl_portx.s.intc_map = 1;
2074                         sli_ctl_portx.s.intd_map = 1;
2075                         cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
2076 
2077                         sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
2078                         sli_ctl_portx.s.inta_map = 0;
2079                         sli_ctl_portx.s.intb_map = 0;
2080                         sli_ctl_portx.s.intc_map = 0;
2081                         sli_ctl_portx.s.intd_map = 0;
2082                         cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
2083                 }
2084         }
2085 
2086         octeon_pci_dma_init();
2087 
2088         return 0;
2089 }
2090 arch_initcall(octeon_pcie_setup);
2091 

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