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Linux/arch/mips/sibyte/bcm1480/smp.c

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  1 /*
  2  * Copyright (C) 2001,2002,2004 Broadcom Corporation
  3  *
  4  * This program is free software; you can redistribute it and/or
  5  * modify it under the terms of the GNU General Public License
  6  * as published by the Free Software Foundation; either version 2
  7  * of the License, or (at your option) any later version.
  8  *
  9  * This program is distributed in the hope that it will be useful,
 10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12  * GNU General Public License for more details.
 13  *
 14  * You should have received a copy of the GNU General Public License
 15  * along with this program; if not, write to the Free Software
 16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 17  */
 18 
 19 #include <linux/init.h>
 20 #include <linux/delay.h>
 21 #include <linux/smp.h>
 22 #include <linux/kernel_stat.h>
 23 #include <linux/sched.h>
 24 #include <linux/sched/task_stack.h>
 25 
 26 #include <asm/mmu_context.h>
 27 #include <asm/io.h>
 28 #include <asm/fw/cfe/cfe_api.h>
 29 #include <asm/sibyte/sb1250.h>
 30 #include <asm/sibyte/bcm1480_regs.h>
 31 #include <asm/sibyte/bcm1480_int.h>
 32 
 33 /*
 34  * These are routines for dealing with the bcm1480 smp capabilities
 35  * independent of board/firmware
 36  */
 37 
 38 static void *mailbox_0_set_regs[] = {
 39         IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 40         IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 41         IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 42         IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 43 };
 44 
 45 static void *mailbox_0_clear_regs[] = {
 46         IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 47         IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 48         IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 49         IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 50 };
 51 
 52 static void *mailbox_0_regs[] = {
 53         IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
 54         IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
 55         IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
 56         IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
 57 };
 58 
 59 /*
 60  * SMP init and finish on secondary CPUs
 61  */
 62 void bcm1480_smp_init(void)
 63 {
 64         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 65                 STATUSF_IP1 | STATUSF_IP0;
 66 
 67         /* Set interrupt mask, but don't enable */
 68         change_c0_status(ST0_IM, imask);
 69 }
 70 
 71 /*
 72  * These are routines for dealing with the sb1250 smp capabilities
 73  * independent of board/firmware
 74  */
 75 
 76 /*
 77  * Simple enough; everything is set up, so just poke the appropriate mailbox
 78  * register, and we should be set
 79  */
 80 static void bcm1480_send_ipi_single(int cpu, unsigned int action)
 81 {
 82         __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
 83 }
 84 
 85 static void bcm1480_send_ipi_mask(const struct cpumask *mask,
 86                                   unsigned int action)
 87 {
 88         unsigned int i;
 89 
 90         for_each_cpu(i, mask)
 91                 bcm1480_send_ipi_single(i, action);
 92 }
 93 
 94 /*
 95  * Code to run on secondary just after probing the CPU
 96  */
 97 static void bcm1480_init_secondary(void)
 98 {
 99         extern void bcm1480_smp_init(void);
100 
101         bcm1480_smp_init();
102 }
103 
104 /*
105  * Do any tidying up before marking online and running the idle
106  * loop
107  */
108 static void bcm1480_smp_finish(void)
109 {
110         extern void sb1480_clockevent_init(void);
111 
112         sb1480_clockevent_init();
113         local_irq_enable();
114 }
115 
116 /*
117  * Setup the PC, SP, and GP of a secondary processor and start it
118  * running!
119  */
120 static int bcm1480_boot_secondary(int cpu, struct task_struct *idle)
121 {
122         int retval;
123 
124         retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
125                                __KSTK_TOS(idle),
126                                (unsigned long)task_thread_info(idle), 0);
127         if (retval != 0)
128                 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
129         return retval;
130 }
131 
132 /*
133  * Use CFE to find out how many CPUs are available, setting up
134  * cpu_possible_mask and the logical/physical mappings.
135  * XXXKW will the boot CPU ever not be physical 0?
136  *
137  * Common setup before any secondaries are started
138  */
139 static void __init bcm1480_smp_setup(void)
140 {
141         int i, num;
142 
143         init_cpu_possible(cpumask_of(0));
144         __cpu_number_map[0] = 0;
145         __cpu_logical_map[0] = 0;
146 
147         for (i = 1, num = 0; i < NR_CPUS; i++) {
148                 if (cfe_cpu_stop(i) == 0) {
149                         set_cpu_possible(i, true);
150                         __cpu_number_map[i] = ++num;
151                         __cpu_logical_map[num] = i;
152                 }
153         }
154         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
155 }
156 
157 static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
158 {
159 }
160 
161 const struct plat_smp_ops bcm1480_smp_ops = {
162         .send_ipi_single        = bcm1480_send_ipi_single,
163         .send_ipi_mask          = bcm1480_send_ipi_mask,
164         .init_secondary         = bcm1480_init_secondary,
165         .smp_finish             = bcm1480_smp_finish,
166         .boot_secondary         = bcm1480_boot_secondary,
167         .smp_setup              = bcm1480_smp_setup,
168         .prepare_cpus           = bcm1480_prepare_cpus,
169 };
170 
171 void bcm1480_mailbox_interrupt(void)
172 {
173         int cpu = smp_processor_id();
174         int irq = K_BCM1480_INT_MBOX_0_0;
175         unsigned int action;
176 
177         kstat_incr_irq_this_cpu(irq);
178         /* Load the mailbox register to figure out what we're supposed to do */
179         action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
180 
181         /* Clear the mailbox to clear the interrupt */
182         __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
183 
184         if (action & SMP_RESCHEDULE_YOURSELF)
185                 scheduler_ipi();
186 
187         if (action & SMP_CALL_FUNCTION) {
188                 irq_enter();
189                 generic_smp_call_function_interrupt();
190                 irq_exit();
191         }
192 }
193 

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