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Linux/arch/mips/sni/time.c

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  1 #include <linux/types.h>
  2 #include <linux/interrupt.h>
  3 #include <linux/smp.h>
  4 #include <linux/time.h>
  5 #include <linux/clockchips.h>
  6 
  7 #include <asm/i8253.h>
  8 #include <asm/sni.h>
  9 #include <asm/time.h>
 10 #include <asm-generic/rtc.h>
 11 
 12 #define SNI_CLOCK_TICK_RATE     3686400
 13 #define SNI_COUNTER2_DIV        64
 14 #define SNI_COUNTER0_DIV        ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
 15 
 16 static void a20r_set_mode(enum clock_event_mode mode,
 17                           struct clock_event_device *evt)
 18 {
 19         switch (mode) {
 20         case CLOCK_EVT_MODE_PERIODIC:
 21                 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
 22                 wmb();
 23                 *(volatile u8 *)(A20R_PT_CLOCK_BASE +  0) = SNI_COUNTER0_DIV;
 24                 wmb();
 25                 *(volatile u8 *)(A20R_PT_CLOCK_BASE +  0) = SNI_COUNTER0_DIV >> 8;
 26                 wmb();
 27 
 28                 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4;
 29                 wmb();
 30                 *(volatile u8 *)(A20R_PT_CLOCK_BASE +  8) = SNI_COUNTER2_DIV;
 31                 wmb();
 32                 *(volatile u8 *)(A20R_PT_CLOCK_BASE +  8) = SNI_COUNTER2_DIV >> 8;
 33                 wmb();
 34 
 35                 break;
 36         case CLOCK_EVT_MODE_ONESHOT:
 37         case CLOCK_EVT_MODE_UNUSED:
 38         case CLOCK_EVT_MODE_SHUTDOWN:
 39                 break;
 40         case CLOCK_EVT_MODE_RESUME:
 41                 break;
 42         }
 43 }
 44 
 45 static struct clock_event_device a20r_clockevent_device = {
 46         .name           = "a20r-timer",
 47         .features       = CLOCK_EVT_FEAT_PERIODIC,
 48 
 49         /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
 50 
 51         .rating         = 300,
 52         .irq            = SNI_A20R_IRQ_TIMER,
 53         .set_mode       = a20r_set_mode,
 54 };
 55 
 56 static irqreturn_t a20r_interrupt(int irq, void *dev_id)
 57 {
 58         struct clock_event_device *cd = dev_id;
 59 
 60         *(volatile u8 *)A20R_PT_TIM0_ACK = 0;
 61         wmb();
 62 
 63         cd->event_handler(cd);
 64 
 65         return IRQ_HANDLED;
 66 }
 67 
 68 static struct irqaction a20r_irqaction = {
 69         .handler        = a20r_interrupt,
 70         .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
 71         .name           = "a20r-timer",
 72 };
 73 
 74 /*
 75  * a20r platform uses 2 counters to divide the input frequency.
 76  * Counter 2 output is connected to Counter 0 & 1 input.
 77  */
 78 static void __init sni_a20r_timer_setup(void)
 79 {
 80         struct clock_event_device *cd = &a20r_clockevent_device;
 81         struct irqaction *action = &a20r_irqaction;
 82         unsigned int cpu = smp_processor_id();
 83 
 84         cd->cpumask             = cpumask_of(cpu);
 85         clockevents_register_device(cd);
 86         action->dev_id = cd;
 87         setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
 88 }
 89 
 90 #define SNI_8254_TICK_RATE        1193182UL
 91 
 92 #define SNI_8254_TCSAMP_COUNTER   ((SNI_8254_TICK_RATE / HZ) + 255)
 93 
 94 static __init unsigned long dosample(void)
 95 {
 96         u32 ct0, ct1;
 97         volatile u8 msb, lsb;
 98 
 99         /* Start the counter. */
100         outb_p(0x34, 0x43);
101         outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
102         outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
103 
104         /* Get initial counter invariant */
105         ct0 = read_c0_count();
106 
107         /* Latch and spin until top byte of counter0 is zero */
108         do {
109                 outb(0x00, 0x43);
110                 lsb = inb(0x40);
111                 msb = inb(0x40);
112                 ct1 = read_c0_count();
113         } while (msb);
114 
115         /* Stop the counter. */
116         outb(0x38, 0x43);
117         /*
118          * Return the difference, this is how far the r4k counter increments
119          * for every 1/HZ seconds. We round off the nearest 1 MHz of master
120          * clock (= 1000000 / HZ / 2).
121          */
122         /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
123         return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
124 }
125 
126 /*
127  * Here we need to calibrate the cycle counter to at least be close.
128  */
129 void __init plat_time_init(void)
130 {
131         unsigned long r4k_ticks[3];
132         unsigned long r4k_tick;
133 
134         /*
135          * Figure out the r4k offset, the algorithm is very simple and works in
136          * _all_ cases as long as the 8254 counter register itself works ok (as
137          * an interrupt driving timer it does not because of bug, this is why
138          * we are using the onchip r4k counter/compare register to serve this
139          * purpose, but for r4k_offset calculation it will work ok for us).
140          * There are other very complicated ways of performing this calculation
141          * but this one works just fine so I am not going to futz around. ;-)
142          */
143         printk(KERN_INFO "Calibrating system timer... ");
144         dosample();     /* Prime cache. */
145         dosample();     /* Prime cache. */
146         /* Zero is NOT an option. */
147         do {
148                 r4k_ticks[0] = dosample();
149         } while (!r4k_ticks[0]);
150         do {
151                 r4k_ticks[1] = dosample();
152         } while (!r4k_ticks[1]);
153 
154         if (r4k_ticks[0] != r4k_ticks[1]) {
155                 printk("warning: timer counts differ, retrying... ");
156                 r4k_ticks[2] = dosample();
157                 if (r4k_ticks[2] == r4k_ticks[0]
158                     || r4k_ticks[2] == r4k_ticks[1])
159                         r4k_tick = r4k_ticks[2];
160                 else {
161                         printk("disagreement, using average... ");
162                         r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
163                                    + r4k_ticks[2]) / 3;
164                 }
165         } else
166                 r4k_tick = r4k_ticks[0];
167 
168         printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
169                 (int) (r4k_tick / (500000 / HZ)),
170                 (int) (r4k_tick % (500000 / HZ)));
171 
172         mips_hpt_frequency = r4k_tick * HZ;
173 
174         switch (sni_brd_type) {
175         case SNI_BRD_10:
176         case SNI_BRD_10NEW:
177         case SNI_BRD_TOWER_OASIC:
178         case SNI_BRD_MINITOWER:
179                 sni_a20r_timer_setup();
180                 break;
181         }
182         setup_pit_timer();
183 }
184 
185 void read_persistent_clock(struct timespec *ts)
186 {
187         ts->tv_sec = -1;
188         ts->tv_nsec = 0;
189 }
190 

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