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Linux/arch/mips/txx9/generic/setup_tx3927.c

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  1 /*
  2  * TX3927 setup routines
  3  * Based on linux/arch/mips/txx9/jmr3927/setup.c
  4  *
  5  * Copyright 2001 MontaVista Software Inc.
  6  * Copyright (C) 2000-2001 Toshiba Corporation
  7  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
  8  *
  9  * This file is subject to the terms and conditions of the GNU General Public
 10  * License.  See the file "COPYING" in the main directory of this archive
 11  * for more details.
 12  */
 13 #include <linux/init.h>
 14 #include <linux/ioport.h>
 15 #include <linux/delay.h>
 16 #include <linux/param.h>
 17 #include <linux/io.h>
 18 #include <linux/mtd/physmap.h>
 19 #include <asm/mipsregs.h>
 20 #include <asm/txx9irq.h>
 21 #include <asm/txx9tmr.h>
 22 #include <asm/txx9pio.h>
 23 #include <asm/txx9/generic.h>
 24 #include <asm/txx9/tx3927.h>
 25 
 26 void __init tx3927_wdt_init(void)
 27 {
 28         txx9_wdt_init(TX3927_TMR_REG(2));
 29 }
 30 
 31 void __init tx3927_setup(void)
 32 {
 33         int i;
 34         unsigned int conf;
 35 
 36         txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
 37                           TX3927_REG_SIZE);
 38 
 39         /* SDRAMC,ROMC are configured by PROM */
 40         for (i = 0; i < 8; i++) {
 41                 if (!(tx3927_romcptr->cr[i] & 0x8))
 42                         continue;       /* disabled */
 43                 txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i);
 44                 txx9_ce_res[i].end =
 45                         txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1;
 46                 request_resource(&iomem_resource, &txx9_ce_res[i]);
 47         }
 48 
 49         /* clocks */
 50         txx9_gbus_clock = txx9_cpu_clock / 2;
 51         /* change default value to udelay/mdelay take reasonable time */
 52         loops_per_jiffy = txx9_cpu_clock / HZ / 2;
 53 
 54         /* CCFG */
 55         /* enable Timeout BusError */
 56         if (txx9_ccfg_toeon)
 57                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 58 
 59         /* clear BusErrorOnWrite flag */
 60         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 61         if (read_c0_conf() & TX39_CONF_WBON)
 62                 /* Disable PCI snoop */
 63                 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 64         else
 65                 /* Enable PCI SNOOP - with write through only */
 66                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 67         /* do reset on watchdog */
 68         tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
 69 
 70         printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 71                tx3927_ccfgptr->crir,
 72                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 73 
 74         /* TMR */
 75         for (i = 0; i < TX3927_NR_TMR; i++)
 76                 txx9_tmr_init(TX3927_TMR_REG(i));
 77 
 78         /* DMA */
 79         tx3927_dmaptr->mcr = 0;
 80         for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
 81                 /* reset channel */
 82                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 83                 tx3927_dmaptr->ch[i].ccr = 0;
 84         }
 85         /* enable DMA */
 86 #ifdef __BIG_ENDIAN
 87         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 88 #else
 89         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 90 #endif
 91 
 92         /* PIO */
 93         __raw_writel(0, &tx3927_pioptr->maskcpu);
 94         __raw_writel(0, &tx3927_pioptr->maskext);
 95         txx9_gpio_init(TX3927_PIO_REG, 0, 16);
 96 
 97         conf = read_c0_conf();
 98         if (conf & TX39_CONF_DCE) {
 99                 if (!(conf & TX39_CONF_WBON))
100                         pr_info("TX3927 D-Cache WriteThrough.\n");
101                 else if (!(conf & TX39_CONF_CWFON))
102                         pr_info("TX3927 D-Cache WriteBack.\n");
103                 else
104                         pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
105         }
106 }
107 
108 void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
109 {
110         txx9_clockevent_init(TX3927_TMR_REG(evt_tmrnr),
111                              TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr),
112                              TXX9_IMCLK);
113         txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK);
114 }
115 
116 void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
117 {
118         int i;
119 
120         for (i = 0; i < 2; i++)
121                 txx9_sio_init(TX3927_SIO_REG(i),
122                               TXX9_IRQ_BASE + TX3927_IR_SIO(i),
123                               i, sclk, (1 << i) & cts_mask);
124 }
125 
126 void __init tx3927_mtd_init(int ch)
127 {
128         struct physmap_flash_data pdata = {
129                 .width = TX3927_ROMC_WIDTH(ch) / 8,
130         };
131         unsigned long start = txx9_ce_res[ch].start;
132         unsigned long size = txx9_ce_res[ch].end - start + 1;
133 
134         if (!(tx3927_romcptr->cr[ch] & 0x8))
135                 return; /* disabled */
136         txx9_physmap_flash_init(ch, start, size, &pdata);
137 }
138 

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