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Linux/arch/nds32/include/asm/io.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 // Copyright (C) 2005-2017 Andes Technology Corporation
  3 
  4 #ifndef __ASM_NDS32_IO_H
  5 #define __ASM_NDS32_IO_H
  6 
  7 #include <linux/types.h>
  8 
  9 extern void iounmap(volatile void __iomem *addr);
 10 #define __raw_writeb __raw_writeb
 11 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 12 {
 13         asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
 14 }
 15 
 16 #define __raw_writew __raw_writew
 17 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 18 {
 19         asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
 20 }
 21 
 22 #define __raw_writel __raw_writel
 23 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 24 {
 25         asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
 26 }
 27 
 28 #define __raw_readb __raw_readb
 29 static inline u8 __raw_readb(const volatile void __iomem *addr)
 30 {
 31         u8 val;
 32 
 33         asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
 34         return val;
 35 }
 36 
 37 #define __raw_readw __raw_readw
 38 static inline u16 __raw_readw(const volatile void __iomem *addr)
 39 {
 40         u16 val;
 41 
 42         asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
 43         return val;
 44 }
 45 
 46 #define __raw_readl __raw_readl
 47 static inline u32 __raw_readl(const volatile void __iomem *addr)
 48 {
 49         u32 val;
 50 
 51         asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
 52         return val;
 53 }
 54 
 55 #define __iormb()               rmb()
 56 #define __iowmb()               wmb()
 57 
 58 /*
 59  * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
 60  * are not guaranteed to provide ordering against spinlocks or memory
 61  * accesses.
 62  */
 63 
 64 #define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
 65 #define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
 66 #define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
 67 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
 68 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 69 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 70 
 71 /*
 72  * {read,write}{b,w,l,q}() access little endian memory and return result in
 73  * native endianness.
 74  */
 75 #define readb(c)        ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 76 #define readw(c)        ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 77 #define readl(c)        ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 78 
 79 #define writeb(v,c)     ({ __iowmb(); writeb_relaxed((v),(c)); })
 80 #define writew(v,c)     ({ __iowmb(); writew_relaxed((v),(c)); })
 81 #define writel(v,c)     ({ __iowmb(); writel_relaxed((v),(c)); })
 82 #include <asm-generic/io.h>
 83 #endif /* __ASM_NDS32_IO_H */
 84 

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