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Linux/arch/openrisc/kernel/time.c

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  1 /*
  2  * OpenRISC time.c
  3  *
  4  * Linux architectural port borrowing liberally from similar works of
  5  * others.  All original copyrights apply as per the original source
  6  * declaration.
  7  *
  8  * Modifications for the OpenRISC architecture:
  9  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
 10  *
 11  *      This program is free software; you can redistribute it and/or
 12  *      modify it under the terms of the GNU General Public License
 13  *      as published by the Free Software Foundation; either version
 14  *      2 of the License, or (at your option) any later version.
 15  */
 16 
 17 #include <linux/kernel.h>
 18 #include <linux/time.h>
 19 #include <linux/timex.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/ftrace.h>
 22 
 23 #include <linux/clocksource.h>
 24 #include <linux/clockchips.h>
 25 #include <linux/irq.h>
 26 #include <linux/io.h>
 27 
 28 #include <asm/cpuinfo.h>
 29 
 30 /* Test the timer ticks to count, used in sync routine */
 31 inline void openrisc_timer_set(unsigned long count)
 32 {
 33         mtspr(SPR_TTCR, count);
 34 }
 35 
 36 /* Set the timer to trigger in delta cycles */
 37 inline void openrisc_timer_set_next(unsigned long delta)
 38 {
 39         u32 c;
 40 
 41         /* Read 32-bit counter value, add delta, mask off the low 28 bits.
 42          * We're guaranteed delta won't be bigger than 28 bits because the
 43          * generic timekeeping code ensures that for us.
 44          */
 45         c = mfspr(SPR_TTCR);
 46         c += delta;
 47         c &= SPR_TTMR_TP;
 48 
 49         /* Set counter and enable interrupt.
 50          * Keep timer in continuous mode always.
 51          */
 52         mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
 53 }
 54 
 55 static int openrisc_timer_set_next_event(unsigned long delta,
 56                                          struct clock_event_device *dev)
 57 {
 58         openrisc_timer_set_next(delta);
 59         return 0;
 60 }
 61 
 62 /* This is the clock event device based on the OR1K tick timer.
 63  * As the timer is being used as a continuous clock-source (required for HR
 64  * timers) we cannot enable the PERIODIC feature.  The tick timer can run using
 65  * one-shot events, so no problem.
 66  */
 67 DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer);
 68 
 69 void openrisc_clockevent_init(void)
 70 {
 71         unsigned int cpu = smp_processor_id();
 72         struct clock_event_device *evt =
 73                 &per_cpu(clockevent_openrisc_timer, cpu);
 74         struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu];
 75 
 76         mtspr(SPR_TTMR, SPR_TTMR_CR);
 77 
 78 #ifdef CONFIG_SMP
 79         evt->broadcast = tick_broadcast;
 80 #endif
 81         evt->name = "openrisc_timer_clockevent",
 82         evt->features = CLOCK_EVT_FEAT_ONESHOT,
 83         evt->rating = 300,
 84         evt->set_next_event = openrisc_timer_set_next_event,
 85 
 86         evt->cpumask = cpumask_of(cpu);
 87 
 88         /* We only have 28 bits */
 89         clockevents_config_and_register(evt, cpuinfo->clock_frequency,
 90                                         100, 0x0fffffff);
 91 
 92 }
 93 
 94 static inline void timer_ack(void)
 95 {
 96         /* Clear the IP bit and disable further interrupts */
 97         /* This can be done very simply... we just need to keep the timer
 98            running, so just maintain the CR bits while clearing the rest
 99            of the register
100          */
101         mtspr(SPR_TTMR, SPR_TTMR_CR);
102 }
103 
104 /*
105  * The timer interrupt is mostly handled in generic code nowadays... this
106  * function just acknowledges the interrupt and fires the event handler that
107  * has been set on the clockevent device by the generic time management code.
108  *
109  * This function needs to be called by the timer exception handler and that's
110  * all the exception handler needs to do.
111  */
112 
113 irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
114 {
115         struct pt_regs *old_regs = set_irq_regs(regs);
116         unsigned int cpu = smp_processor_id();
117         struct clock_event_device *evt =
118                 &per_cpu(clockevent_openrisc_timer, cpu);
119 
120         timer_ack();
121 
122         /*
123          * update_process_times() expects us to have called irq_enter().
124          */
125         irq_enter();
126         evt->event_handler(evt);
127         irq_exit();
128 
129         set_irq_regs(old_regs);
130 
131         return IRQ_HANDLED;
132 }
133 
134 /**
135  * Clocksource: Based on OpenRISC timer/counter
136  *
137  * This sets up the OpenRISC Tick Timer as a clock source.  The tick timer
138  * is 32 bits wide and runs at the CPU clock frequency.
139  */
140 static u64 openrisc_timer_read(struct clocksource *cs)
141 {
142         return (u64) mfspr(SPR_TTCR);
143 }
144 
145 static struct clocksource openrisc_timer = {
146         .name = "openrisc_timer",
147         .rating = 200,
148         .read = openrisc_timer_read,
149         .mask = CLOCKSOURCE_MASK(32),
150         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
151 };
152 
153 static int __init openrisc_timer_init(void)
154 {
155         struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
156 
157         if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
158                 panic("failed to register clocksource");
159 
160         /* Enable the incrementer: 'continuous' mode with interrupt disabled */
161         mtspr(SPR_TTMR, SPR_TTMR_CR);
162 
163         return 0;
164 }
165 
166 void __init time_init(void)
167 {
168         u32 upr;
169 
170         upr = mfspr(SPR_UPR);
171         if (!(upr & SPR_UPR_TTP))
172                 panic("Linux not supported on devices without tick timer");
173 
174         openrisc_timer_init();
175         openrisc_clockevent_init();
176 }
177 

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