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Linux/arch/powerpc/include/asm/book3s/64/mmu.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
  3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
  4 
  5 #include <asm/page.h>
  6 
  7 #ifndef __ASSEMBLY__
  8 /*
  9  * Page size definition
 10  *
 11  *    shift : is the "PAGE_SHIFT" value for that page size
 12  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 13  *            directly to a slbmte "vsid" value
 14  *    penc  : is the HPTE encoding mask for the "LP" field:
 15  *
 16  */
 17 struct mmu_psize_def {
 18         unsigned int    shift;  /* number of bits */
 19         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
 20         unsigned int    tlbiel; /* tlbiel supported for that page size */
 21         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
 22         union {
 23                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
 24                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
 25         };
 26 };
 27 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 28 #endif /* __ASSEMBLY__ */
 29 
 30 /*
 31  * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
 32  * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
 33  * page_to_nid does a page->section->node lookup
 34  * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
 35  * memory requirements with large number of sections.
 36  * 51 bits is the max physical real address on POWER9
 37  */
 38 #if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) &&  \
 39         defined(CONFIG_PPC_64K_PAGES)
 40 #define MAX_PHYSMEM_BITS 51
 41 #else
 42 #define MAX_PHYSMEM_BITS 46
 43 #endif
 44 
 45 /* 64-bit classic hash table MMU */
 46 #include <asm/book3s/64/mmu-hash.h>
 47 
 48 #ifndef __ASSEMBLY__
 49 /*
 50  * ISA 3.0 partition and process table entry format
 51  */
 52 struct prtb_entry {
 53         __be64 prtb0;
 54         __be64 prtb1;
 55 };
 56 extern struct prtb_entry *process_tb;
 57 
 58 struct patb_entry {
 59         __be64 patb0;
 60         __be64 patb1;
 61 };
 62 extern struct patb_entry *partition_tb;
 63 
 64 /* Bits in patb0 field */
 65 #define PATB_HR         (1UL << 63)
 66 #define RPDB_MASK       0x0fffffffffffff00UL
 67 #define RPDB_SHIFT      (1UL << 8)
 68 #define RTS1_SHIFT      61              /* top 2 bits of radix tree size */
 69 #define RTS1_MASK       (3UL << RTS1_SHIFT)
 70 #define RTS2_SHIFT      5               /* bottom 3 bits of radix tree size */
 71 #define RTS2_MASK       (7UL << RTS2_SHIFT)
 72 #define RPDS_MASK       0x1f            /* root page dir. size field */
 73 
 74 /* Bits in patb1 field */
 75 #define PATB_GR         (1UL << 63)     /* guest uses radix; must match HR */
 76 #define PRTS_MASK       0x1f            /* process table size field */
 77 #define PRTB_MASK       0x0ffffffffffff000UL
 78 
 79 /* Number of supported PID bits */
 80 extern unsigned int mmu_pid_bits;
 81 
 82 /* Base PID to allocate from */
 83 extern unsigned int mmu_base_pid;
 84 
 85 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
 86 #define PRTB_ENTRIES    (1ul << mmu_pid_bits)
 87 
 88 /*
 89  * Power9 currently only support 64K partition table size.
 90  */
 91 #define PATB_SIZE_SHIFT 16
 92 
 93 typedef unsigned long mm_context_id_t;
 94 struct spinlock;
 95 
 96 /* Maximum possible number of NPUs in a system. */
 97 #define NV_MAX_NPUS 8
 98 
 99 typedef struct {
100         union {
101                 /*
102                  * We use id as the PIDR content for radix. On hash we can use
103                  * more than one id. The extended ids are used when we start
104                  * having address above 512TB. We allocate one extended id
105                  * for each 512TB. The new id is then used with the 49 bit
106                  * EA to build a new VA. We always use ESID_BITS_1T_MASK bits
107                  * from EA and new context ids to build the new VAs.
108                  */
109                 mm_context_id_t id;
110                 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
111         };
112 
113         /* Number of bits in the mm_cpumask */
114         atomic_t active_cpus;
115 
116         /* Number of users of the external (Nest) MMU */
117         atomic_t copros;
118 
119         /* Number of user space windows opened in process mm_context */
120         atomic_t vas_windows;
121 
122         struct hash_mm_context *hash_context;
123 
124         unsigned long vdso_base;
125         /*
126          * pagetable fragment support
127          */
128         void *pte_frag;
129         void *pmd_frag;
130 #ifdef CONFIG_SPAPR_TCE_IOMMU
131         struct list_head iommu_group_mem_list;
132 #endif
133 
134 #ifdef CONFIG_PPC_MEM_KEYS
135         /*
136          * Each bit represents one protection key.
137          * bit set   -> key allocated
138          * bit unset -> key available for allocation
139          */
140         u32 pkey_allocation_map;
141         s16 execute_only_pkey; /* key holding execute-only protection */
142 #endif
143 } mm_context_t;
144 
145 static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
146 {
147         return ctx->hash_context->user_psize;
148 }
149 
150 static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
151 {
152         ctx->hash_context->user_psize = user_psize;
153 }
154 
155 static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
156 {
157         return ctx->hash_context->low_slices_psize;
158 }
159 
160 static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
161 {
162         return ctx->hash_context->high_slices_psize;
163 }
164 
165 static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
166 {
167         return ctx->hash_context->slb_addr_limit;
168 }
169 
170 static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)
171 {
172         ctx->hash_context->slb_addr_limit = limit;
173 }
174 
175 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
176 {
177 #ifdef CONFIG_PPC_64K_PAGES
178         if (psize == MMU_PAGE_64K)
179                 return &ctx->hash_context->mask_64k;
180 #endif
181 #ifdef CONFIG_HUGETLB_PAGE
182         if (psize == MMU_PAGE_16M)
183                 return &ctx->hash_context->mask_16m;
184         if (psize == MMU_PAGE_16G)
185                 return &ctx->hash_context->mask_16g;
186 #endif
187         BUG_ON(psize != MMU_PAGE_4K);
188 
189         return &ctx->hash_context->mask_4k;
190 }
191 
192 #ifdef CONFIG_PPC_SUBPAGE_PROT
193 static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx)
194 {
195         return ctx->hash_context->spt;
196 }
197 #endif
198 
199 /*
200  * The current system page and segment sizes
201  */
202 extern int mmu_linear_psize;
203 extern int mmu_virtual_psize;
204 extern int mmu_vmalloc_psize;
205 extern int mmu_vmemmap_psize;
206 extern int mmu_io_psize;
207 
208 /* MMU initialization */
209 void mmu_early_init_devtree(void);
210 void hash__early_init_devtree(void);
211 void radix__early_init_devtree(void);
212 extern void hash__early_init_mmu(void);
213 extern void radix__early_init_mmu(void);
214 static inline void __init early_init_mmu(void)
215 {
216         if (radix_enabled())
217                 return radix__early_init_mmu();
218         return hash__early_init_mmu();
219 }
220 extern void hash__early_init_mmu_secondary(void);
221 extern void radix__early_init_mmu_secondary(void);
222 static inline void early_init_mmu_secondary(void)
223 {
224         if (radix_enabled())
225                 return radix__early_init_mmu_secondary();
226         return hash__early_init_mmu_secondary();
227 }
228 
229 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
230                                          phys_addr_t first_memblock_size);
231 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
232                                          phys_addr_t first_memblock_size);
233 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
234                                               phys_addr_t first_memblock_size)
235 {
236         if (early_radix_enabled())
237                 return radix__setup_initial_memory_limit(first_memblock_base,
238                                                    first_memblock_size);
239         return hash__setup_initial_memory_limit(first_memblock_base,
240                                            first_memblock_size);
241 }
242 
243 #ifdef CONFIG_PPC_PSERIES
244 extern void radix_init_pseries(void);
245 #else
246 static inline void radix_init_pseries(void) { };
247 #endif
248 
249 static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
250 {
251         int index = ea >> MAX_EA_BITS_PER_CONTEXT;
252 
253         if (likely(index < ARRAY_SIZE(ctx->extended_id)))
254                 return ctx->extended_id[index];
255 
256         /* should never happen */
257         WARN_ON(1);
258         return 0;
259 }
260 
261 static inline unsigned long get_user_vsid(mm_context_t *ctx,
262                                           unsigned long ea, int ssize)
263 {
264         unsigned long context = get_user_context(ctx, ea);
265 
266         return get_vsid(context, ea, ssize);
267 }
268 
269 #endif /* __ASSEMBLY__ */
270 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
271 

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