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Linux/arch/powerpc/include/asm/cell-regs.h

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  1 /*
  2  * cbe_regs.h
  3  *
  4  * This file is intended to hold the various register definitions for CBE
  5  * on-chip system devices (memory controller, IO controller, etc...)
  6  *
  7  * (C) Copyright IBM Corporation 2001,2006
  8  *
  9  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
 10  *          David J. Erb (djerb@us.ibm.com)
 11  *
 12  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
 13  */
 14 
 15 #ifndef CBE_REGS_H
 16 #define CBE_REGS_H
 17 
 18 #include <asm/cell-pmu.h>
 19 
 20 /*
 21  *
 22  * Some HID register definitions
 23  *
 24  */
 25 
 26 /* CBE specific HID0 bits */
 27 #define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
 28 #define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
 29 #define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
 30 #define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
 31 
 32 #define MAX_CBE         2
 33 
 34 /*
 35  *
 36  * Pervasive unit register definitions
 37  *
 38  */
 39 
 40 union spe_reg {
 41         u64 val;
 42         u8 spe[8];
 43 };
 44 
 45 union ppe_spe_reg {
 46         u64 val;
 47         struct {
 48                 u32 ppe;
 49                 u32 spe;
 50         };
 51 };
 52 
 53 
 54 struct cbe_pmd_regs {
 55         /* Debug Bus Control */
 56         u64     pad_0x0000;                                     /* 0x0000 */
 57 
 58         u64     group_control;                                  /* 0x0008 */
 59 
 60         u8      pad_0x0010_0x00a8 [0x00a8 - 0x0010];            /* 0x0010 */
 61 
 62         u64     debug_bus_control;                              /* 0x00a8 */
 63 
 64         u8      pad_0x00b0_0x0100 [0x0100 - 0x00b0];            /* 0x00b0 */
 65 
 66         u64     trace_aux_data;                                 /* 0x0100 */
 67         u64     trace_buffer_0_63;                              /* 0x0108 */
 68         u64     trace_buffer_64_127;                            /* 0x0110 */
 69         u64     trace_address;                                  /* 0x0118 */
 70         u64     ext_tr_timer;                                   /* 0x0120 */
 71 
 72         u8      pad_0x0128_0x0400 [0x0400 - 0x0128];            /* 0x0128 */
 73 
 74         /* Performance Monitor */
 75         u64     pm_status;                                      /* 0x0400 */
 76         u64     pm_control;                                     /* 0x0408 */
 77         u64     pm_interval;                                    /* 0x0410 */
 78         u64     pm_ctr[4];                                      /* 0x0418 */
 79         u64     pm_start_stop;                                  /* 0x0438 */
 80         u64     pm07_control[8];                                /* 0x0440 */
 81 
 82         u8      pad_0x0480_0x0800 [0x0800 - 0x0480];            /* 0x0480 */
 83 
 84         /* Thermal Sensor Registers */
 85         union   spe_reg ts_ctsr1;                               /* 0x0800 */
 86         u64     ts_ctsr2;                                       /* 0x0808 */
 87         union   spe_reg ts_mtsr1;                               /* 0x0810 */
 88         u64     ts_mtsr2;                                       /* 0x0818 */
 89         union   spe_reg ts_itr1;                                /* 0x0820 */
 90         u64     ts_itr2;                                        /* 0x0828 */
 91         u64     ts_gitr;                                        /* 0x0830 */
 92         u64     ts_isr;                                         /* 0x0838 */
 93         u64     ts_imr;                                         /* 0x0840 */
 94         union   spe_reg tm_cr1;                                 /* 0x0848 */
 95         u64     tm_cr2;                                         /* 0x0850 */
 96         u64     tm_simr;                                        /* 0x0858 */
 97         union   ppe_spe_reg tm_tpr;                             /* 0x0860 */
 98         union   spe_reg tm_str1;                                /* 0x0868 */
 99         u64     tm_str2;                                        /* 0x0870 */
100         union   ppe_spe_reg tm_tsr;                             /* 0x0878 */
101 
102         /* Power Management */
103         u64     pmcr;                                           /* 0x0880 */
104 #define CBE_PMD_PAUSE_ZERO_CONTROL      0x10000
105         u64     pmsr;                                           /* 0x0888 */
106 
107         /* Time Base Register */
108         u64     tbr;                                            /* 0x0890 */
109 
110         u8      pad_0x0898_0x0c00 [0x0c00 - 0x0898];            /* 0x0898 */
111 
112         /* Fault Isolation Registers */
113         u64     checkstop_fir;                                  /* 0x0c00 */
114         u64     recoverable_fir;                                /* 0x0c08 */
115         u64     spec_att_mchk_fir;                              /* 0x0c10 */
116         u32     fir_mode_reg;                                   /* 0x0c18 */
117         u8      pad_0x0c1c_0x0c20 [4];                          /* 0x0c1c */
118 #define CBE_PMD_FIR_MODE_M8             0x00800
119         u64     fir_enable_mask;                                /* 0x0c20 */
120 
121         u8      pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];            /* 0x0c28 */
122         u64     ras_esc_0;                                      /* 0x0ca8 */
123         u8      pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];            /* 0x0cb0 */
124 };
125 
126 extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
127 extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
128 
129 /*
130  * PMU shadow registers
131  *
132  * Many of the registers in the performance monitoring unit are write-only,
133  * so we need to save a copy of what we write to those registers.
134  *
135  * The actual data counters are read/write. However, writing to the counters
136  * only takes effect if the PMU is enabled. Otherwise the value is stored in
137  * a hardware latch until the next time the PMU is enabled. So we save a copy
138  * of the counter values if we need to read them back while the PMU is
139  * disabled. The counter_value_in_latch field is a bitmap indicating which
140  * counters currently have a value waiting to be written.
141  */
142 
143 struct cbe_pmd_shadow_regs {
144         u32 group_control;
145         u32 debug_bus_control;
146         u32 trace_address;
147         u32 ext_tr_timer;
148         u32 pm_status;
149         u32 pm_control;
150         u32 pm_interval;
151         u32 pm_start_stop;
152         u32 pm07_control[NR_CTRS];
153 
154         u32 pm_ctr[NR_PHYS_CTRS];
155         u32 counter_value_in_latch;
156 };
157 
158 extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
159 extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
160 
161 /*
162  *
163  * IIC unit register definitions
164  *
165  */
166 
167 struct cbe_iic_pending_bits {
168         u32 data;
169         u8 flags;
170         u8 class;
171         u8 source;
172         u8 prio;
173 };
174 
175 #define CBE_IIC_IRQ_VALID       0x80
176 #define CBE_IIC_IRQ_IPI         0x40
177 
178 struct cbe_iic_thread_regs {
179         struct cbe_iic_pending_bits pending;
180         struct cbe_iic_pending_bits pending_destr;
181         u64 generate;
182         u64 prio;
183 };
184 
185 struct cbe_iic_regs {
186         u8      pad_0x0000_0x0400[0x0400 - 0x0000];             /* 0x0000 */
187 
188         /* IIC interrupt registers */
189         struct  cbe_iic_thread_regs thread[2];                  /* 0x0400 */
190 
191         u64     iic_ir;                                         /* 0x0440 */
192 #define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
193 #define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
194 #define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
195 #define CBE_IIC_IR_IOC_0        0x0
196 #define CBE_IIC_IR_IOC_1S       0xb
197 #define CBE_IIC_IR_PT_0         0xe
198 #define CBE_IIC_IR_PT_1         0xf
199 
200         u64     iic_is;                                         /* 0x0448 */
201 #define CBE_IIC_IS_PMI          0x2
202 
203         u8      pad_0x0450_0x0500[0x0500 - 0x0450];             /* 0x0450 */
204 
205         /* IOC FIR */
206         u64     ioc_fir_reset;                                  /* 0x0500 */
207         u64     ioc_fir_set;                                    /* 0x0508 */
208         u64     ioc_checkstop_enable;                           /* 0x0510 */
209         u64     ioc_fir_error_mask;                             /* 0x0518 */
210         u64     ioc_syserr_enable;                              /* 0x0520 */
211         u64     ioc_fir;                                        /* 0x0528 */
212 
213         u8      pad_0x0530_0x1000[0x1000 - 0x0530];             /* 0x0530 */
214 };
215 
216 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
217 extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
218 
219 
220 struct cbe_mic_tm_regs {
221         u8      pad_0x0000_0x0040[0x0040 - 0x0000];             /* 0x0000 */
222 
223         u64     mic_ctl_cnfg2;                                  /* 0x0040 */
224 #define CBE_MIC_ENABLE_AUX_TRC          0x8000000000000000LL
225 #define CBE_MIC_DISABLE_PWR_SAV_2       0x0200000000000000LL
226 #define CBE_MIC_DISABLE_AUX_TRC_WRAP    0x0100000000000000LL
227 #define CBE_MIC_ENABLE_AUX_TRC_INT      0x0080000000000000LL
228 
229         u64     pad_0x0048;                                     /* 0x0048 */
230 
231         u64     mic_aux_trc_base;                               /* 0x0050 */
232         u64     mic_aux_trc_max_addr;                           /* 0x0058 */
233         u64     mic_aux_trc_cur_addr;                           /* 0x0060 */
234         u64     mic_aux_trc_grf_addr;                           /* 0x0068 */
235         u64     mic_aux_trc_grf_data;                           /* 0x0070 */
236 
237         u64     pad_0x0078;                                     /* 0x0078 */
238 
239         u64     mic_ctl_cnfg_0;                                 /* 0x0080 */
240 #define CBE_MIC_DISABLE_PWR_SAV_0       0x8000000000000000LL
241 
242         u64     pad_0x0088;                                     /* 0x0088 */
243 
244         u64     slow_fast_timer_0;                              /* 0x0090 */
245         u64     slow_next_timer_0;                              /* 0x0098 */
246 
247         u8      pad_0x00a0_0x00f8[0x00f8 - 0x00a0];             /* 0x00a0 */
248         u64     mic_df_ecc_address_0;                           /* 0x00f8 */
249 
250         u8      pad_0x0100_0x01b8[0x01b8 - 0x0100];             /* 0x0100 */
251         u64     mic_df_ecc_address_1;                           /* 0x01b8 */
252 
253         u64     mic_ctl_cnfg_1;                                 /* 0x01c0 */
254 #define CBE_MIC_DISABLE_PWR_SAV_1       0x8000000000000000LL
255 
256         u64     pad_0x01c8;                                     /* 0x01c8 */
257 
258         u64     slow_fast_timer_1;                              /* 0x01d0 */
259         u64     slow_next_timer_1;                              /* 0x01d8 */
260 
261         u8      pad_0x01e0_0x0208[0x0208 - 0x01e0];             /* 0x01e0 */
262         u64     mic_exc;                                        /* 0x0208 */
263 #define CBE_MIC_EXC_BLOCK_SCRUB         0x0800000000000000ULL
264 #define CBE_MIC_EXC_FAST_SCRUB          0x0100000000000000ULL
265 
266         u64     mic_mnt_cfg;                                    /* 0x0210 */
267 #define CBE_MIC_MNT_CFG_CHAN_0_POP      0x0002000000000000ULL
268 #define CBE_MIC_MNT_CFG_CHAN_1_POP      0x0004000000000000ULL
269 
270         u64     mic_df_config;                                  /* 0x0218 */
271 #define CBE_MIC_ECC_DISABLE_0           0x4000000000000000ULL
272 #define CBE_MIC_ECC_REP_SINGLE_0        0x2000000000000000ULL
273 #define CBE_MIC_ECC_DISABLE_1           0x0080000000000000ULL
274 #define CBE_MIC_ECC_REP_SINGLE_1        0x0040000000000000ULL
275 
276         u8      pad_0x0220_0x0230[0x0230 - 0x0220];             /* 0x0220 */
277         u64     mic_fir;                                        /* 0x0230 */
278 #define CBE_MIC_FIR_ECC_SINGLE_0_ERR    0x0200000000000000ULL
279 #define CBE_MIC_FIR_ECC_MULTI_0_ERR     0x0100000000000000ULL
280 #define CBE_MIC_FIR_ECC_SINGLE_1_ERR    0x0080000000000000ULL
281 #define CBE_MIC_FIR_ECC_MULTI_1_ERR     0x0040000000000000ULL
282 #define CBE_MIC_FIR_ECC_ERR_MASK        0xffff000000000000ULL
283 #define CBE_MIC_FIR_ECC_SINGLE_0_CTE    0x0000020000000000ULL
284 #define CBE_MIC_FIR_ECC_MULTI_0_CTE     0x0000010000000000ULL
285 #define CBE_MIC_FIR_ECC_SINGLE_1_CTE    0x0000008000000000ULL
286 #define CBE_MIC_FIR_ECC_MULTI_1_CTE     0x0000004000000000ULL
287 #define CBE_MIC_FIR_ECC_CTE_MASK        0x0000ffff00000000ULL
288 #define CBE_MIC_FIR_ECC_SINGLE_0_RESET  0x0000000002000000ULL
289 #define CBE_MIC_FIR_ECC_MULTI_0_RESET   0x0000000001000000ULL
290 #define CBE_MIC_FIR_ECC_SINGLE_1_RESET  0x0000000000800000ULL
291 #define CBE_MIC_FIR_ECC_MULTI_1_RESET   0x0000000000400000ULL
292 #define CBE_MIC_FIR_ECC_RESET_MASK      0x00000000ffff0000ULL
293 #define CBE_MIC_FIR_ECC_SINGLE_0_SET    0x0000000000000200ULL
294 #define CBE_MIC_FIR_ECC_MULTI_0_SET     0x0000000000000100ULL
295 #define CBE_MIC_FIR_ECC_SINGLE_1_SET    0x0000000000000080ULL
296 #define CBE_MIC_FIR_ECC_MULTI_1_SET     0x0000000000000040ULL
297 #define CBE_MIC_FIR_ECC_SET_MASK        0x000000000000ffffULL
298         u64     mic_fir_debug;                                  /* 0x0238 */
299 
300         u8      pad_0x0240_0x1000[0x1000 - 0x0240];             /* 0x0240 */
301 };
302 
303 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
304 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
305 
306 
307 /* Cell page table entries */
308 #define CBE_IOPTE_PP_W          0x8000000000000000ul /* protection: write */
309 #define CBE_IOPTE_PP_R          0x4000000000000000ul /* protection: read */
310 #define CBE_IOPTE_M             0x2000000000000000ul /* coherency required */
311 #define CBE_IOPTE_SO_R          0x1000000000000000ul /* ordering: writes */
312 #define CBE_IOPTE_SO_RW         0x1800000000000000ul /* ordering: r & w */
313 #define CBE_IOPTE_RPN_Mask      0x07fffffffffff000ul /* RPN */
314 #define CBE_IOPTE_H             0x0000000000000800ul /* cache hint */
315 #define CBE_IOPTE_IOID_Mask     0x00000000000007fful /* ioid */
316 
317 /* some utility functions to deal with SMT */
318 extern u32 cbe_get_hw_thread_id(int cpu);
319 extern u32 cbe_cpu_to_node(int cpu);
320 extern u32 cbe_node_to_cpu(int node);
321 
322 /* Init this module early */
323 extern void cbe_regs_init(void);
324 
325 
326 #endif /* CBE_REGS_H */
327 

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