~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/cputable.h

Version: ~ [ linux-5.4-rc3 ] ~ [ linux-5.3.6 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.79 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.149 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.196 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.196 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.75 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 #ifndef __ASM_POWERPC_CPUTABLE_H
  2 #define __ASM_POWERPC_CPUTABLE_H
  3 
  4 
  5 #include <linux/types.h>
  6 #include <asm/asm-compat.h>
  7 #include <asm/feature-fixups.h>
  8 #include <uapi/asm/cputable.h>
  9 
 10 #ifndef __ASSEMBLY__
 11 
 12 /* This structure can grow, it's real size is used by head.S code
 13  * via the mkdefs mechanism.
 14  */
 15 struct cpu_spec;
 16 
 17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
 18 typedef void (*cpu_restore_t)(void);
 19 
 20 enum powerpc_oprofile_type {
 21         PPC_OPROFILE_INVALID = 0,
 22         PPC_OPROFILE_RS64 = 1,
 23         PPC_OPROFILE_POWER4 = 2,
 24         PPC_OPROFILE_G4 = 3,
 25         PPC_OPROFILE_FSL_EMB = 4,
 26         PPC_OPROFILE_CELL = 5,
 27         PPC_OPROFILE_PA6T = 6,
 28 };
 29 
 30 enum powerpc_pmc_type {
 31         PPC_PMC_DEFAULT = 0,
 32         PPC_PMC_IBM = 1,
 33         PPC_PMC_PA6T = 2,
 34         PPC_PMC_G4 = 3,
 35 };
 36 
 37 struct pt_regs;
 38 
 39 extern int machine_check_generic(struct pt_regs *regs);
 40 extern int machine_check_4xx(struct pt_regs *regs);
 41 extern int machine_check_440A(struct pt_regs *regs);
 42 extern int machine_check_e500mc(struct pt_regs *regs);
 43 extern int machine_check_e500(struct pt_regs *regs);
 44 extern int machine_check_e200(struct pt_regs *regs);
 45 extern int machine_check_47x(struct pt_regs *regs);
 46 
 47 extern void cpu_down_flush_e500v2(void);
 48 extern void cpu_down_flush_e500mc(void);
 49 extern void cpu_down_flush_e5500(void);
 50 extern void cpu_down_flush_e6500(void);
 51 
 52 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
 53 struct cpu_spec {
 54         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
 55         unsigned int    pvr_mask;
 56         unsigned int    pvr_value;
 57 
 58         char            *cpu_name;
 59         unsigned long   cpu_features;           /* Kernel features */
 60         unsigned int    cpu_user_features;      /* Userland features */
 61         unsigned int    cpu_user_features2;     /* Userland features v2 */
 62         unsigned int    mmu_features;           /* MMU features */
 63 
 64         /* cache line sizes */
 65         unsigned int    icache_bsize;
 66         unsigned int    dcache_bsize;
 67 
 68         /* flush caches inside the current cpu */
 69         void (*cpu_down_flush)(void);
 70 
 71         /* number of performance monitor counters */
 72         unsigned int    num_pmcs;
 73         enum powerpc_pmc_type pmc_type;
 74 
 75         /* this is called to initialize various CPU bits like L1 cache,
 76          * BHT, SPD, etc... from head.S before branching to identify_machine
 77          */
 78         cpu_setup_t     cpu_setup;
 79         /* Used to restore cpu setup on secondary processors and at resume */
 80         cpu_restore_t   cpu_restore;
 81 
 82         /* Used by oprofile userspace to select the right counters */
 83         char            *oprofile_cpu_type;
 84 
 85         /* Processor specific oprofile operations */
 86         enum powerpc_oprofile_type oprofile_type;
 87 
 88         /* Bit locations inside the mmcra change */
 89         unsigned long   oprofile_mmcra_sihv;
 90         unsigned long   oprofile_mmcra_sipr;
 91 
 92         /* Bits to clear during an oprofile exception */
 93         unsigned long   oprofile_mmcra_clear;
 94 
 95         /* Name of processor class, for the ELF AT_PLATFORM entry */
 96         char            *platform;
 97 
 98         /* Processor specific machine check handling. Return negative
 99          * if the error is fatal, 1 if it was fully recovered and 0 to
100          * pass up (not CPU originated) */
101         int             (*machine_check)(struct pt_regs *regs);
102 
103         /*
104          * Processor specific early machine check handler which is
105          * called in real mode to handle SLB and TLB errors.
106          */
107         long            (*machine_check_early)(struct pt_regs *regs);
108 
109         /*
110          * Processor specific routine to flush tlbs.
111          */
112         void            (*flush_tlb)(unsigned int action);
113 
114 };
115 
116 extern struct cpu_spec          *cur_cpu_spec;
117 
118 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
119 
120 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
121 extern void do_feature_fixups(unsigned long value, void *fixup_start,
122                               void *fixup_end);
123 
124 extern const char *powerpc_base_platform;
125 
126 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
127 extern void cpu_feature_keys_init(void);
128 #else
129 static inline void cpu_feature_keys_init(void) { }
130 #endif
131 
132 /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
133 enum {
134         TLB_INVAL_SCOPE_GLOBAL = 0,     /* invalidate all TLBs */
135         TLB_INVAL_SCOPE_LPID = 1,       /* invalidate TLBs for current LPID */
136 };
137 
138 #endif /* __ASSEMBLY__ */
139 
140 /* CPU kernel features */
141 
142 /* Retain the 32b definitions all use bottom half of word */
143 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x00000001)
144 #define CPU_FTR_L2CR                    ASM_CONST(0x00000002)
145 #define CPU_FTR_SPEC7450                ASM_CONST(0x00000004)
146 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x00000008)
147 #define CPU_FTR_TAU                     ASM_CONST(0x00000010)
148 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x00000020)
149 #define CPU_FTR_USE_TB                  ASM_CONST(0x00000040)
150 #define CPU_FTR_L2CSR                   ASM_CONST(0x00000080)
151 #define CPU_FTR_601                     ASM_CONST(0x00000100)
152 #define CPU_FTR_DBELL                   ASM_CONST(0x00000200)
153 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x00000400)
154 #define CPU_FTR_L3CR                    ASM_CONST(0x00000800)
155 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x00001000)
156 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x00002000)
157 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x00004000)
158 #define CPU_FTR_NO_DPM                  ASM_CONST(0x00008000)
159 #define CPU_FTR_476_DD2                 ASM_CONST(0x00010000)
160 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x00020000)
161 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x00040000)
162 #define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x00080000)
163 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x00100000)
164 #define CPU_FTR_PPC_LE                  ASM_CONST(0x00200000)
165 #define CPU_FTR_REAL_LE                 ASM_CONST(0x00400000)
166 #define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x00800000)
167 #define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x01000000)
168 #define CPU_FTR_SPE                     ASM_CONST(0x02000000)
169 #define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x04000000)
170 #define CPU_FTR_LWSYNC                  ASM_CONST(0x08000000)
171 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x10000000)
172 #define CPU_FTR_INDEXED_DCR             ASM_CONST(0x20000000)
173 #define CPU_FTR_EMB_HV                  ASM_CONST(0x40000000)
174 
175 /*
176  * Add the 64-bit processor unique features in the top half of the word;
177  * on 32-bit, make the names available but defined to be 0.
178  */
179 #ifdef __powerpc64__
180 #define LONG_ASM_CONST(x)               ASM_CONST(x)
181 #else
182 #define LONG_ASM_CONST(x)               0
183 #endif
184 
185 #define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000100000000)
186 #define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000200000000)
187 #define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000400000000)
188 #define CPU_FTR_ARCH_207S               LONG_ASM_CONST(0x0000000800000000)
189 #define CPU_FTR_ARCH_300                LONG_ASM_CONST(0x0000001000000000)
190 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000002000000000)
191 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000004000000000)
192 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000008000000000)
193 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000010000000000)
194 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000020000000000)
195 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000040000000000)
196 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0000080000000000)
197 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0000100000000000)
198 #define CPU_FTR_VSX                     LONG_ASM_CONST(0x0000200000000000)
199 #define CPU_FTR_SAO                     LONG_ASM_CONST(0x0000400000000000)
200 #define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0000800000000000)
201 #define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0001000000000000)
202 #define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0002000000000000)
203 #define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0004000000000000)
204 #define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0008000000000000)
205 #define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0010000000000000)
206 #define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x0020000000000000)
207 #define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x0040000000000000)
208 #define CPU_FTR_TM                      LONG_ASM_CONST(0x0080000000000000)
209 #define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
210 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
211 #define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
212 #define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
213 #define CPU_FTR_PMAO_BUG                LONG_ASM_CONST(0x1000000000000000)
214 #define CPU_FTR_SUBCORE                 LONG_ASM_CONST(0x2000000000000000)
215 
216 #ifndef __ASSEMBLY__
217 
218 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
219 
220 #define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
221 
222 /* We only set the altivec features if the kernel was compiled with altivec
223  * support
224  */
225 #ifdef CONFIG_ALTIVEC
226 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
227 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
228 #else
229 #define CPU_FTR_ALTIVEC_COMP    0
230 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
231 #endif
232 
233 /* We only set the VSX features if the kernel was compiled with VSX
234  * support
235  */
236 #ifdef CONFIG_VSX
237 #define CPU_FTR_VSX_COMP        CPU_FTR_VSX
238 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
239 #else
240 #define CPU_FTR_VSX_COMP        0
241 #define PPC_FEATURE_HAS_VSX_COMP    0
242 #endif
243 
244 /* We only set the spe features if the kernel was compiled with spe
245  * support
246  */
247 #ifdef CONFIG_SPE
248 #define CPU_FTR_SPE_COMP        CPU_FTR_SPE
249 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
250 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
251 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
252 #else
253 #define CPU_FTR_SPE_COMP        0
254 #define PPC_FEATURE_HAS_SPE_COMP    0
255 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
256 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
257 #endif
258 
259 /* We only set the TM feature if the kernel was compiled with TM supprt */
260 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
261 #define CPU_FTR_TM_COMP                 CPU_FTR_TM
262 #define PPC_FEATURE2_HTM_COMP           PPC_FEATURE2_HTM
263 #define PPC_FEATURE2_HTM_NOSC_COMP      PPC_FEATURE2_HTM_NOSC
264 #else
265 #define CPU_FTR_TM_COMP                 0
266 #define PPC_FEATURE2_HTM_COMP           0
267 #define PPC_FEATURE2_HTM_NOSC_COMP      0
268 #endif
269 
270 /* We need to mark all pages as being coherent if we're SMP or we have a
271  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
272  * require it for PCI "streaming/prefetch" to work properly.
273  * This is also required by 52xx family.
274  */
275 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
276         || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
277         || defined(CONFIG_PPC_MPC52xx)
278 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
279 #else
280 #define CPU_FTR_COMMON                  0
281 #endif
282 
283 /* The powersave features NAP & DOZE seems to confuse BDI when
284    debugging. So if a BDI is used, disable theses
285  */
286 #ifndef CONFIG_BDI_SWITCH
287 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
288 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
289 #else
290 #define CPU_FTR_MAYBE_CAN_DOZE  0
291 #define CPU_FTR_MAYBE_CAN_NAP   0
292 #endif
293 
294 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
295         CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
296 #define CPU_FTRS_603    (CPU_FTR_COMMON | \
297             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
298             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
299 #define CPU_FTRS_604    (CPU_FTR_COMMON | \
300             CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
301 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
302             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
303             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
304 #define CPU_FTRS_740    (CPU_FTR_COMMON | \
305             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
306             CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
307             CPU_FTR_PPC_LE)
308 #define CPU_FTRS_750    (CPU_FTR_COMMON | \
309             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
310             CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
311             CPU_FTR_PPC_LE)
312 #define CPU_FTRS_750CL  (CPU_FTRS_750)
313 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
314 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
315 #define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
316 #define CPU_FTRS_750GX  (CPU_FTRS_750FX)
317 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
318             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
319             CPU_FTR_ALTIVEC_COMP | \
320             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
321 #define CPU_FTRS_7400   (CPU_FTR_COMMON | \
322             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
323             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
324             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
325 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
326             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
327             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
328             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
330             CPU_FTR_USE_TB | \
331             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
333             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
334             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
335 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
336             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
337             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
338             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
339             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
340 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
341             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
342             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
343             CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
344 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
345             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
346             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
347             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
348             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
349             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
350 #define CPU_FTRS_7455   (CPU_FTR_COMMON | \
351             CPU_FTR_USE_TB | \
352             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
353             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
354             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
355 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
356             CPU_FTR_USE_TB | \
357             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
358             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
359             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
360             CPU_FTR_NEED_PAIRED_STWCX)
361 #define CPU_FTRS_7447   (CPU_FTR_COMMON | \
362             CPU_FTR_USE_TB | \
363             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
364             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
365             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
366 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
367             CPU_FTR_USE_TB | \
368             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
369             CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
370             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
371 #define CPU_FTRS_7448   (CPU_FTR_COMMON | \
372             CPU_FTR_USE_TB | \
373             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
374             CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
375             CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
376 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
377             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
378 #define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
379             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
380 #define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
381             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
382             CPU_FTR_COMMON)
383 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
384             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
385             CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
386 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
387 #define CPU_FTRS_8XX    (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
388 #define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
389 #define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
390 #define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
391             CPU_FTR_INDEXED_DCR)
392 #define CPU_FTRS_47X    (CPU_FTRS_440x6)
393 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
394             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
395             CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
396             CPU_FTR_DEBUG_LVL_EXC)
397 #define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
398             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
399             CPU_FTR_NOEXECUTE)
400 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
401             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
402             CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
403 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
404             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
405             CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
406 /*
407  * e5500/e6500 erratum A-006958 is a timebase bug that can use the
408  * same workaround as CPU_FTR_CELL_TB_BUG.
409  */
410 #define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
411             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
412             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
413             CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
414 #define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
415             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
416             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
417             CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
418             CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
419 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
420 
421 /* 64-bit CPUs */
422 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
423             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
424             CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
425             CPU_FTR_STCX_CHECKS_ADDRESS)
426 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
427             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
428             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
429             CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
430             CPU_FTR_HVMODE | CPU_FTR_DABRX)
431 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
432             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
433             CPU_FTR_MMCRA | CPU_FTR_SMT | \
434             CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
435             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
436 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
437             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
438             CPU_FTR_MMCRA | CPU_FTR_SMT | \
439             CPU_FTR_COHERENT_ICACHE | \
440             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
441             CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
442             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
443             CPU_FTR_DABRX)
444 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
445             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
446             CPU_FTR_MMCRA | CPU_FTR_SMT | \
447             CPU_FTR_COHERENT_ICACHE | \
448             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
449             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
450             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
451             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
452             CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
453 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
454             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
455             CPU_FTR_MMCRA | CPU_FTR_SMT | \
456             CPU_FTR_COHERENT_ICACHE | \
457             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
458             CPU_FTR_DSCR | CPU_FTR_SAO  | \
459             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
460             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
461             CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
462             CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE)
463 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
464 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
465 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
466             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
467             CPU_FTR_MMCRA | CPU_FTR_SMT | \
468             CPU_FTR_COHERENT_ICACHE | \
469             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
470             CPU_FTR_DSCR | CPU_FTR_SAO  | \
471             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
472             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
473             CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
474             CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
475 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
476             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
477             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
478             CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
479             CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
480 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
481             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
482             CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
483 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
484 
485 #ifdef __powerpc64__
486 #ifdef CONFIG_PPC_BOOK3E
487 #define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500)
488 #else
489 #define CPU_FTRS_POSSIBLE       \
490             (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
491              CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
492              CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
493              CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9)
494 #endif
495 #else
496 enum {
497         CPU_FTRS_POSSIBLE =
498 #ifdef CONFIG_PPC_BOOK3S_32
499             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
500             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
501             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
502             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
503             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
504             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
505             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
506             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
507             CPU_FTRS_CLASSIC32 |
508 #else
509             CPU_FTRS_GENERIC_32 |
510 #endif
511 #ifdef CONFIG_8xx
512             CPU_FTRS_8XX |
513 #endif
514 #ifdef CONFIG_40x
515             CPU_FTRS_40X |
516 #endif
517 #ifdef CONFIG_44x
518             CPU_FTRS_44X | CPU_FTRS_440x6 |
519 #endif
520 #ifdef CONFIG_PPC_47x
521             CPU_FTRS_47X | CPU_FTR_476_DD2 |
522 #endif
523 #ifdef CONFIG_E200
524             CPU_FTRS_E200 |
525 #endif
526 #ifdef CONFIG_E500
527             CPU_FTRS_E500 | CPU_FTRS_E500_2 |
528 #endif
529 #ifdef CONFIG_PPC_E500MC
530             CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
531 #endif
532             0,
533 };
534 #endif /* __powerpc64__ */
535 
536 #ifdef __powerpc64__
537 #ifdef CONFIG_PPC_BOOK3E
538 #define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500)
539 #else
540 #define CPU_FTRS_ALWAYS         \
541             (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
542              CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
543              CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
544              CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
545              CPU_FTRS_POWER9)
546 #endif
547 #else
548 enum {
549         CPU_FTRS_ALWAYS =
550 #ifdef CONFIG_PPC_BOOK3S_32
551             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
552             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
553             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
554             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
555             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
556             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
557             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
558             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
559             CPU_FTRS_CLASSIC32 &
560 #else
561             CPU_FTRS_GENERIC_32 &
562 #endif
563 #ifdef CONFIG_8xx
564             CPU_FTRS_8XX &
565 #endif
566 #ifdef CONFIG_40x
567             CPU_FTRS_40X &
568 #endif
569 #ifdef CONFIG_44x
570             CPU_FTRS_44X & CPU_FTRS_440x6 &
571 #endif
572 #ifdef CONFIG_E200
573             CPU_FTRS_E200 &
574 #endif
575 #ifdef CONFIG_E500
576             CPU_FTRS_E500 & CPU_FTRS_E500_2 &
577 #endif
578 #ifdef CONFIG_PPC_E500MC
579             CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
580 #endif
581             ~CPU_FTR_EMB_HV &   /* can be removed at runtime */
582             CPU_FTRS_POSSIBLE,
583 };
584 #endif /* __powerpc64__ */
585 
586 #define HBP_NUM 1
587 
588 #endif /* !__ASSEMBLY__ */
589 
590 #endif /* __ASM_POWERPC_CPUTABLE_H */
591 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp