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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/eeh.h

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  1 /*
  2  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
  3  * Copyright 2001-2012 IBM Corporation.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 18  */
 19 
 20 #ifndef _POWERPC_EEH_H
 21 #define _POWERPC_EEH_H
 22 #ifdef __KERNEL__
 23 
 24 #include <linux/init.h>
 25 #include <linux/list.h>
 26 #include <linux/string.h>
 27 #include <linux/time.h>
 28 #include <linux/atomic.h>
 29 
 30 #include <uapi/asm/eeh.h>
 31 
 32 struct pci_dev;
 33 struct pci_bus;
 34 struct pci_dn;
 35 
 36 #ifdef CONFIG_EEH
 37 
 38 /* EEH subsystem flags */
 39 #define EEH_ENABLED             0x01    /* EEH enabled                       */
 40 #define EEH_FORCE_DISABLED      0x02    /* EEH disabled                      */
 41 #define EEH_PROBE_MODE_DEV      0x04    /* From PCI device                   */
 42 #define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree                  */
 43 #define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid                     */
 44 #define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log                 */
 45 #define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately              */
 46 
 47 /*
 48  * Delay for PE reset, all in ms
 49  *
 50  * PCI specification has reset hold time of 100 milliseconds.
 51  * We have 250 milliseconds here. The PCI bus settlement time
 52  * is specified as 1.5 seconds and we have 1.8 seconds.
 53  */
 54 #define EEH_PE_RST_HOLD_TIME            250
 55 #define EEH_PE_RST_SETTLE_TIME          1800
 56 
 57 /*
 58  * The struct is used to trace PE related EEH functionality.
 59  * In theory, there will have one instance of the struct to
 60  * be created against particular PE. In nature, PEs correlate
 61  * to each other. the struct has to reflect that hierarchy in
 62  * order to easily pick up those affected PEs when one particular
 63  * PE has EEH errors.
 64  *
 65  * Also, one particular PE might be composed of PCI device, PCI
 66  * bus and its subordinate components. The struct also need ship
 67  * the information. Further more, one particular PE is only meaingful
 68  * in the corresponding PHB. Therefore, the root PEs should be created
 69  * against existing PHBs in on-to-one fashion.
 70  */
 71 #define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
 72 #define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
 73 #define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
 74 #define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
 75 #define EEH_PE_VF       (1 << 4)        /* VF PE     */
 76 
 77 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
 78 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
 79 #define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
 80 #define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
 81 
 82 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
 83 #define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
 84 #define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
 85 #define EEH_PE_PRI_BUS          (1 << 11)       /* Cached primary bus   */
 86 
 87 struct eeh_pe {
 88         int type;                       /* PE type: PHB/Bus/Device      */
 89         int state;                      /* PE EEH dependent mode        */
 90         int config_addr;                /* Traditional PCI address      */
 91         int addr;                       /* PE configuration address     */
 92         struct pci_controller *phb;     /* Associated PHB               */
 93         struct pci_bus *bus;            /* Top PCI bus for bus PE       */
 94         int check_count;                /* Times of ignored error       */
 95         int freeze_count;               /* Times of froze up            */
 96         time64_t tstamp;                /* Time on first-time freeze    */
 97         int false_positives;            /* Times of reported #ff's      */
 98         atomic_t pass_dev_cnt;          /* Count of passed through devs */
 99         struct eeh_pe *parent;          /* Parent PE                    */
100         void *data;                     /* PE auxillary data            */
101         struct list_head child_list;    /* List of PEs below this PE    */
102         struct list_head child;         /* Memb. child_list/eeh_phb_pe  */
103         struct list_head edevs;         /* List of eeh_dev in this PE   */
104 };
105 
106 #define eeh_pe_for_each_dev(pe, edev, tmp) \
107                 list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
108 
109 #define eeh_for_each_pe(root, pe) \
110         for (pe = root; pe; pe = eeh_pe_next(pe, root))
111 
112 static inline bool eeh_pe_passed(struct eeh_pe *pe)
113 {
114         return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
115 }
116 
117 /*
118  * The struct is used to trace EEH state for the associated
119  * PCI device node or PCI device. In future, it might
120  * represent PE as well so that the EEH device to form
121  * another tree except the currently existing tree of PCI
122  * buses and PCI devices
123  */
124 #define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
125 #define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
126 #define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
127 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
128 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
129 
130 #define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
131 #define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
132 #define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
133 
134 struct eeh_dev {
135         int mode;                       /* EEH mode                     */
136         int class_code;                 /* Class code of the device     */
137         int pe_config_addr;             /* PE config address            */
138         u32 config_space[16];           /* Saved PCI config space       */
139         int pcix_cap;                   /* Saved PCIx capability        */
140         int pcie_cap;                   /* Saved PCIe capability        */
141         int aer_cap;                    /* Saved AER capability         */
142         int af_cap;                     /* Saved AF capability          */
143         struct eeh_pe *pe;              /* Associated PE                */
144         struct list_head entry;         /* Membership in eeh_pe.edevs   */
145         struct list_head rmv_entry;     /* Membership in rmv_list       */
146         struct pci_dn *pdn;             /* Associated PCI device node   */
147         struct pci_dev *pdev;           /* Associated PCI device        */
148         bool in_error;                  /* Error flag for edev          */
149         struct pci_dev *physfn;         /* Associated SRIOV PF          */
150 };
151 
152 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
153 {
154         return edev ? edev->pdn : NULL;
155 }
156 
157 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
158 {
159         return edev ? edev->pdev : NULL;
160 }
161 
162 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
163 {
164         return edev ? edev->pe : NULL;
165 }
166 
167 /* Return values from eeh_ops::next_error */
168 enum {
169         EEH_NEXT_ERR_NONE = 0,
170         EEH_NEXT_ERR_INF,
171         EEH_NEXT_ERR_FROZEN_PE,
172         EEH_NEXT_ERR_FENCED_PHB,
173         EEH_NEXT_ERR_DEAD_PHB,
174         EEH_NEXT_ERR_DEAD_IOC
175 };
176 
177 /*
178  * The struct is used to trace the registered EEH operation
179  * callback functions. Actually, those operation callback
180  * functions are heavily platform dependent. That means the
181  * platform should register its own EEH operation callback
182  * functions before any EEH further operations.
183  */
184 #define EEH_OPT_DISABLE         0       /* EEH disable  */
185 #define EEH_OPT_ENABLE          1       /* EEH enable   */
186 #define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
187 #define EEH_OPT_THAW_DMA        3       /* DMA enable   */
188 #define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
189 #define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
190 #define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
191 #define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
192 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
193 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
194 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
195 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
196 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
197 #define EEH_RESET_HOT           1       /* Hot reset                    */
198 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
199 #define EEH_LOG_TEMP            1       /* EEH temporary error log      */
200 #define EEH_LOG_PERM            2       /* EEH permanent error log      */
201 
202 struct eeh_ops {
203         char *name;
204         int (*init)(void);
205         void* (*probe)(struct pci_dn *pdn, void *data);
206         int (*set_option)(struct eeh_pe *pe, int option);
207         int (*get_pe_addr)(struct eeh_pe *pe);
208         int (*get_state)(struct eeh_pe *pe, int *delay);
209         int (*reset)(struct eeh_pe *pe, int option);
210         int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
211         int (*configure_bridge)(struct eeh_pe *pe);
212         int (*err_inject)(struct eeh_pe *pe, int type, int func,
213                           unsigned long addr, unsigned long mask);
214         int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
215         int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
216         int (*next_error)(struct eeh_pe **pe);
217         int (*restore_config)(struct pci_dn *pdn);
218         int (*notify_resume)(struct pci_dn *pdn);
219 };
220 
221 extern int eeh_subsystem_flags;
222 extern int eeh_max_freezes;
223 extern struct eeh_ops *eeh_ops;
224 extern raw_spinlock_t confirm_error_lock;
225 
226 static inline void eeh_add_flag(int flag)
227 {
228         eeh_subsystem_flags |= flag;
229 }
230 
231 static inline void eeh_clear_flag(int flag)
232 {
233         eeh_subsystem_flags &= ~flag;
234 }
235 
236 static inline bool eeh_has_flag(int flag)
237 {
238         return !!(eeh_subsystem_flags & flag);
239 }
240 
241 static inline bool eeh_enabled(void)
242 {
243         return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
244 }
245 
246 static inline void eeh_serialize_lock(unsigned long *flags)
247 {
248         raw_spin_lock_irqsave(&confirm_error_lock, *flags);
249 }
250 
251 static inline void eeh_serialize_unlock(unsigned long flags)
252 {
253         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
254 }
255 
256 static inline bool eeh_state_active(int state)
257 {
258         return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
259         == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
260 }
261 
262 typedef void *(*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
263 typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
264 void eeh_set_pe_aux_size(int size);
265 int eeh_phb_pe_create(struct pci_controller *phb);
266 int eeh_wait_state(struct eeh_pe *pe, int max_wait);
267 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
268 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
269 struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
270                           int pe_no, int config_addr);
271 int eeh_add_to_parent_pe(struct eeh_dev *edev);
272 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
273 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
274 void *eeh_pe_traverse(struct eeh_pe *root,
275                       eeh_pe_traverse_func fn, void *flag);
276 void *eeh_pe_dev_traverse(struct eeh_pe *root,
277                           eeh_edev_traverse_func fn, void *flag);
278 void eeh_pe_restore_bars(struct eeh_pe *pe);
279 const char *eeh_pe_loc_get(struct eeh_pe *pe);
280 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
281 
282 struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
283 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
284 void eeh_probe_devices(void);
285 int __init eeh_ops_register(struct eeh_ops *ops);
286 int __exit eeh_ops_unregister(const char *name);
287 int eeh_check_failure(const volatile void __iomem *token);
288 int eeh_dev_check_failure(struct eeh_dev *edev);
289 void eeh_addr_cache_build(void);
290 void eeh_add_device_early(struct pci_dn *);
291 void eeh_add_device_tree_early(struct pci_dn *);
292 void eeh_add_device_late(struct pci_dev *);
293 void eeh_add_device_tree_late(struct pci_bus *);
294 void eeh_add_sysfs_files(struct pci_bus *);
295 void eeh_remove_device(struct pci_dev *);
296 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
297 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
298 int eeh_dev_open(struct pci_dev *pdev);
299 void eeh_dev_release(struct pci_dev *pdev);
300 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
301 int eeh_pe_set_option(struct eeh_pe *pe, int option);
302 int eeh_pe_get_state(struct eeh_pe *pe);
303 int eeh_pe_reset(struct eeh_pe *pe, int option);
304 int eeh_pe_configure(struct eeh_pe *pe);
305 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
306                       unsigned long addr, unsigned long mask);
307 int eeh_restore_vf_config(struct pci_dn *pdn);
308 
309 /**
310  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
311  *
312  * If this macro yields TRUE, the caller relays to eeh_check_failure()
313  * which does further tests out of line.
314  */
315 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
316 
317 /*
318  * Reads from a device which has been isolated by EEH will return
319  * all 1s.  This macro gives an all-1s value of the given size (in
320  * bytes: 1, 2, or 4) for comparing with the result of a read.
321  */
322 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
323 
324 #else /* !CONFIG_EEH */
325 
326 static inline bool eeh_enabled(void)
327 {
328         return false;
329 }
330 
331 static inline void eeh_probe_devices(void) { }
332 
333 static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
334 {
335         return NULL;
336 }
337 
338 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
339 
340 static inline int eeh_check_failure(const volatile void __iomem *token)
341 {
342         return 0;
343 }
344 
345 #define eeh_dev_check_failure(x) (0)
346 
347 static inline void eeh_addr_cache_build(void) { }
348 
349 static inline void eeh_add_device_early(struct pci_dn *pdn) { }
350 
351 static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
352 
353 static inline void eeh_add_device_late(struct pci_dev *dev) { }
354 
355 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
356 
357 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
358 
359 static inline void eeh_remove_device(struct pci_dev *dev) { }
360 
361 #define EEH_POSSIBLE_ERROR(val, type) (0)
362 #define EEH_IO_ERROR_VALUE(size) (-1UL)
363 #endif /* CONFIG_EEH */
364 
365 #ifdef CONFIG_PPC64
366 /*
367  * MMIO read/write operations with EEH support.
368  */
369 static inline u8 eeh_readb(const volatile void __iomem *addr)
370 {
371         u8 val = in_8(addr);
372         if (EEH_POSSIBLE_ERROR(val, u8))
373                 eeh_check_failure(addr);
374         return val;
375 }
376 
377 static inline u16 eeh_readw(const volatile void __iomem *addr)
378 {
379         u16 val = in_le16(addr);
380         if (EEH_POSSIBLE_ERROR(val, u16))
381                 eeh_check_failure(addr);
382         return val;
383 }
384 
385 static inline u32 eeh_readl(const volatile void __iomem *addr)
386 {
387         u32 val = in_le32(addr);
388         if (EEH_POSSIBLE_ERROR(val, u32))
389                 eeh_check_failure(addr);
390         return val;
391 }
392 
393 static inline u64 eeh_readq(const volatile void __iomem *addr)
394 {
395         u64 val = in_le64(addr);
396         if (EEH_POSSIBLE_ERROR(val, u64))
397                 eeh_check_failure(addr);
398         return val;
399 }
400 
401 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
402 {
403         u16 val = in_be16(addr);
404         if (EEH_POSSIBLE_ERROR(val, u16))
405                 eeh_check_failure(addr);
406         return val;
407 }
408 
409 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
410 {
411         u32 val = in_be32(addr);
412         if (EEH_POSSIBLE_ERROR(val, u32))
413                 eeh_check_failure(addr);
414         return val;
415 }
416 
417 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
418 {
419         u64 val = in_be64(addr);
420         if (EEH_POSSIBLE_ERROR(val, u64))
421                 eeh_check_failure(addr);
422         return val;
423 }
424 
425 static inline void eeh_memcpy_fromio(void *dest, const
426                                      volatile void __iomem *src,
427                                      unsigned long n)
428 {
429         _memcpy_fromio(dest, src, n);
430 
431         /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
432          * were copied. Check all four bytes.
433          */
434         if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
435                 eeh_check_failure(src);
436 }
437 
438 /* in-string eeh macros */
439 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
440                               int ns)
441 {
442         _insb(addr, buf, ns);
443         if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
444                 eeh_check_failure(addr);
445 }
446 
447 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
448                               int ns)
449 {
450         _insw(addr, buf, ns);
451         if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
452                 eeh_check_failure(addr);
453 }
454 
455 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
456                               int nl)
457 {
458         _insl(addr, buf, nl);
459         if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
460                 eeh_check_failure(addr);
461 }
462 
463 #endif /* CONFIG_PPC64 */
464 #endif /* __KERNEL__ */
465 #endif /* _POWERPC_EEH_H */
466 

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