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Linux/arch/powerpc/include/asm/eeh.h

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  1 /*
  2  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
  3  * Copyright 2001-2012 IBM Corporation.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 18  */
 19 
 20 #ifndef _POWERPC_EEH_H
 21 #define _POWERPC_EEH_H
 22 #ifdef __KERNEL__
 23 
 24 #include <linux/init.h>
 25 #include <linux/list.h>
 26 #include <linux/string.h>
 27 #include <linux/time.h>
 28 
 29 struct pci_dev;
 30 struct pci_bus;
 31 struct device_node;
 32 
 33 #ifdef CONFIG_EEH
 34 
 35 /*
 36  * The struct is used to trace PE related EEH functionality.
 37  * In theory, there will have one instance of the struct to
 38  * be created against particular PE. In nature, PEs corelate
 39  * to each other. the struct has to reflect that hierarchy in
 40  * order to easily pick up those affected PEs when one particular
 41  * PE has EEH errors.
 42  *
 43  * Also, one particular PE might be composed of PCI device, PCI
 44  * bus and its subordinate components. The struct also need ship
 45  * the information. Further more, one particular PE is only meaingful
 46  * in the corresponding PHB. Therefore, the root PEs should be created
 47  * against existing PHBs in on-to-one fashion.
 48  */
 49 #define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
 50 #define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
 51 #define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
 52 #define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
 53 
 54 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
 55 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
 56 #define EEH_PE_PHB_DEAD         (1 << 2)        /* Dead PHB             */
 57 
 58 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
 59 
 60 struct eeh_pe {
 61         int type;                       /* PE type: PHB/Bus/Device      */
 62         int state;                      /* PE EEH dependent mode        */
 63         int config_addr;                /* Traditional PCI address      */
 64         int addr;                       /* PE configuration address     */
 65         struct pci_controller *phb;     /* Associated PHB               */
 66         struct pci_bus *bus;            /* Top PCI bus for bus PE       */
 67         int check_count;                /* Times of ignored error       */
 68         int freeze_count;               /* Times of froze up            */
 69         struct timeval tstamp;          /* Time on first-time freeze    */
 70         int false_positives;            /* Times of reported #ff's      */
 71         struct eeh_pe *parent;          /* Parent PE                    */
 72         struct list_head child_list;    /* Link PE to the child list    */
 73         struct list_head edevs;         /* Link list of EEH devices     */
 74         struct list_head child;         /* Child PEs                    */
 75 };
 76 
 77 #define eeh_pe_for_each_dev(pe, edev, tmp) \
 78                 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
 79 
 80 /*
 81  * The struct is used to trace EEH state for the associated
 82  * PCI device node or PCI device. In future, it might
 83  * represent PE as well so that the EEH device to form
 84  * another tree except the currently existing tree of PCI
 85  * buses and PCI devices
 86  */
 87 #define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 88 #define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 89 #define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 90 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 91 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 92 
 93 #define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 94 #define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 95 
 96 struct eeh_dev {
 97         int mode;                       /* EEH mode                     */
 98         int class_code;                 /* Class code of the device     */
 99         int config_addr;                /* Config address               */
100         int pe_config_addr;             /* PE config address            */
101         u32 config_space[16];           /* Saved PCI config space       */
102         u8 pcie_cap;                    /* Saved PCIe capability        */
103         struct eeh_pe *pe;              /* Associated PE                */
104         struct list_head list;          /* Form link list in the PE     */
105         struct pci_controller *phb;     /* Associated PHB               */
106         struct device_node *dn;         /* Associated device node       */
107         struct pci_dev *pdev;           /* Associated PCI device        */
108         struct pci_bus *bus;            /* PCI bus for partial hotplug  */
109 };
110 
111 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
112 {
113         return edev ? edev->dn : NULL;
114 }
115 
116 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
117 {
118         return edev ? edev->pdev : NULL;
119 }
120 
121 /* Return values from eeh_ops::next_error */
122 enum {
123         EEH_NEXT_ERR_NONE = 0,
124         EEH_NEXT_ERR_INF,
125         EEH_NEXT_ERR_FROZEN_PE,
126         EEH_NEXT_ERR_FENCED_PHB,
127         EEH_NEXT_ERR_DEAD_PHB,
128         EEH_NEXT_ERR_DEAD_IOC
129 };
130 
131 /*
132  * The struct is used to trace the registered EEH operation
133  * callback functions. Actually, those operation callback
134  * functions are heavily platform dependent. That means the
135  * platform should register its own EEH operation callback
136  * functions before any EEH further operations.
137  */
138 #define EEH_OPT_DISABLE         0       /* EEH disable  */
139 #define EEH_OPT_ENABLE          1       /* EEH enable   */
140 #define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
141 #define EEH_OPT_THAW_DMA        3       /* DMA enable   */
142 #define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
143 #define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
144 #define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
145 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
146 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
147 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
148 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
149 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
150 #define EEH_RESET_HOT           1       /* Hot reset                    */
151 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
152 #define EEH_LOG_TEMP            1       /* EEH temporary error log      */
153 #define EEH_LOG_PERM            2       /* EEH permanent error log      */
154 
155 struct eeh_ops {
156         char *name;
157         int (*init)(void);
158         int (*post_init)(void);
159         void* (*of_probe)(struct device_node *dn, void *flag);
160         int (*dev_probe)(struct pci_dev *dev, void *flag);
161         int (*set_option)(struct eeh_pe *pe, int option);
162         int (*get_pe_addr)(struct eeh_pe *pe);
163         int (*get_state)(struct eeh_pe *pe, int *state);
164         int (*reset)(struct eeh_pe *pe, int option);
165         int (*wait_state)(struct eeh_pe *pe, int max_wait);
166         int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
167         int (*configure_bridge)(struct eeh_pe *pe);
168         int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
169         int (*write_config)(struct device_node *dn, int where, int size, u32 val);
170         int (*next_error)(struct eeh_pe **pe);
171         int (*restore_config)(struct device_node *dn);
172 };
173 
174 extern struct eeh_ops *eeh_ops;
175 extern bool eeh_subsystem_enabled;
176 extern raw_spinlock_t confirm_error_lock;
177 extern int eeh_probe_mode;
178 
179 static inline bool eeh_enabled(void)
180 {
181         return eeh_subsystem_enabled;
182 }
183 
184 static inline void eeh_set_enable(bool mode)
185 {
186         eeh_subsystem_enabled = mode;
187 }
188 
189 #define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
190 #define EEH_PROBE_MODE_DEVTREE  (1<<1)  /* From device tree     */
191 
192 static inline void eeh_probe_mode_set(int flag)
193 {
194         eeh_probe_mode = flag;
195 }
196 
197 static inline int eeh_probe_mode_devtree(void)
198 {
199         return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
200 }
201 
202 static inline int eeh_probe_mode_dev(void)
203 {
204         return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
205 }
206 
207 static inline void eeh_serialize_lock(unsigned long *flags)
208 {
209         raw_spin_lock_irqsave(&confirm_error_lock, *flags);
210 }
211 
212 static inline void eeh_serialize_unlock(unsigned long flags)
213 {
214         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
215 }
216 
217 /*
218  * Max number of EEH freezes allowed before we consider the device
219  * to be permanently disabled.
220  */
221 #define EEH_MAX_ALLOWED_FREEZES 5
222 
223 typedef void *(*eeh_traverse_func)(void *data, void *flag);
224 int eeh_phb_pe_create(struct pci_controller *phb);
225 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
226 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
227 int eeh_add_to_parent_pe(struct eeh_dev *edev);
228 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
229 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
230 void *eeh_pe_traverse(struct eeh_pe *root,
231                 eeh_traverse_func fn, void *flag);
232 void *eeh_pe_dev_traverse(struct eeh_pe *root,
233                 eeh_traverse_func fn, void *flag);
234 void eeh_pe_restore_bars(struct eeh_pe *pe);
235 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
236 
237 void *eeh_dev_init(struct device_node *dn, void *data);
238 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
239 int eeh_init(void);
240 int __init eeh_ops_register(struct eeh_ops *ops);
241 int __exit eeh_ops_unregister(const char *name);
242 unsigned long eeh_check_failure(const volatile void __iomem *token,
243                                 unsigned long val);
244 int eeh_dev_check_failure(struct eeh_dev *edev);
245 void eeh_addr_cache_build(void);
246 void eeh_add_device_early(struct device_node *);
247 void eeh_add_device_tree_early(struct device_node *);
248 void eeh_add_device_late(struct pci_dev *);
249 void eeh_add_device_tree_late(struct pci_bus *);
250 void eeh_add_sysfs_files(struct pci_bus *);
251 void eeh_remove_device(struct pci_dev *);
252 
253 /**
254  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
255  *
256  * If this macro yields TRUE, the caller relays to eeh_check_failure()
257  * which does further tests out of line.
258  */
259 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
260 
261 /*
262  * Reads from a device which has been isolated by EEH will return
263  * all 1s.  This macro gives an all-1s value of the given size (in
264  * bytes: 1, 2, or 4) for comparing with the result of a read.
265  */
266 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
267 
268 #else /* !CONFIG_EEH */
269 
270 static inline bool eeh_enabled(void)
271 {
272         return false;
273 }
274 
275 static inline void eeh_set_enable(bool mode) { }
276 
277 static inline int eeh_init(void)
278 {
279         return 0;
280 }
281 
282 static inline void *eeh_dev_init(struct device_node *dn, void *data)
283 {
284         return NULL;
285 }
286 
287 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
288 
289 static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
290 {
291         return val;
292 }
293 
294 #define eeh_dev_check_failure(x) (0)
295 
296 static inline void eeh_addr_cache_build(void) { }
297 
298 static inline void eeh_add_device_early(struct device_node *dn) { }
299 
300 static inline void eeh_add_device_tree_early(struct device_node *dn) { }
301 
302 static inline void eeh_add_device_late(struct pci_dev *dev) { }
303 
304 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
305 
306 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
307 
308 static inline void eeh_remove_device(struct pci_dev *dev) { }
309 
310 #define EEH_POSSIBLE_ERROR(val, type) (0)
311 #define EEH_IO_ERROR_VALUE(size) (-1UL)
312 #endif /* CONFIG_EEH */
313 
314 #ifdef CONFIG_PPC64
315 /*
316  * MMIO read/write operations with EEH support.
317  */
318 static inline u8 eeh_readb(const volatile void __iomem *addr)
319 {
320         u8 val = in_8(addr);
321         if (EEH_POSSIBLE_ERROR(val, u8))
322                 return eeh_check_failure(addr, val);
323         return val;
324 }
325 
326 static inline u16 eeh_readw(const volatile void __iomem *addr)
327 {
328         u16 val = in_le16(addr);
329         if (EEH_POSSIBLE_ERROR(val, u16))
330                 return eeh_check_failure(addr, val);
331         return val;
332 }
333 
334 static inline u32 eeh_readl(const volatile void __iomem *addr)
335 {
336         u32 val = in_le32(addr);
337         if (EEH_POSSIBLE_ERROR(val, u32))
338                 return eeh_check_failure(addr, val);
339         return val;
340 }
341 
342 static inline u64 eeh_readq(const volatile void __iomem *addr)
343 {
344         u64 val = in_le64(addr);
345         if (EEH_POSSIBLE_ERROR(val, u64))
346                 return eeh_check_failure(addr, val);
347         return val;
348 }
349 
350 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
351 {
352         u16 val = in_be16(addr);
353         if (EEH_POSSIBLE_ERROR(val, u16))
354                 return eeh_check_failure(addr, val);
355         return val;
356 }
357 
358 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
359 {
360         u32 val = in_be32(addr);
361         if (EEH_POSSIBLE_ERROR(val, u32))
362                 return eeh_check_failure(addr, val);
363         return val;
364 }
365 
366 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
367 {
368         u64 val = in_be64(addr);
369         if (EEH_POSSIBLE_ERROR(val, u64))
370                 return eeh_check_failure(addr, val);
371         return val;
372 }
373 
374 static inline void eeh_memcpy_fromio(void *dest, const
375                                      volatile void __iomem *src,
376                                      unsigned long n)
377 {
378         _memcpy_fromio(dest, src, n);
379 
380         /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
381          * were copied. Check all four bytes.
382          */
383         if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
384                 eeh_check_failure(src, *((u32 *)(dest + n - 4)));
385 }
386 
387 /* in-string eeh macros */
388 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
389                               int ns)
390 {
391         _insb(addr, buf, ns);
392         if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
393                 eeh_check_failure(addr, *(u8*)buf);
394 }
395 
396 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
397                               int ns)
398 {
399         _insw(addr, buf, ns);
400         if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
401                 eeh_check_failure(addr, *(u16*)buf);
402 }
403 
404 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
405                               int nl)
406 {
407         _insl(addr, buf, nl);
408         if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
409                 eeh_check_failure(addr, *(u32*)buf);
410 }
411 
412 #endif /* CONFIG_PPC64 */
413 #endif /* __KERNEL__ */
414 #endif /* _POWERPC_EEH_H */
415 

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