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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/eeh.h

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  1 /*
  2  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
  3  * Copyright 2001-2012 IBM Corporation.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License as published by
  7  * the Free Software Foundation; either version 2 of the License, or
  8  * (at your option) any later version.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program; if not, write to the Free Software
 17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 18  */
 19 
 20 #ifndef _POWERPC_EEH_H
 21 #define _POWERPC_EEH_H
 22 #ifdef __KERNEL__
 23 
 24 #include <linux/init.h>
 25 #include <linux/list.h>
 26 #include <linux/string.h>
 27 #include <linux/time.h>
 28 #include <linux/atomic.h>
 29 
 30 #include <uapi/asm/eeh.h>
 31 
 32 struct pci_dev;
 33 struct pci_bus;
 34 struct pci_dn;
 35 
 36 #ifdef CONFIG_EEH
 37 
 38 /* EEH subsystem flags */
 39 #define EEH_ENABLED             0x01    /* EEH enabled          */
 40 #define EEH_FORCE_DISABLED      0x02    /* EEH disabled         */
 41 #define EEH_PROBE_MODE_DEV      0x04    /* From PCI device      */
 42 #define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree     */
 43 #define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid        */
 44 #define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log    */
 45 #define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately */
 46 
 47 /*
 48  * Delay for PE reset, all in ms
 49  *
 50  * PCI specification has reset hold time of 100 milliseconds.
 51  * We have 250 milliseconds here. The PCI bus settlement time
 52  * is specified as 1.5 seconds and we have 1.8 seconds.
 53  */
 54 #define EEH_PE_RST_HOLD_TIME            250
 55 #define EEH_PE_RST_SETTLE_TIME          1800
 56 
 57 /*
 58  * The struct is used to trace PE related EEH functionality.
 59  * In theory, there will have one instance of the struct to
 60  * be created against particular PE. In nature, PEs corelate
 61  * to each other. the struct has to reflect that hierarchy in
 62  * order to easily pick up those affected PEs when one particular
 63  * PE has EEH errors.
 64  *
 65  * Also, one particular PE might be composed of PCI device, PCI
 66  * bus and its subordinate components. The struct also need ship
 67  * the information. Further more, one particular PE is only meaingful
 68  * in the corresponding PHB. Therefore, the root PEs should be created
 69  * against existing PHBs in on-to-one fashion.
 70  */
 71 #define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
 72 #define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
 73 #define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
 74 #define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
 75 
 76 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
 77 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
 78 #define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
 79 #define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
 80 
 81 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
 82 #define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
 83 #define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
 84 
 85 struct eeh_pe {
 86         int type;                       /* PE type: PHB/Bus/Device      */
 87         int state;                      /* PE EEH dependent mode        */
 88         int config_addr;                /* Traditional PCI address      */
 89         int addr;                       /* PE configuration address     */
 90         struct pci_controller *phb;     /* Associated PHB               */
 91         struct pci_bus *bus;            /* Top PCI bus for bus PE       */
 92         int check_count;                /* Times of ignored error       */
 93         int freeze_count;               /* Times of froze up            */
 94         struct timeval tstamp;          /* Time on first-time freeze    */
 95         int false_positives;            /* Times of reported #ff's      */
 96         atomic_t pass_dev_cnt;          /* Count of passed through devs */
 97         struct eeh_pe *parent;          /* Parent PE                    */
 98         void *data;                     /* PE auxillary data            */
 99         struct list_head child_list;    /* Link PE to the child list    */
100         struct list_head edevs;         /* Link list of EEH devices     */
101         struct list_head child;         /* Child PEs                    */
102 };
103 
104 #define eeh_pe_for_each_dev(pe, edev, tmp) \
105                 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
106 
107 static inline bool eeh_pe_passed(struct eeh_pe *pe)
108 {
109         return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
110 }
111 
112 /*
113  * The struct is used to trace EEH state for the associated
114  * PCI device node or PCI device. In future, it might
115  * represent PE as well so that the EEH device to form
116  * another tree except the currently existing tree of PCI
117  * buses and PCI devices
118  */
119 #define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
120 #define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
121 #define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
122 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
123 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
124 
125 #define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
126 #define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
127 #define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
128 
129 struct eeh_dev {
130         int mode;                       /* EEH mode                     */
131         int class_code;                 /* Class code of the device     */
132         int config_addr;                /* Config address               */
133         int pe_config_addr;             /* PE config address            */
134         u32 config_space[16];           /* Saved PCI config space       */
135         int pcix_cap;                   /* Saved PCIx capability        */
136         int pcie_cap;                   /* Saved PCIe capability        */
137         int aer_cap;                    /* Saved AER capability         */
138         struct eeh_pe *pe;              /* Associated PE                */
139         struct list_head list;          /* Form link list in the PE     */
140         struct pci_controller *phb;     /* Associated PHB               */
141         struct pci_dn *pdn;             /* Associated PCI device node   */
142         struct pci_dev *pdev;           /* Associated PCI device        */
143         struct pci_bus *bus;            /* PCI bus for partial hotplug  */
144 };
145 
146 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
147 {
148         return edev ? edev->pdn : NULL;
149 }
150 
151 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
152 {
153         return edev ? edev->pdev : NULL;
154 }
155 
156 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
157 {
158         return edev ? edev->pe : NULL;
159 }
160 
161 /* Return values from eeh_ops::next_error */
162 enum {
163         EEH_NEXT_ERR_NONE = 0,
164         EEH_NEXT_ERR_INF,
165         EEH_NEXT_ERR_FROZEN_PE,
166         EEH_NEXT_ERR_FENCED_PHB,
167         EEH_NEXT_ERR_DEAD_PHB,
168         EEH_NEXT_ERR_DEAD_IOC
169 };
170 
171 /*
172  * The struct is used to trace the registered EEH operation
173  * callback functions. Actually, those operation callback
174  * functions are heavily platform dependent. That means the
175  * platform should register its own EEH operation callback
176  * functions before any EEH further operations.
177  */
178 #define EEH_OPT_DISABLE         0       /* EEH disable  */
179 #define EEH_OPT_ENABLE          1       /* EEH enable   */
180 #define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
181 #define EEH_OPT_THAW_DMA        3       /* DMA enable   */
182 #define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
183 #define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
184 #define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
185 #define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
186 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
187 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
188 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
189 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
190 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
191 #define EEH_RESET_HOT           1       /* Hot reset                    */
192 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
193 #define EEH_LOG_TEMP            1       /* EEH temporary error log      */
194 #define EEH_LOG_PERM            2       /* EEH permanent error log      */
195 
196 struct eeh_ops {
197         char *name;
198         int (*init)(void);
199         int (*post_init)(void);
200         void* (*probe)(struct pci_dn *pdn, void *data);
201         int (*set_option)(struct eeh_pe *pe, int option);
202         int (*get_pe_addr)(struct eeh_pe *pe);
203         int (*get_state)(struct eeh_pe *pe, int *state);
204         int (*reset)(struct eeh_pe *pe, int option);
205         int (*wait_state)(struct eeh_pe *pe, int max_wait);
206         int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
207         int (*configure_bridge)(struct eeh_pe *pe);
208         int (*err_inject)(struct eeh_pe *pe, int type, int func,
209                           unsigned long addr, unsigned long mask);
210         int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
211         int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
212         int (*next_error)(struct eeh_pe **pe);
213         int (*restore_config)(struct pci_dn *pdn);
214 };
215 
216 extern int eeh_subsystem_flags;
217 extern int eeh_max_freezes;
218 extern struct eeh_ops *eeh_ops;
219 extern raw_spinlock_t confirm_error_lock;
220 
221 static inline void eeh_add_flag(int flag)
222 {
223         eeh_subsystem_flags |= flag;
224 }
225 
226 static inline void eeh_clear_flag(int flag)
227 {
228         eeh_subsystem_flags &= ~flag;
229 }
230 
231 static inline bool eeh_has_flag(int flag)
232 {
233         return !!(eeh_subsystem_flags & flag);
234 }
235 
236 static inline bool eeh_enabled(void)
237 {
238         if (eeh_has_flag(EEH_FORCE_DISABLED) ||
239             !eeh_has_flag(EEH_ENABLED))
240                 return false;
241 
242         return true;
243 }
244 
245 static inline void eeh_serialize_lock(unsigned long *flags)
246 {
247         raw_spin_lock_irqsave(&confirm_error_lock, *flags);
248 }
249 
250 static inline void eeh_serialize_unlock(unsigned long flags)
251 {
252         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
253 }
254 
255 typedef void *(*eeh_traverse_func)(void *data, void *flag);
256 void eeh_set_pe_aux_size(int size);
257 int eeh_phb_pe_create(struct pci_controller *phb);
258 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
259 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
260 int eeh_add_to_parent_pe(struct eeh_dev *edev);
261 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
262 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
263 void *eeh_pe_traverse(struct eeh_pe *root,
264                 eeh_traverse_func fn, void *flag);
265 void *eeh_pe_dev_traverse(struct eeh_pe *root,
266                 eeh_traverse_func fn, void *flag);
267 void eeh_pe_restore_bars(struct eeh_pe *pe);
268 const char *eeh_pe_loc_get(struct eeh_pe *pe);
269 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
270 
271 void *eeh_dev_init(struct pci_dn *pdn, void *data);
272 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
273 int eeh_init(void);
274 int __init eeh_ops_register(struct eeh_ops *ops);
275 int __exit eeh_ops_unregister(const char *name);
276 int eeh_check_failure(const volatile void __iomem *token);
277 int eeh_dev_check_failure(struct eeh_dev *edev);
278 void eeh_addr_cache_build(void);
279 void eeh_add_device_early(struct pci_dn *);
280 void eeh_add_device_tree_early(struct pci_dn *);
281 void eeh_add_device_late(struct pci_dev *);
282 void eeh_add_device_tree_late(struct pci_bus *);
283 void eeh_add_sysfs_files(struct pci_bus *);
284 void eeh_remove_device(struct pci_dev *);
285 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
286 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
287 int eeh_dev_open(struct pci_dev *pdev);
288 void eeh_dev_release(struct pci_dev *pdev);
289 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
290 int eeh_pe_set_option(struct eeh_pe *pe, int option);
291 int eeh_pe_get_state(struct eeh_pe *pe);
292 int eeh_pe_reset(struct eeh_pe *pe, int option);
293 int eeh_pe_configure(struct eeh_pe *pe);
294 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
295                       unsigned long addr, unsigned long mask);
296 
297 /**
298  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
299  *
300  * If this macro yields TRUE, the caller relays to eeh_check_failure()
301  * which does further tests out of line.
302  */
303 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
304 
305 /*
306  * Reads from a device which has been isolated by EEH will return
307  * all 1s.  This macro gives an all-1s value of the given size (in
308  * bytes: 1, 2, or 4) for comparing with the result of a read.
309  */
310 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
311 
312 #else /* !CONFIG_EEH */
313 
314 static inline bool eeh_enabled(void)
315 {
316         return false;
317 }
318 
319 static inline int eeh_init(void)
320 {
321         return 0;
322 }
323 
324 static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
325 {
326         return NULL;
327 }
328 
329 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
330 
331 static inline int eeh_check_failure(const volatile void __iomem *token)
332 {
333         return 0;
334 }
335 
336 #define eeh_dev_check_failure(x) (0)
337 
338 static inline void eeh_addr_cache_build(void) { }
339 
340 static inline void eeh_add_device_early(struct pci_dn *pdn) { }
341 
342 static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
343 
344 static inline void eeh_add_device_late(struct pci_dev *dev) { }
345 
346 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
347 
348 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
349 
350 static inline void eeh_remove_device(struct pci_dev *dev) { }
351 
352 #define EEH_POSSIBLE_ERROR(val, type) (0)
353 #define EEH_IO_ERROR_VALUE(size) (-1UL)
354 #endif /* CONFIG_EEH */
355 
356 #ifdef CONFIG_PPC64
357 /*
358  * MMIO read/write operations with EEH support.
359  */
360 static inline u8 eeh_readb(const volatile void __iomem *addr)
361 {
362         u8 val = in_8(addr);
363         if (EEH_POSSIBLE_ERROR(val, u8))
364                 eeh_check_failure(addr);
365         return val;
366 }
367 
368 static inline u16 eeh_readw(const volatile void __iomem *addr)
369 {
370         u16 val = in_le16(addr);
371         if (EEH_POSSIBLE_ERROR(val, u16))
372                 eeh_check_failure(addr);
373         return val;
374 }
375 
376 static inline u32 eeh_readl(const volatile void __iomem *addr)
377 {
378         u32 val = in_le32(addr);
379         if (EEH_POSSIBLE_ERROR(val, u32))
380                 eeh_check_failure(addr);
381         return val;
382 }
383 
384 static inline u64 eeh_readq(const volatile void __iomem *addr)
385 {
386         u64 val = in_le64(addr);
387         if (EEH_POSSIBLE_ERROR(val, u64))
388                 eeh_check_failure(addr);
389         return val;
390 }
391 
392 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
393 {
394         u16 val = in_be16(addr);
395         if (EEH_POSSIBLE_ERROR(val, u16))
396                 eeh_check_failure(addr);
397         return val;
398 }
399 
400 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
401 {
402         u32 val = in_be32(addr);
403         if (EEH_POSSIBLE_ERROR(val, u32))
404                 eeh_check_failure(addr);
405         return val;
406 }
407 
408 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
409 {
410         u64 val = in_be64(addr);
411         if (EEH_POSSIBLE_ERROR(val, u64))
412                 eeh_check_failure(addr);
413         return val;
414 }
415 
416 static inline void eeh_memcpy_fromio(void *dest, const
417                                      volatile void __iomem *src,
418                                      unsigned long n)
419 {
420         _memcpy_fromio(dest, src, n);
421 
422         /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
423          * were copied. Check all four bytes.
424          */
425         if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
426                 eeh_check_failure(src);
427 }
428 
429 /* in-string eeh macros */
430 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
431                               int ns)
432 {
433         _insb(addr, buf, ns);
434         if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
435                 eeh_check_failure(addr);
436 }
437 
438 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
439                               int ns)
440 {
441         _insw(addr, buf, ns);
442         if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
443                 eeh_check_failure(addr);
444 }
445 
446 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
447                               int nl)
448 {
449         _insl(addr, buf, nl);
450         if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
451                 eeh_check_failure(addr);
452 }
453 
454 #endif /* CONFIG_PPC64 */
455 #endif /* __KERNEL__ */
456 #endif /* _POWERPC_EEH_H */
457 

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