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Linux/arch/powerpc/include/asm/fsl_lbc.h

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  1 /* Freescale Local Bus Controller
  2  *
  3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
  4  *
  5  * Authors: Nick Spence <nick.spence@freescale.com>,
  6  *          Scott Wood <scottwood@freescale.com>
  7  *          Jack Lan <jack.lan@freescale.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 22  */
 23 
 24 #ifndef __ASM_FSL_LBC_H
 25 #define __ASM_FSL_LBC_H
 26 
 27 #include <linux/compiler.h>
 28 #include <linux/types.h>
 29 #include <linux/io.h>
 30 #include <linux/device.h>
 31 #include <linux/spinlock.h>
 32 
 33 struct fsl_lbc_bank {
 34         __be32 br;             /**< Base Register  */
 35 #define BR_BA           0xFFFF8000
 36 #define BR_BA_SHIFT             15
 37 #define BR_PS           0x00001800
 38 #define BR_PS_SHIFT             11
 39 #define BR_PS_8         0x00000800  /* Port Size 8 bit */
 40 #define BR_PS_16        0x00001000  /* Port Size 16 bit */
 41 #define BR_PS_32        0x00001800  /* Port Size 32 bit */
 42 #define BR_DECC         0x00000600
 43 #define BR_DECC_SHIFT            9
 44 #define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
 45 #define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
 46 #define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
 47 #define BR_WP           0x00000100
 48 #define BR_WP_SHIFT              8
 49 #define BR_MSEL         0x000000E0
 50 #define BR_MSEL_SHIFT            5
 51 #define BR_MS_GPCM      0x00000000  /* GPCM */
 52 #define BR_MS_FCM       0x00000020  /* FCM */
 53 #define BR_MS_SDRAM     0x00000060  /* SDRAM */
 54 #define BR_MS_UPMA      0x00000080  /* UPMA */
 55 #define BR_MS_UPMB      0x000000A0  /* UPMB */
 56 #define BR_MS_UPMC      0x000000C0  /* UPMC */
 57 #define BR_V            0x00000001
 58 #define BR_V_SHIFT               0
 59 #define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
 60 
 61         __be32 or;             /**< Base Register  */
 62 #define OR0 0x5004
 63 #define OR1 0x500C
 64 #define OR2 0x5014
 65 #define OR3 0x501C
 66 #define OR4 0x5024
 67 #define OR5 0x502C
 68 #define OR6 0x5034
 69 #define OR7 0x503C
 70 
 71 #define OR_FCM_AM               0xFFFF8000
 72 #define OR_FCM_AM_SHIFT                 15
 73 #define OR_FCM_BCTLD            0x00001000
 74 #define OR_FCM_BCTLD_SHIFT              12
 75 #define OR_FCM_PGS              0x00000400
 76 #define OR_FCM_PGS_SHIFT                10
 77 #define OR_FCM_CSCT             0x00000200
 78 #define OR_FCM_CSCT_SHIFT                9
 79 #define OR_FCM_CST              0x00000100
 80 #define OR_FCM_CST_SHIFT                 8
 81 #define OR_FCM_CHT              0x00000080
 82 #define OR_FCM_CHT_SHIFT                 7
 83 #define OR_FCM_SCY              0x00000070
 84 #define OR_FCM_SCY_SHIFT                 4
 85 #define OR_FCM_SCY_1            0x00000010
 86 #define OR_FCM_SCY_2            0x00000020
 87 #define OR_FCM_SCY_3            0x00000030
 88 #define OR_FCM_SCY_4            0x00000040
 89 #define OR_FCM_SCY_5            0x00000050
 90 #define OR_FCM_SCY_6            0x00000060
 91 #define OR_FCM_SCY_7            0x00000070
 92 #define OR_FCM_RST              0x00000008
 93 #define OR_FCM_RST_SHIFT                 3
 94 #define OR_FCM_TRLX             0x00000004
 95 #define OR_FCM_TRLX_SHIFT                2
 96 #define OR_FCM_EHTR             0x00000002
 97 #define OR_FCM_EHTR_SHIFT                1
 98 
 99 #define OR_GPCM_AM              0xFFFF8000
100 #define OR_GPCM_AM_SHIFT                15
101 };
102 
103 struct fsl_lbc_regs {
104         struct fsl_lbc_bank bank[12];
105         u8 res0[0x8];
106         __be32 mar;             /**< UPM Address Register */
107         u8 res1[0x4];
108         __be32 mamr;            /**< UPMA Mode Register */
109 #define MxMR_OP_NO      (0 << 28) /**< normal operation */
110 #define MxMR_OP_WA      (1 << 28) /**< write array */
111 #define MxMR_OP_RA      (2 << 28) /**< read array */
112 #define MxMR_OP_RP      (3 << 28) /**< run pattern */
113 #define MxMR_MAD        0x3f      /**< machine address */
114         __be32 mbmr;            /**< UPMB Mode Register */
115         __be32 mcmr;            /**< UPMC Mode Register */
116         u8 res2[0x8];
117         __be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
118         __be32 mdr;             /**< UPM Data Register */
119         u8 res3[0x4];
120         __be32 lsor;            /**< Special Operation Initiation Register */
121         __be32 lsdmr;           /**< SDRAM Mode Register */
122         u8 res4[0x8];
123         __be32 lurt;            /**< UPM Refresh Timer */
124         __be32 lsrt;            /**< SDRAM Refresh Timer */
125         u8 res5[0x8];
126         __be32 ltesr;           /**< Transfer Error Status Register */
127 #define LTESR_BM   0x80000000
128 #define LTESR_FCT  0x40000000
129 #define LTESR_PAR  0x20000000
130 #define LTESR_WP   0x04000000
131 #define LTESR_ATMW 0x00800000
132 #define LTESR_ATMR 0x00400000
133 #define LTESR_CS   0x00080000
134 #define LTESR_UPM  0x00000002
135 #define LTESR_CC   0x00000001
136 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
137 #define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
138                          | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
139                          | LTESR_CC)
140 #define LTESR_CLEAR     0xFFFFFFFF
141 #define LTECCR_CLEAR    0xFFFFFFFF
142 #define LTESR_STATUS    LTESR_MASK
143 #define LTEIR_ENABLE    LTESR_MASK
144 #define LTEDR_ENABLE    0x00000000
145         __be32 ltedr;           /**< Transfer Error Disable Register */
146         __be32 lteir;           /**< Transfer Error Interrupt Register */
147         __be32 lteatr;          /**< Transfer Error Attributes Register */
148         __be32 ltear;           /**< Transfer Error Address Register */
149         __be32 lteccr;          /**< Transfer Error ECC Register */
150         u8 res6[0x8];
151         __be32 lbcr;            /**< Configuration Register */
152 #define LBCR_LDIS  0x80000000
153 #define LBCR_LDIS_SHIFT    31
154 #define LBCR_BCTLC 0x00C00000
155 #define LBCR_BCTLC_SHIFT   22
156 #define LBCR_AHD   0x00200000
157 #define LBCR_LPBSE 0x00020000
158 #define LBCR_LPBSE_SHIFT   17
159 #define LBCR_EPAR  0x00010000
160 #define LBCR_EPAR_SHIFT    16
161 #define LBCR_BMT   0x0000FF00
162 #define LBCR_BMT_SHIFT      8
163 #define LBCR_BMTPS 0x0000000F
164 #define LBCR_BMTPS_SHIFT    0
165 #define LBCR_INIT  0x00040000
166         __be32 lcrr;            /**< Clock Ratio Register */
167 #define LCRR_DBYP    0x80000000
168 #define LCRR_DBYP_SHIFT      31
169 #define LCRR_BUFCMDC 0x30000000
170 #define LCRR_BUFCMDC_SHIFT   28
171 #define LCRR_ECL     0x03000000
172 #define LCRR_ECL_SHIFT       24
173 #define LCRR_EADC    0x00030000
174 #define LCRR_EADC_SHIFT      16
175 #define LCRR_CLKDIV  0x0000000F
176 #define LCRR_CLKDIV_SHIFT     0
177         u8 res7[0x8];
178         __be32 fmr;             /**< Flash Mode Register */
179 #define FMR_CWTO     0x0000F000
180 #define FMR_CWTO_SHIFT       12
181 #define FMR_BOOT     0x00000800
182 #define FMR_ECCM     0x00000100
183 #define FMR_AL       0x00000030
184 #define FMR_AL_SHIFT          4
185 #define FMR_OP       0x00000003
186 #define FMR_OP_SHIFT          0
187         __be32 fir;             /**< Flash Instruction Register */
188 #define FIR_OP0      0xF0000000
189 #define FIR_OP0_SHIFT        28
190 #define FIR_OP1      0x0F000000
191 #define FIR_OP1_SHIFT        24
192 #define FIR_OP2      0x00F00000
193 #define FIR_OP2_SHIFT        20
194 #define FIR_OP3      0x000F0000
195 #define FIR_OP3_SHIFT        16
196 #define FIR_OP4      0x0000F000
197 #define FIR_OP4_SHIFT        12
198 #define FIR_OP5      0x00000F00
199 #define FIR_OP5_SHIFT         8
200 #define FIR_OP6      0x000000F0
201 #define FIR_OP6_SHIFT         4
202 #define FIR_OP7      0x0000000F
203 #define FIR_OP7_SHIFT         0
204 #define FIR_OP_NOP   0x0        /* No operation and end of sequence */
205 #define FIR_OP_CA    0x1        /* Issue current column address */
206 #define FIR_OP_PA    0x2        /* Issue current block+page address */
207 #define FIR_OP_UA    0x3        /* Issue user defined address */
208 #define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
209 #define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
210 #define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
211 #define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
212 #define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
213 #define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
214 #define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
215 #define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
216 #define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
217 #define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
218 #define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
219 #define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
220         __be32 fcr;             /**< Flash Command Register */
221 #define FCR_CMD0     0xFF000000
222 #define FCR_CMD0_SHIFT       24
223 #define FCR_CMD1     0x00FF0000
224 #define FCR_CMD1_SHIFT       16
225 #define FCR_CMD2     0x0000FF00
226 #define FCR_CMD2_SHIFT        8
227 #define FCR_CMD3     0x000000FF
228 #define FCR_CMD3_SHIFT        0
229         __be32 fbar;            /**< Flash Block Address Register */
230 #define FBAR_BLK     0x00FFFFFF
231         __be32 fpar;            /**< Flash Page Address Register */
232 #define FPAR_SP_PI   0x00007C00
233 #define FPAR_SP_PI_SHIFT     10
234 #define FPAR_SP_MS   0x00000200
235 #define FPAR_SP_CI   0x000001FF
236 #define FPAR_SP_CI_SHIFT      0
237 #define FPAR_LP_PI   0x0003F000
238 #define FPAR_LP_PI_SHIFT     12
239 #define FPAR_LP_MS   0x00000800
240 #define FPAR_LP_CI   0x000007FF
241 #define FPAR_LP_CI_SHIFT      0
242         __be32 fbcr;            /**< Flash Byte Count Register */
243 #define FBCR_BC      0x00000FFF
244 };
245 
246 /*
247  * FSL UPM routines
248  */
249 struct fsl_upm {
250         __be32 __iomem *mxmr;
251         int width;
252 };
253 
254 extern u32 fsl_lbc_addr(phys_addr_t addr_base);
255 extern int fsl_lbc_find(phys_addr_t addr_base);
256 extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
257 
258 /**
259  * fsl_upm_start_pattern - start UPM patterns execution
260  * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
261  * @pat_offset: UPM pattern offset for the command to be executed
262  *
263  * This routine programmes UPM so the next memory access that hits an UPM
264  * will trigger pattern execution, starting at pat_offset.
265  */
266 static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
267 {
268         clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
269 }
270 
271 /**
272  * fsl_upm_end_pattern - end UPM patterns execution
273  * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
274  *
275  * This routine reverts UPM to normal operation mode.
276  */
277 static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
278 {
279         clrbits32(upm->mxmr, MxMR_OP_RP);
280 
281         while (in_be32(upm->mxmr) & MxMR_OP_RP)
282                 cpu_relax();
283 }
284 
285 /* overview of the fsl lbc controller */
286 
287 struct fsl_lbc_ctrl {
288         /* device info */
289         struct device                   *dev;
290         struct fsl_lbc_regs __iomem     *regs;
291         int                             irq[2];
292         wait_queue_head_t               irq_wait;
293         spinlock_t                      lock;
294         void                            *nand;
295 
296         /* status read from LTESR by irq handler */
297         unsigned int                    irq_status;
298 
299 #ifdef CONFIG_SUSPEND
300         /* save regs when system go to deep-sleep */
301         struct fsl_lbc_regs             *saved_regs;
302 #endif
303 };
304 
305 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
306                                u32 mar);
307 extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
308 
309 #endif /* __ASM_FSL_LBC_H */
310 

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