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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/opal.h

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  1 /*
  2  * PowerNV OPAL definitions.
  3  *
  4  * Copyright 2011 IBM Corp.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version
  9  * 2 of the License, or (at your option) any later version.
 10  */
 11 
 12 #ifndef _ASM_POWERPC_OPAL_H
 13 #define _ASM_POWERPC_OPAL_H
 14 
 15 #include <asm/opal-api.h>
 16 
 17 #ifndef __ASSEMBLY__
 18 
 19 #include <linux/notifier.h>
 20 
 21 /* We calculate number of sg entries based on PAGE_SIZE */
 22 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
 23 
 24 /* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
 25 #define OPAL_BUSY_DELAY_MS      10
 26 
 27 /* /sys/firmware/opal */
 28 extern struct kobject *opal_kobj;
 29 
 30 /* /ibm,opal */
 31 extern struct device_node *opal_node;
 32 
 33 /* API functions */
 34 int64_t opal_invalid_call(void);
 35 int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
 36 int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
 37                         uint64_t bdf);
 38 int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
 39                         uint64_t lpcr);
 40 int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
 41                         uint64_t addr, uint64_t PE_mask);
 42 int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
 43                                 uint64_t PE_handle);
 44 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
 45                         uint64_t rate_phys, uint32_t size);
 46 int64_t opal_console_write(int64_t term_number, __be64 *length,
 47                            const uint8_t *buffer);
 48 int64_t opal_console_read(int64_t term_number, __be64 *length,
 49                           uint8_t *buffer);
 50 int64_t opal_console_write_buffer_space(int64_t term_number,
 51                                         __be64 *length);
 52 int64_t opal_console_flush(int64_t term_number);
 53 int64_t opal_rtc_read(__be32 *year_month_day,
 54                       __be64 *hour_minute_second_millisecond);
 55 int64_t opal_rtc_write(uint32_t year_month_day,
 56                        uint64_t hour_minute_second_millisecond);
 57 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
 58 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
 59                        uint32_t hour_min);
 60 int64_t opal_cec_power_down(uint64_t request);
 61 int64_t opal_cec_reboot(void);
 62 int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
 63 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 64 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 65 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 66 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 67 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 68                                     uint64_t tce_mem_size);
 69 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 70                                     uint64_t tce_mem_size);
 71 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 72                                   uint64_t offset, uint8_t *data);
 73 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 74                                        uint64_t offset, __be16 *data);
 75 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 76                                   uint64_t offset, __be32 *data);
 77 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 78                                    uint64_t offset, uint8_t data);
 79 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 80                                         uint64_t offset, uint16_t data);
 81 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 82                                    uint64_t offset, uint32_t data);
 83 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 84 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 85 int64_t opal_register_exception_handler(uint64_t opal_exception,
 86                                         uint64_t handler_address,
 87                                         uint64_t glue_cache_line);
 88 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 89                                    uint8_t *freeze_state,
 90                                    __be16 *pci_error_type,
 91                                    __be64 *phb_status);
 92 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 93                                   uint64_t eeh_action_token);
 94 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
 95                                 uint64_t eeh_action_token);
 96 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
 97                             uint32_t func, uint64_t addr, uint64_t mask);
 98 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 99 
100 
101 
102 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
103                                  uint16_t window_num, uint16_t enable);
104 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
105                                     uint16_t window_num,
106                                     uint64_t starting_real_address,
107                                     uint64_t starting_pci_address,
108                                     uint64_t size);
109 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
110                                     uint16_t window_type, uint16_t window_num,
111                                     uint16_t segment_num);
112 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
113                                       uint64_t ivt_addr, uint64_t ivt_len,
114                                       uint64_t reject_array_addr,
115                                       uint64_t peltv_addr);
116 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
117                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
118                         uint8_t pe_action);
119 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
120                            uint8_t state);
121 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
122 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
123                                 uint32_t state);
124 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
125                                   uint8_t *p_bit, uint8_t *q_bit);
126 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
127                                   uint8_t p_bit, uint8_t q_bit);
128 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
129 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
130                              uint32_t xive_num);
131 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
132                              __be32 *interrupt_source_number);
133 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
134                         uint8_t msi_range, __be32 *msi_address,
135                         __be32 *message_data);
136 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
137                         uint32_t xive_num, uint8_t msi_range,
138                         __be64 *msi_address, __be32 *message_data);
139 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
140 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
141 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
142 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
143                                    uint16_t tce_levels, uint64_t tce_table_addr,
144                                    uint64_t tce_table_size, uint64_t tce_page_size);
145 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
146                                         uint16_t dma_window_number, uint64_t pci_start_addr,
147                                         uint64_t pci_mem_size);
148 int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
149 
150 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
151                                    uint64_t diag_buffer_len);
152 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
153                                    uint64_t diag_buffer_len);
154 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
155                                     uint64_t diag_buffer_len);
156 int64_t opal_pci_fence_phb(uint64_t phb_id);
157 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
158 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
159 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
160 int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
161 int64_t opal_get_dpo_status(__be64 *dpo_timeout);
162 int64_t opal_set_system_attention_led(uint8_t led_action);
163 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
164                             __be16 *pci_error_type, __be16 *severity);
165 int64_t opal_pci_poll(uint64_t id);
166 int64_t opal_return_cpu(void);
167 int64_t opal_check_token(uint64_t token);
168 int64_t opal_reinit_cpus(uint64_t flags);
169 
170 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
171 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
172 
173 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
174                        uint32_t addr, uint32_t data, uint32_t sz);
175 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
176                       uint32_t addr, __be32 *data, uint32_t sz);
177 
178 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
179 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
180 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
181 int64_t opal_send_ack_elog(uint64_t log_id);
182 void opal_resend_pending_logs(void);
183 
184 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
185 int64_t opal_manage_flash(uint8_t op);
186 int64_t opal_update_flash(uint64_t blk_list);
187 int64_t opal_dump_init(uint8_t dump_type);
188 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
189 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
190 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
191 int64_t opal_dump_ack(uint32_t dump_id);
192 int64_t opal_dump_resend_notification(void);
193 
194 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
195 int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
196                                         uint64_t num_lines);
197 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
198 int64_t opal_sync_host_reboot(void);
199 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
200                 uint64_t length);
201 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
202                 uint64_t length);
203 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
204 int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
205 int64_t opal_handle_hmi(void);
206 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
207 int64_t opal_unregister_dump_region(uint32_t id);
208 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
209 int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
210 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
211 int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
212 int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
213 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
214                 uint64_t msg_len);
215 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
216                 uint64_t *msg_len);
217 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
218                          struct opal_i2c_request *oreq);
219 int64_t opal_prd_msg(struct opal_prd_msg *msg);
220 int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
221                           __be64 *led_value, __be64 *max_led_type);
222 int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
223                           const u64 led_value, __be64 *max_led_type);
224 
225 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
226                 uint64_t size, uint64_t token);
227 int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
228                 uint64_t size, uint64_t token);
229 int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
230                 uint64_t token);
231 int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
232 int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
233 int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
234 int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
235                                  uint64_t data);
236 int64_t opal_pci_poll2(uint64_t id, uint64_t data);
237 
238 int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
239 int64_t opal_int_set_cppr(uint8_t cppr);
240 int64_t opal_int_eoi(uint32_t xirr);
241 int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
242 int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
243                           uint32_t pe_num, uint32_t tce_size,
244                           uint64_t dma_addr, uint32_t npages);
245 int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
246 int64_t opal_xive_reset(uint64_t version);
247 int64_t opal_xive_get_irq_info(uint32_t girq,
248                                __be64 *out_flags,
249                                __be64 *out_eoi_page,
250                                __be64 *out_trig_page,
251                                __be32 *out_esb_shift,
252                                __be32 *out_src_chip);
253 int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
254                                  uint8_t *out_prio, __be32 *out_lirq);
255 int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
256                                  uint32_t lirq);
257 int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
258                                  __be64 *out_qpage,
259                                  __be64 *out_qsize,
260                                  __be64 *out_qeoi_page,
261                                  __be32 *out_escalate_irq,
262                                  __be64 *out_qflags);
263 int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
264                                  uint64_t qpage,
265                                  uint64_t qsize,
266                                  uint64_t qflags);
267 int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
268 int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
269 int64_t opal_xive_free_vp_block(uint64_t vp);
270 int64_t opal_xive_get_vp_info(uint64_t vp,
271                               __be64 *out_flags,
272                               __be64 *out_cam_value,
273                               __be64 *out_report_cl_pair,
274                               __be32 *out_chip_id);
275 int64_t opal_xive_set_vp_info(uint64_t vp,
276                               uint64_t flags,
277                               uint64_t report_cl_pair);
278 int64_t opal_xive_allocate_irq(uint32_t chip_id);
279 int64_t opal_xive_free_irq(uint32_t girq);
280 int64_t opal_xive_sync(uint32_t type, uint32_t id);
281 int64_t opal_xive_dump(uint32_t type, uint32_t id);
282 int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
283                         uint64_t desc, uint16_t pe_number);
284 
285 int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
286                                                         uint64_t cpu_pir);
287 int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
288 int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
289 
290 int opal_get_powercap(u32 handle, int token, u32 *pcap);
291 int opal_set_powercap(u32 handle, int token, u32 pcap);
292 int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
293 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
294 int opal_sensor_group_clear(u32 group_hndl, int token);
295 int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
296 int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
297 
298 s64 opal_signal_system_reset(s32 cpu);
299 s64 opal_quiesce(u64 shutdown_type, s32 cpu);
300 
301 /* Internal functions */
302 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
303                                    int depth, void *data);
304 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
305                                  const char *uname, int depth, void *data);
306 extern void opal_configure_cores(void);
307 
308 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
309 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
310 extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
311 extern int opal_flush_chars(uint32_t vtermno, bool wait);
312 extern int opal_flush_console(uint32_t vtermno);
313 
314 extern void hvc_opal_init_early(void);
315 
316 extern int opal_notifier_register(struct notifier_block *nb);
317 extern int opal_notifier_unregister(struct notifier_block *nb);
318 
319 extern int opal_message_notifier_register(enum opal_msg_type msg_type,
320                                                 struct notifier_block *nb);
321 extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
322                                             struct notifier_block *nb);
323 extern void opal_notifier_enable(void);
324 extern void opal_notifier_disable(void);
325 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
326 
327 extern int opal_async_get_token_interruptible(void);
328 extern int opal_async_release_token(int token);
329 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
330 extern int opal_async_wait_response_interruptible(uint64_t token,
331                 struct opal_msg *msg);
332 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
333 extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
334 extern int sensor_group_enable(u32 grp_hndl, bool enable);
335 
336 struct rtc_time;
337 extern time64_t opal_get_boot_time(void);
338 extern void opal_nvram_init(void);
339 extern void opal_flash_update_init(void);
340 extern void opal_flash_update_print_message(void);
341 extern int opal_elog_init(void);
342 extern void opal_platform_dump_init(void);
343 extern void opal_sys_param_init(void);
344 extern void opal_msglog_init(void);
345 extern void opal_msglog_sysfs_init(void);
346 extern int opal_async_comp_init(void);
347 extern int opal_sensor_init(void);
348 extern int opal_hmi_handler_init(void);
349 extern int opal_event_init(void);
350 
351 extern int opal_machine_check(struct pt_regs *regs);
352 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
353 extern int opal_hmi_exception_early(struct pt_regs *regs);
354 extern int opal_handle_hmi_exception(struct pt_regs *regs);
355 
356 extern void opal_shutdown(void);
357 extern int opal_resync_timebase(void);
358 
359 extern void opal_lpc_init(void);
360 
361 extern void opal_kmsg_init(void);
362 
363 extern int opal_event_request(unsigned int opal_event_nr);
364 
365 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
366                                              unsigned long vmalloc_size);
367 void opal_free_sg_list(struct opal_sg_list *sg);
368 
369 extern int opal_error_code(int rc);
370 
371 ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
372 
373 static inline int opal_get_async_rc(struct opal_msg msg)
374 {
375         if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
376                 return OPAL_PARAMETER;
377         else
378                 return be64_to_cpu(msg.params[1]);
379 }
380 
381 void opal_wake_poller(void);
382 
383 void opal_powercap_init(void);
384 void opal_psr_init(void);
385 void opal_sensor_groups_init(void);
386 
387 #endif /* __ASSEMBLY__ */
388 
389 #endif /* _ASM_POWERPC_OPAL_H */
390 

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