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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/perf_event_server.h

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  1 /*
  2  * Performance event support - PowerPC classic/server specific definitions.
  3  *
  4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version
  9  * 2 of the License, or (at your option) any later version.
 10  */
 11 
 12 #include <linux/types.h>
 13 #include <asm/hw_irq.h>
 14 
 15 #define MAX_HWEVENTS            8
 16 #define MAX_EVENT_ALTERNATIVES  8
 17 #define MAX_LIMITED_HWCOUNTERS  2
 18 
 19 /*
 20  * This struct provides the constants and functions needed to
 21  * describe the PMU on a particular POWER-family CPU.
 22  */
 23 struct power_pmu {
 24         const char      *name;
 25         int             n_counter;
 26         int             max_alternatives;
 27         unsigned long   add_fields;
 28         unsigned long   test_adder;
 29         int             (*compute_mmcr)(u64 events[], int n_ev,
 30                                 unsigned int hwc[], unsigned long mmcr[]);
 31         int             (*get_constraint)(u64 event_id, unsigned long *mskp,
 32                                 unsigned long *valp);
 33         int             (*get_alternatives)(u64 event_id, unsigned int flags,
 34                                 u64 alt[]);
 35         void            (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
 36         int             (*limited_pmc_event)(u64 event_id);
 37         u32             flags;
 38         int             n_generic;
 39         int             *generic_events;
 40         int             (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
 41                                [PERF_COUNT_HW_CACHE_OP_MAX]
 42                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
 43 };
 44 
 45 /*
 46  * Values for power_pmu.flags
 47  */
 48 #define PPMU_LIMITED_PMC5_6     1       /* PMC5/6 have limited function */
 49 #define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
 50 
 51 /*
 52  * Values for flags to get_alternatives()
 53  */
 54 #define PPMU_LIMITED_PMC_OK     1       /* can put this on a limited PMC */
 55 #define PPMU_LIMITED_PMC_REQD   2       /* have to put this on a limited PMC */
 56 #define PPMU_ONLY_COUNT_RUN     4       /* only counting in run state */
 57 
 58 extern int register_power_pmu(struct power_pmu *);
 59 
 60 struct pt_regs;
 61 extern unsigned long perf_misc_flags(struct pt_regs *regs);
 62 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 63 
 64 #define PERF_EVENT_INDEX_OFFSET 1
 65 
 66 /*
 67  * Only override the default definitions in include/linux/perf_event.h
 68  * if we have hardware PMU support.
 69  */
 70 #ifdef CONFIG_PPC_PERF_CTRS
 71 #define perf_misc_flags(regs)   perf_misc_flags(regs)
 72 #endif
 73 
 74 /*
 75  * The power_pmu.get_constraint function returns a 32/64-bit value and
 76  * a 32/64-bit mask that express the constraints between this event_id and
 77  * other events.
 78  *
 79  * The value and mask are divided up into (non-overlapping) bitfields
 80  * of three different types:
 81  *
 82  * Select field: this expresses the constraint that some set of bits
 83  * in MMCR* needs to be set to a specific value for this event_id.  For a
 84  * select field, the mask contains 1s in every bit of the field, and
 85  * the value contains a unique value for each possible setting of the
 86  * MMCR* bits.  The constraint checking code will ensure that two events
 87  * that set the same field in their masks have the same value in their
 88  * value dwords.
 89  *
 90  * Add field: this expresses the constraint that there can be at most
 91  * N events in a particular class.  A field of k bits can be used for
 92  * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
 93  * set (and the other bits 0), and the value has only the least significant
 94  * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
 95  * in the struct power_pmu for this processor come into play.  The
 96  * add_fields value contains 1 in the LSB of the field, and the
 97  * test_adder contains 2^(k-1) - 1 - N in the field.
 98  *
 99  * NAND field: this expresses the constraint that you may not have events
100  * in all of a set of classes.  (For example, on PPC970, you can't select
101  * events from the FPU, ISU and IDU simultaneously, although any two are
102  * possible.)  For N classes, the field is N+1 bits wide, and each class
103  * is assigned one bit from the least-significant N bits.  The mask has
104  * only the most-significant bit set, and the value has only the bit
105  * for the event_id's class set.  The test_adder has the least significant
106  * bit set in the field.
107  *
108  * If an event_id is not subject to the constraint expressed by a particular
109  * field, then it will have 0 in both the mask and value for that field.
110  */
111 

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