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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/ppc_asm.h

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  1 /*
  2  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
  3  */
  4 #ifndef _ASM_POWERPC_PPC_ASM_H
  5 #define _ASM_POWERPC_PPC_ASM_H
  6 
  7 #include <linux/stringify.h>
  8 #include <asm/asm-compat.h>
  9 #include <asm/processor.h>
 10 #include <asm/ppc-opcode.h>
 11 #include <asm/firmware.h>
 12 
 13 #ifdef __ASSEMBLY__
 14 
 15 #define SZL                     (BITS_PER_LONG/8)
 16 
 17 /*
 18  * Stuff for accurate CPU time accounting.
 19  * These macros handle transitions between user and system state
 20  * in exception entry and exit and accumulate time to the
 21  * user_time and system_time fields in the paca.
 22  */
 23 
 24 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 25 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
 26 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
 27 #define ACCOUNT_STOLEN_TIME
 28 #else
 29 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)                             \
 30         MFTB(ra);                       /* get timebase */              \
 31         PPC_LL  rb, ACCOUNT_STARTTIME_USER(ptr);                        \
 32         PPC_STL ra, ACCOUNT_STARTTIME(ptr);                             \
 33         subf    rb,rb,ra;               /* subtract start value */      \
 34         PPC_LL  ra, ACCOUNT_USER_TIME(ptr);                             \
 35         add     ra,ra,rb;               /* add on to user time */       \
 36         PPC_STL ra, ACCOUNT_USER_TIME(ptr);                             \
 37 
 38 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)                              \
 39         MFTB(ra);                       /* get timebase */              \
 40         PPC_LL  rb, ACCOUNT_STARTTIME(ptr);                             \
 41         PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr);                        \
 42         subf    rb,rb,ra;               /* subtract start value */      \
 43         PPC_LL  ra, ACCOUNT_SYSTEM_TIME(ptr);                           \
 44         add     ra,ra,rb;               /* add on to system time */     \
 45         PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
 46 
 47 #ifdef CONFIG_PPC_SPLPAR
 48 #define ACCOUNT_STOLEN_TIME                                             \
 49 BEGIN_FW_FTR_SECTION;                                                   \
 50         beq     33f;                                                    \
 51         /* from user - see if there are any DTL entries to process */   \
 52         ld      r10,PACALPPACAPTR(r13); /* get ptr to VPA */            \
 53         ld      r11,PACA_DTL_RIDX(r13); /* get log read index */        \
 54         addi    r10,r10,LPPACA_DTLIDX;                                  \
 55         LDX_BE  r10,0,r10;              /* get log write index */       \
 56         cmpd    cr1,r11,r10;                                            \
 57         beq+    cr1,33f;                                                \
 58         bl      accumulate_stolen_time;                         \
 59         ld      r12,_MSR(r1);                                           \
 60         andi.   r10,r12,MSR_PR;         /* Restore cr0 (coming from user) */ \
 61 33:                                                                     \
 62 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 63 
 64 #else  /* CONFIG_PPC_SPLPAR */
 65 #define ACCOUNT_STOLEN_TIME
 66 
 67 #endif /* CONFIG_PPC_SPLPAR */
 68 
 69 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 70 
 71 /*
 72  * Macros for storing registers into and loading registers from
 73  * exception frames.
 74  */
 75 #ifdef __powerpc64__
 76 #define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
 77 #define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
 78 #define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
 79 #define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
 80 #else
 81 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
 82 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
 83 #define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
 84                                 SAVE_10GPRS(22, base)
 85 #define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
 86                                 REST_10GPRS(22, base)
 87 #endif
 88 
 89 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
 90 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
 91 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
 92 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
 93 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
 94 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
 95 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
 96 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
 97 
 98 #define SAVE_FPR(n, base)       stfd    n,8*TS_FPRWIDTH*(n)(base)
 99 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
100 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
101 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
102 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
103 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
104 #define REST_FPR(n, base)       lfd     n,8*TS_FPRWIDTH*(n)(base)
105 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
106 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
107 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
108 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
109 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
110 
111 #define SAVE_VR(n,b,base)       li b,16*(n);  stvx n,base,b
112 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
113 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
114 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
115 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
116 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
117 #define REST_VR(n,b,base)       li b,16*(n); lvx n,base,b
118 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
119 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
120 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
121 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
122 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
123 
124 #ifdef __BIG_ENDIAN__
125 #define STXVD2X_ROT(n,b,base)           STXVD2X(n,b,base)
126 #define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base)
127 #else
128 #define STXVD2X_ROT(n,b,base)           XXSWAPD(n,n);           \
129                                         STXVD2X(n,b,base);      \
130                                         XXSWAPD(n,n)
131 
132 #define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base);       \
133                                         XXSWAPD(n,n)
134 #endif
135 /* Save the lower 32 VSRs in the thread VSR region */
136 #define SAVE_VSR(n,b,base)      li b,16*(n);  STXVD2X_ROT(n,R##base,R##b)
137 #define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
138 #define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
139 #define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
140 #define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
141 #define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
142 #define REST_VSR(n,b,base)      li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
143 #define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
144 #define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
145 #define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
146 #define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
147 #define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
148 
149 /*
150  * b = base register for addressing, o = base offset from register of 1st EVR
151  * n = first EVR, s = scratch
152  */
153 #define SAVE_EVR(n,s,b,o)       evmergehi s,s,n; stw s,o+4*(n)(b)
154 #define SAVE_2EVRS(n,s,b,o)     SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
155 #define SAVE_4EVRS(n,s,b,o)     SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
156 #define SAVE_8EVRS(n,s,b,o)     SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
157 #define SAVE_16EVRS(n,s,b,o)    SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
158 #define SAVE_32EVRS(n,s,b,o)    SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
159 #define REST_EVR(n,s,b,o)       lwz s,o+4*(n)(b); evmergelo n,s,n
160 #define REST_2EVRS(n,s,b,o)     REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
161 #define REST_4EVRS(n,s,b,o)     REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
162 #define REST_8EVRS(n,s,b,o)     REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
163 #define REST_16EVRS(n,s,b,o)    REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
164 #define REST_32EVRS(n,s,b,o)    REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
165 
166 /* Macros to adjust thread priority for hardware multithreading */
167 #define HMT_VERY_LOW    or      31,31,31        # very low priority
168 #define HMT_LOW         or      1,1,1
169 #define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
170 #define HMT_MEDIUM      or      2,2,2
171 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
172 #define HMT_HIGH        or      3,3,3
173 #define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
174 
175 #ifdef CONFIG_PPC64
176 #define ULONG_SIZE      8
177 #else
178 #define ULONG_SIZE      4
179 #endif
180 #define __VCPU_GPR(n)   (VCPU_GPRS + (n * ULONG_SIZE))
181 #define VCPU_GPR(n)     __VCPU_GPR(__REG_##n)
182 
183 #ifdef __KERNEL__
184 #ifdef CONFIG_PPC64
185 
186 #define STACKFRAMESIZE 256
187 #define __STK_REG(i)   (112 + ((i)-14)*8)
188 #define STK_REG(i)     __STK_REG(__REG_##i)
189 
190 #ifdef PPC64_ELF_ABI_v2
191 #define STK_GOT         24
192 #define __STK_PARAM(i)  (32 + ((i)-3)*8)
193 #else
194 #define STK_GOT         40
195 #define __STK_PARAM(i)  (48 + ((i)-3)*8)
196 #endif
197 #define STK_PARAM(i)    __STK_PARAM(__REG_##i)
198 
199 #ifdef PPC64_ELF_ABI_v2
200 
201 #define _GLOBAL(name) \
202         .align 2 ; \
203         .type name,@function; \
204         .globl name; \
205 name:
206 
207 #define _GLOBAL_TOC(name) \
208         .align 2 ; \
209         .type name,@function; \
210         .globl name; \
211 name: \
212 0:      addis r2,r12,(.TOC.-0b)@ha; \
213         addi r2,r2,(.TOC.-0b)@l; \
214         .localentry name,.-name
215 
216 #define DOTSYM(a)       a
217 
218 #else
219 
220 #define XGLUE(a,b) a##b
221 #define GLUE(a,b) XGLUE(a,b)
222 
223 #define _GLOBAL(name) \
224         .align 2 ; \
225         .globl name; \
226         .globl GLUE(.,name); \
227         .pushsection ".opd","aw"; \
228 name: \
229         .quad GLUE(.,name); \
230         .quad .TOC.@tocbase; \
231         .quad 0; \
232         .popsection; \
233         .type GLUE(.,name),@function; \
234 GLUE(.,name):
235 
236 #define _GLOBAL_TOC(name) _GLOBAL(name)
237 
238 #define DOTSYM(a)       GLUE(.,a)
239 
240 #endif
241 
242 #else /* 32-bit */
243 
244 #define _ENTRY(n)       \
245         .globl n;       \
246 n:
247 
248 #define _GLOBAL(n)      \
249         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
250         .globl n;       \
251 n:
252 
253 #define _GLOBAL_TOC(name) _GLOBAL(name)
254 
255 #endif
256 
257 /*
258  * __kprobes (the C annotation) puts the symbol into the .kprobes.text
259  * section, which gets emitted at the end of regular text.
260  *
261  * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
262  * a blacklist. The former is for core kprobe functions/data, the
263  * latter is for those that incdentially must be excluded from probing
264  * and allows them to be linked at more optimal location within text.
265  */
266 #ifdef CONFIG_KPROBES
267 #define _ASM_NOKPROBE_SYMBOL(entry)                     \
268         .pushsection "_kprobe_blacklist","aw";          \
269         PPC_LONG (entry) ;                              \
270         .popsection
271 #else
272 #define _ASM_NOKPROBE_SYMBOL(entry)
273 #endif
274 
275 #define FUNC_START(name)        _GLOBAL(name)
276 #define FUNC_END(name)
277 
278 /* 
279  * LOAD_REG_IMMEDIATE(rn, expr)
280  *   Loads the value of the constant expression 'expr' into register 'rn'
281  *   using immediate instructions only.  Use this when it's important not
282  *   to reference other data (i.e. on ppc64 when the TOC pointer is not
283  *   valid) and when 'expr' is a constant or absolute address.
284  *
285  * LOAD_REG_ADDR(rn, name)
286  *   Loads the address of label 'name' into register 'rn'.  Use this when
287  *   you don't particularly need immediate instructions only, but you need
288  *   the whole address in one register (e.g. it's a structure address and
289  *   you want to access various offsets within it).  On ppc32 this is
290  *   identical to LOAD_REG_IMMEDIATE.
291  *
292  * LOAD_REG_ADDR_PIC(rn, name)
293  *   Loads the address of label 'name' into register 'run'. Use this when
294  *   the kernel doesn't run at the linked or relocated address. Please
295  *   note that this macro will clobber the lr register.
296  *
297  * LOAD_REG_ADDRBASE(rn, name)
298  * ADDROFF(name)
299  *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
300  *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
301  *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
302  *   in size, so is suitable for use directly as an offset in load and store
303  *   instructions.  Use this when loading/storing a single word or less as:
304  *      LOAD_REG_ADDRBASE(rX, name)
305  *      ld      rY,ADDROFF(name)(rX)
306  */
307 
308 /* Be careful, this will clobber the lr register. */
309 #define LOAD_REG_ADDR_PIC(reg, name)            \
310         bl      0f;                             \
311 0:      mflr    reg;                            \
312         addis   reg,reg,(name - 0b)@ha;         \
313         addi    reg,reg,(name - 0b)@l;
314 
315 #ifdef __powerpc64__
316 #ifdef HAVE_AS_ATHIGH
317 #define __AS_ATHIGH high
318 #else
319 #define __AS_ATHIGH h
320 #endif
321 #define LOAD_REG_IMMEDIATE(reg,expr)            \
322         lis     reg,(expr)@highest;             \
323         ori     reg,reg,(expr)@higher;  \
324         rldicr  reg,reg,32,31;          \
325         oris    reg,reg,(expr)@__AS_ATHIGH;     \
326         ori     reg,reg,(expr)@l;
327 
328 #define LOAD_REG_ADDR(reg,name)                 \
329         ld      reg,name@got(r2)
330 
331 #define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
332 #define ADDROFF(name)                   0
333 
334 /* offsets for stack frame layout */
335 #define LRSAVE  16
336 
337 #else /* 32-bit */
338 
339 #define LOAD_REG_IMMEDIATE(reg,expr)            \
340         lis     reg,(expr)@ha;          \
341         addi    reg,reg,(expr)@l;
342 
343 #define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE(reg, name)
344 
345 #define LOAD_REG_ADDRBASE(reg, name)    lis     reg,name@ha
346 #define ADDROFF(name)                   name@l
347 
348 /* offsets for stack frame layout */
349 #define LRSAVE  4
350 
351 #endif
352 
353 /* various errata or part fixups */
354 #ifdef CONFIG_PPC601_SYNC_FIX
355 #define SYNC                            \
356 BEGIN_FTR_SECTION                       \
357         sync;                           \
358         isync;                          \
359 END_FTR_SECTION_IFSET(CPU_FTR_601)
360 #define SYNC_601                        \
361 BEGIN_FTR_SECTION                       \
362         sync;                           \
363 END_FTR_SECTION_IFSET(CPU_FTR_601)
364 #define ISYNC_601                       \
365 BEGIN_FTR_SECTION                       \
366         isync;                          \
367 END_FTR_SECTION_IFSET(CPU_FTR_601)
368 #else
369 #define SYNC
370 #define SYNC_601
371 #define ISYNC_601
372 #endif
373 
374 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
375 #define MFTB(dest)                      \
376 90:     mfspr dest, SPRN_TBRL;          \
377 BEGIN_FTR_SECTION_NESTED(96);           \
378         cmpwi dest,0;                   \
379         beq-  90b;                      \
380 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
381 #else
382 #define MFTB(dest)                      MFTBL(dest)
383 #endif
384 
385 #ifdef CONFIG_PPC_8xx
386 #define MFTBL(dest)                     mftb dest
387 #define MFTBU(dest)                     mftbu dest
388 #else
389 #define MFTBL(dest)                     mfspr dest, SPRN_TBRL
390 #define MFTBU(dest)                     mfspr dest, SPRN_TBRU
391 #endif
392 
393 #ifndef CONFIG_SMP
394 #define TLBSYNC
395 #else /* CONFIG_SMP */
396 /* tlbsync is not implemented on 601 */
397 #define TLBSYNC                         \
398 BEGIN_FTR_SECTION                       \
399         tlbsync;                        \
400         sync;                           \
401 END_FTR_SECTION_IFCLR(CPU_FTR_601)
402 #endif
403 
404 #ifdef CONFIG_PPC64
405 #define MTOCRF(FXM, RS)                 \
406         BEGIN_FTR_SECTION_NESTED(848);  \
407         mtcrf   (FXM), RS;              \
408         FTR_SECTION_ELSE_NESTED(848);   \
409         mtocrf (FXM), RS;               \
410         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
411 #endif
412 
413 /*
414  * This instruction is not implemented on the PPC 603 or 601; however, on
415  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
416  * All of these instructions exist in the 8xx, they have magical powers,
417  * and they must be used.
418  */
419 
420 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
421 #define tlbia                                   \
422         li      r4,1024;                        \
423         mtctr   r4;                             \
424         lis     r4,KERNELBASE@h;                \
425         .machine push;                          \
426         .machine "power4";                      \
427 0:      tlbie   r4;                             \
428         .machine pop;                           \
429         addi    r4,r4,0x1000;                   \
430         bdnz    0b
431 #endif
432 
433 
434 #ifdef CONFIG_IBM440EP_ERR42
435 #define PPC440EP_ERR42 isync
436 #else
437 #define PPC440EP_ERR42
438 #endif
439 
440 /* The following stops all load and store data streams associated with stream
441  * ID (ie. streams created explicitly).  The embedded and server mnemonics for
442  * dcbt are different so we use machine "power4" here explicitly.
443  */
444 #define DCBT_STOP_ALL_STREAM_IDS(scratch)       \
445 .machine push ;                                 \
446 .machine "power4" ;                             \
447        lis     scratch,0x60000000@h;            \
448        dcbt    0,scratch,0b01010;               \
449 .machine pop
450 
451 /*
452  * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
453  * keep the address intact to be compatible with code shared with
454  * 32-bit classic.
455  *
456  * On the other hand, I find it useful to have them behave as expected
457  * by their name (ie always do the addition) on 64-bit BookE
458  */
459 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
460 #define toreal(rd)
461 #define fromreal(rd)
462 
463 /*
464  * We use addis to ensure compatibility with the "classic" ppc versions of
465  * these macros, which use rs = 0 to get the tophys offset in rd, rather than
466  * converting the address in r0, and so this version has to do that too
467  * (i.e. set register rd to 0 when rs == 0).
468  */
469 #define tophys(rd,rs)                           \
470         addis   rd,rs,0
471 
472 #define tovirt(rd,rs)                           \
473         addis   rd,rs,0
474 
475 #elif defined(CONFIG_PPC64)
476 #define toreal(rd)              /* we can access c000... in real mode */
477 #define fromreal(rd)
478 
479 #define tophys(rd,rs)                           \
480         clrldi  rd,rs,2
481 
482 #define tovirt(rd,rs)                           \
483         rotldi  rd,rs,16;                       \
484         ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
485         rotldi  rd,rd,48
486 #else
487 /*
488  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
489  * physical base address of RAM at compile time.
490  */
491 #define toreal(rd)      tophys(rd,rd)
492 #define fromreal(rd)    tovirt(rd,rd)
493 
494 #define tophys(rd,rs)                           \
495 0:      addis   rd,rs,-PAGE_OFFSET@h;           \
496         .section ".vtop_fixup","aw";            \
497         .align  1;                              \
498         .long   0b;                             \
499         .previous
500 
501 #define tovirt(rd,rs)                           \
502 0:      addis   rd,rs,PAGE_OFFSET@h;            \
503         .section ".ptov_fixup","aw";            \
504         .align  1;                              \
505         .long   0b;                             \
506         .previous
507 #endif
508 
509 #ifdef CONFIG_PPC_BOOK3S_64
510 #define RFI             rfid
511 #define MTMSRD(r)       mtmsrd  r
512 #define MTMSR_EERI(reg) mtmsrd  reg,1
513 #else
514 #ifndef CONFIG_40x
515 #define RFI             rfi
516 #else
517 #define RFI             rfi; b .        /* Prevent prefetch past rfi */
518 #endif
519 #define MTMSRD(r)       mtmsr   r
520 #define MTMSR_EERI(reg) mtmsr   reg
521 #endif
522 
523 #endif /* __KERNEL__ */
524 
525 /* The boring bits... */
526 
527 /* Condition Register Bit Fields */
528 
529 #define cr0     0
530 #define cr1     1
531 #define cr2     2
532 #define cr3     3
533 #define cr4     4
534 #define cr5     5
535 #define cr6     6
536 #define cr7     7
537 
538 
539 /*
540  * General Purpose Registers (GPRs)
541  *
542  * The lower case r0-r31 should be used in preference to the upper
543  * case R0-R31 as they provide more error checking in the assembler.
544  * Use R0-31 only when really nessesary.
545  */
546 
547 #define r0      %r0
548 #define r1      %r1
549 #define r2      %r2
550 #define r3      %r3
551 #define r4      %r4
552 #define r5      %r5
553 #define r6      %r6
554 #define r7      %r7
555 #define r8      %r8
556 #define r9      %r9
557 #define r10     %r10
558 #define r11     %r11
559 #define r12     %r12
560 #define r13     %r13
561 #define r14     %r14
562 #define r15     %r15
563 #define r16     %r16
564 #define r17     %r17
565 #define r18     %r18
566 #define r19     %r19
567 #define r20     %r20
568 #define r21     %r21
569 #define r22     %r22
570 #define r23     %r23
571 #define r24     %r24
572 #define r25     %r25
573 #define r26     %r26
574 #define r27     %r27
575 #define r28     %r28
576 #define r29     %r29
577 #define r30     %r30
578 #define r31     %r31
579 
580 
581 /* Floating Point Registers (FPRs) */
582 
583 #define fr0     0
584 #define fr1     1
585 #define fr2     2
586 #define fr3     3
587 #define fr4     4
588 #define fr5     5
589 #define fr6     6
590 #define fr7     7
591 #define fr8     8
592 #define fr9     9
593 #define fr10    10
594 #define fr11    11
595 #define fr12    12
596 #define fr13    13
597 #define fr14    14
598 #define fr15    15
599 #define fr16    16
600 #define fr17    17
601 #define fr18    18
602 #define fr19    19
603 #define fr20    20
604 #define fr21    21
605 #define fr22    22
606 #define fr23    23
607 #define fr24    24
608 #define fr25    25
609 #define fr26    26
610 #define fr27    27
611 #define fr28    28
612 #define fr29    29
613 #define fr30    30
614 #define fr31    31
615 
616 /* AltiVec Registers (VPRs) */
617 
618 #define v0      0
619 #define v1      1
620 #define v2      2
621 #define v3      3
622 #define v4      4
623 #define v5      5
624 #define v6      6
625 #define v7      7
626 #define v8      8
627 #define v9      9
628 #define v10     10
629 #define v11     11
630 #define v12     12
631 #define v13     13
632 #define v14     14
633 #define v15     15
634 #define v16     16
635 #define v17     17
636 #define v18     18
637 #define v19     19
638 #define v20     20
639 #define v21     21
640 #define v22     22
641 #define v23     23
642 #define v24     24
643 #define v25     25
644 #define v26     26
645 #define v27     27
646 #define v28     28
647 #define v29     29
648 #define v30     30
649 #define v31     31
650 
651 /* VSX Registers (VSRs) */
652 
653 #define vs0     0
654 #define vs1     1
655 #define vs2     2
656 #define vs3     3
657 #define vs4     4
658 #define vs5     5
659 #define vs6     6
660 #define vs7     7
661 #define vs8     8
662 #define vs9     9
663 #define vs10    10
664 #define vs11    11
665 #define vs12    12
666 #define vs13    13
667 #define vs14    14
668 #define vs15    15
669 #define vs16    16
670 #define vs17    17
671 #define vs18    18
672 #define vs19    19
673 #define vs20    20
674 #define vs21    21
675 #define vs22    22
676 #define vs23    23
677 #define vs24    24
678 #define vs25    25
679 #define vs26    26
680 #define vs27    27
681 #define vs28    28
682 #define vs29    29
683 #define vs30    30
684 #define vs31    31
685 #define vs32    32
686 #define vs33    33
687 #define vs34    34
688 #define vs35    35
689 #define vs36    36
690 #define vs37    37
691 #define vs38    38
692 #define vs39    39
693 #define vs40    40
694 #define vs41    41
695 #define vs42    42
696 #define vs43    43
697 #define vs44    44
698 #define vs45    45
699 #define vs46    46
700 #define vs47    47
701 #define vs48    48
702 #define vs49    49
703 #define vs50    50
704 #define vs51    51
705 #define vs52    52
706 #define vs53    53
707 #define vs54    54
708 #define vs55    55
709 #define vs56    56
710 #define vs57    57
711 #define vs58    58
712 #define vs59    59
713 #define vs60    60
714 #define vs61    61
715 #define vs62    62
716 #define vs63    63
717 
718 /* SPE Registers (EVPRs) */
719 
720 #define evr0    0
721 #define evr1    1
722 #define evr2    2
723 #define evr3    3
724 #define evr4    4
725 #define evr5    5
726 #define evr6    6
727 #define evr7    7
728 #define evr8    8
729 #define evr9    9
730 #define evr10   10
731 #define evr11   11
732 #define evr12   12
733 #define evr13   13
734 #define evr14   14
735 #define evr15   15
736 #define evr16   16
737 #define evr17   17
738 #define evr18   18
739 #define evr19   19
740 #define evr20   20
741 #define evr21   21
742 #define evr22   22
743 #define evr23   23
744 #define evr24   24
745 #define evr25   25
746 #define evr26   26
747 #define evr27   27
748 #define evr28   28
749 #define evr29   29
750 #define evr30   30
751 #define evr31   31
752 
753 /* some stab codes */
754 #define N_FUN   36
755 #define N_RSYM  64
756 #define N_SLINE 68
757 #define N_SO    100
758 
759 /*
760  * Create an endian fixup trampoline
761  *
762  * This starts with a "tdi 0,0,0x48" instruction which is
763  * essentially a "trap never", and thus akin to a nop.
764  *
765  * The opcode for this instruction read with the wrong endian
766  * however results in a b . + 8
767  *
768  * So essentially we use that trick to execute the following
769  * trampoline in "reverse endian" if we are running with the
770  * MSR_LE bit set the "wrong" way for whatever endianness the
771  * kernel is built for.
772  */
773 
774 #ifdef CONFIG_PPC_BOOK3E
775 #define FIXUP_ENDIAN
776 #else
777 /*
778  * This version may be used in in HV or non-HV context.
779  * MSR[EE] must be disabled.
780  */
781 #define FIXUP_ENDIAN                                               \
782         tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
783         b     191f;       /* Skip trampoline if endian is good  */ \
784         .long 0xa600607d; /* mfmsr r11                          */ \
785         .long 0x01006b69; /* xori r11,r11,1                     */ \
786         .long 0x00004039; /* li r10,0                           */ \
787         .long 0x6401417d; /* mtmsrd r10,1                       */ \
788         .long 0x05009f42; /* bcl 20,31,$+4                      */ \
789         .long 0xa602487d; /* mflr r10                           */ \
790         .long 0x14004a39; /* addi r10,r10,20                    */ \
791         .long 0xa6035a7d; /* mtsrr0 r10                         */ \
792         .long 0xa6037b7d; /* mtsrr1 r11                         */ \
793         .long 0x2400004c; /* rfid                               */ \
794 191:
795 
796 /*
797  * This version that may only be used with MSR[HV]=1
798  * - Does not clear MSR[RI], so more robust.
799  * - Slightly smaller and faster.
800  */
801 #define FIXUP_ENDIAN_HV                                            \
802         tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
803         b     191f;       /* Skip trampoline if endian is good  */ \
804         .long 0xa600607d; /* mfmsr r11                          */ \
805         .long 0x01006b69; /* xori r11,r11,1                     */ \
806         .long 0x05009f42; /* bcl 20,31,$+4                      */ \
807         .long 0xa602487d; /* mflr r10                           */ \
808         .long 0x14004a39; /* addi r10,r10,20                    */ \
809         .long 0xa64b5a7d; /* mthsrr0 r10                        */ \
810         .long 0xa64b7b7d; /* mthsrr1 r11                        */ \
811         .long 0x2402004c; /* hrfid                              */ \
812 191:
813 
814 #endif /* !CONFIG_PPC_BOOK3E */
815 
816 #endif /*  __ASSEMBLY__ */
817 
818 /*
819  * Helper macro for exception table entries
820  */
821 #define EX_TABLE(_fault, _target)               \
822         stringify_in_c(.section __ex_table,"a";)\
823         stringify_in_c(.balign 4;)              \
824         stringify_in_c(.long (_fault) - . ;)    \
825         stringify_in_c(.long (_target) - . ;)   \
826         stringify_in_c(.previous)
827 
828 #endif /* _ASM_POWERPC_PPC_ASM_H */
829 

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