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TOMOYO Linux Cross Reference
Linux/arch/powerpc/include/asm/spu.h

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  1 /*
  2  * SPU core / file system interface and HW structures
  3  *
  4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
  5  *
  6  * Author: Arnd Bergmann <arndb@de.ibm.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2, or (at your option)
 11  * any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  */
 22 
 23 #ifndef _SPU_H
 24 #define _SPU_H
 25 #ifdef __KERNEL__
 26 
 27 #include <linux/workqueue.h>
 28 #include <linux/device.h>
 29 #include <linux/mutex.h>
 30 #include <asm/reg.h>
 31 #include <asm/copro.h>
 32 
 33 #define LS_SIZE (256 * 1024)
 34 #define LS_ADDR_MASK (LS_SIZE - 1)
 35 
 36 #define MFC_PUT_CMD             0x20
 37 #define MFC_PUTS_CMD            0x28
 38 #define MFC_PUTR_CMD            0x30
 39 #define MFC_PUTF_CMD            0x22
 40 #define MFC_PUTB_CMD            0x21
 41 #define MFC_PUTFS_CMD           0x2A
 42 #define MFC_PUTBS_CMD           0x29
 43 #define MFC_PUTRF_CMD           0x32
 44 #define MFC_PUTRB_CMD           0x31
 45 #define MFC_PUTL_CMD            0x24
 46 #define MFC_PUTRL_CMD           0x34
 47 #define MFC_PUTLF_CMD           0x26
 48 #define MFC_PUTLB_CMD           0x25
 49 #define MFC_PUTRLF_CMD          0x36
 50 #define MFC_PUTRLB_CMD          0x35
 51 
 52 #define MFC_GET_CMD             0x40
 53 #define MFC_GETS_CMD            0x48
 54 #define MFC_GETF_CMD            0x42
 55 #define MFC_GETB_CMD            0x41
 56 #define MFC_GETFS_CMD           0x4A
 57 #define MFC_GETBS_CMD           0x49
 58 #define MFC_GETL_CMD            0x44
 59 #define MFC_GETLF_CMD           0x46
 60 #define MFC_GETLB_CMD           0x45
 61 
 62 #define MFC_SDCRT_CMD           0x80
 63 #define MFC_SDCRTST_CMD         0x81
 64 #define MFC_SDCRZ_CMD           0x89
 65 #define MFC_SDCRS_CMD           0x8D
 66 #define MFC_SDCRF_CMD           0x8F
 67 
 68 #define MFC_GETLLAR_CMD         0xD0
 69 #define MFC_PUTLLC_CMD          0xB4
 70 #define MFC_PUTLLUC_CMD         0xB0
 71 #define MFC_PUTQLLUC_CMD        0xB8
 72 #define MFC_SNDSIG_CMD          0xA0
 73 #define MFC_SNDSIGB_CMD         0xA1
 74 #define MFC_SNDSIGF_CMD         0xA2
 75 #define MFC_BARRIER_CMD         0xC0
 76 #define MFC_EIEIO_CMD           0xC8
 77 #define MFC_SYNC_CMD            0xCC
 78 
 79 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
 80 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
 81 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
 82 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
 83 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
 84 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
 85 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
 86 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
 87 
 88 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
 89 
 90 /* Events for Channels 0-2 */
 91 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
 92 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
 93 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
 94 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
 95 #define MFC_DECREMENTER_EVENT               0x00000020
 96 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
 97 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
 98 #define MFC_SIGNAL_2_EVENT                  0x00000100
 99 #define MFC_SIGNAL_1_EVENT                  0x00000200
100 #define MFC_LLR_LOST_EVENT                  0x00000400
101 #define MFC_PRIV_ATTN_EVENT                 0x00000800
102 #define MFC_MULTI_SRC_EVENT                 0x00001000
103 
104 /* Flag indicating progress during context switch. */
105 #define SPU_CONTEXT_SWITCH_PENDING      0UL
106 #define SPU_CONTEXT_FAULT_PENDING       1UL
107 
108 struct spu_context;
109 struct spu_runqueue;
110 struct spu_lscsa;
111 struct device_node;
112 
113 enum spu_utilization_state {
114         SPU_UTIL_USER,
115         SPU_UTIL_SYSTEM,
116         SPU_UTIL_IOWAIT,
117         SPU_UTIL_IDLE_LOADED,
118         SPU_UTIL_MAX
119 };
120 
121 struct spu {
122         const char *name;
123         unsigned long local_store_phys;
124         u8 *local_store;
125         unsigned long problem_phys;
126         struct spu_problem __iomem *problem;
127         struct spu_priv2 __iomem *priv2;
128         struct list_head cbe_list;
129         struct list_head full_list;
130         enum { SPU_FREE, SPU_USED } alloc_state;
131         int number;
132         unsigned int irqs[3];
133         u32 node;
134         unsigned long flags;
135         u64 class_0_pending;
136         u64 class_0_dar;
137         u64 class_1_dar;
138         u64 class_1_dsisr;
139         size_t ls_size;
140         unsigned int slb_replace;
141         struct mm_struct *mm;
142         struct spu_context *ctx;
143         struct spu_runqueue *rq;
144         unsigned long long timestamp;
145         pid_t pid;
146         pid_t tgid;
147         spinlock_t register_lock;
148 
149         void (* wbox_callback)(struct spu *spu);
150         void (* ibox_callback)(struct spu *spu);
151         void (* stop_callback)(struct spu *spu, int irq);
152         void (* mfc_callback)(struct spu *spu);
153 
154         char irq_c0[8];
155         char irq_c1[8];
156         char irq_c2[8];
157 
158         u64 spe_id;
159 
160         void* pdata; /* platform private data */
161 
162         /* of based platforms only */
163         struct device_node *devnode;
164 
165         /* native only */
166         struct spu_priv1 __iomem *priv1;
167 
168         /* beat only */
169         u64 shadow_int_mask_RW[3];
170 
171         struct device dev;
172 
173         int has_mem_affinity;
174         struct list_head aff_list;
175 
176         struct {
177                 /* protected by interrupt reentrancy */
178                 enum spu_utilization_state util_state;
179                 unsigned long long tstamp;
180                 unsigned long long times[SPU_UTIL_MAX];
181                 unsigned long long vol_ctx_switch;
182                 unsigned long long invol_ctx_switch;
183                 unsigned long long min_flt;
184                 unsigned long long maj_flt;
185                 unsigned long long hash_flt;
186                 unsigned long long slb_flt;
187                 unsigned long long class2_intr;
188                 unsigned long long libassist;
189         } stats;
190 };
191 
192 struct cbe_spu_info {
193         struct mutex list_mutex;
194         struct list_head spus;
195         int n_spus;
196         int nr_active;
197         atomic_t busy_spus;
198         atomic_t reserved_spus;
199 };
200 
201 extern struct cbe_spu_info cbe_spu_info[];
202 
203 void spu_init_channels(struct spu *spu);
204 void spu_irq_setaffinity(struct spu *spu, int cpu);
205 
206 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
207                 void *code, int code_size);
208 
209 extern void spu_invalidate_slbs(struct spu *spu);
210 extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
211 int spu_64k_pages_available(void);
212 
213 /* Calls from the memory management to the SPU */
214 struct mm_struct;
215 extern void spu_flush_all_slbs(struct mm_struct *mm);
216 
217 /* This interface allows a profiler (e.g., OProfile) to store a ref
218  * to spu context information that it creates.  This caching technique
219  * avoids the need to recreate this information after a save/restore operation.
220  *
221  * Assumes the caller has already incremented the ref count to
222  * profile_info; then spu_context_destroy must call kref_put
223  * on prof_info_kref.
224  */
225 void spu_set_profile_private_kref(struct spu_context *ctx,
226                                   struct kref *prof_info_kref,
227                                   void ( * prof_info_release) (struct kref *kref));
228 
229 void *spu_get_profile_private_kref(struct spu_context *ctx);
230 
231 /* system callbacks from the SPU */
232 struct spu_syscall_block {
233         u64 nr_ret;
234         u64 parm[6];
235 };
236 extern long spu_sys_callback(struct spu_syscall_block *s);
237 
238 /* syscalls implemented in spufs */
239 struct file;
240 struct coredump_params;
241 struct spufs_calls {
242         long (*create_thread)(const char __user *name,
243                                         unsigned int flags, umode_t mode,
244                                         struct file *neighbor);
245         long (*spu_run)(struct file *filp, __u32 __user *unpc,
246                                                 __u32 __user *ustatus);
247         int (*coredump_extra_notes_size)(void);
248         int (*coredump_extra_notes_write)(struct coredump_params *cprm);
249         void (*notify_spus_active)(void);
250         struct module *owner;
251 };
252 
253 /* return status from spu_run, same as in libspe */
254 #define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
255 #define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
256 #define SPE_EVENT_SPE_DATA_SEGMENT      0x0020  /*A DMA segmentation error    */
257 #define SPE_EVENT_SPE_DATA_STORAGE      0x0040  /*A DMA storage error */
258 #define SPE_EVENT_INVALID_DMA           0x0800  /* Invalid MFC DMA */
259 
260 /*
261  * Flags for sys_spu_create.
262  */
263 #define SPU_CREATE_EVENTS_ENABLED       0x0001
264 #define SPU_CREATE_GANG                 0x0002
265 #define SPU_CREATE_NOSCHED              0x0004
266 #define SPU_CREATE_ISOLATE              0x0008
267 #define SPU_CREATE_AFFINITY_SPU         0x0010
268 #define SPU_CREATE_AFFINITY_MEM         0x0020
269 
270 #define SPU_CREATE_FLAG_ALL             0x003f /* mask of all valid flags */
271 
272 
273 int register_spu_syscalls(struct spufs_calls *calls);
274 void unregister_spu_syscalls(struct spufs_calls *calls);
275 
276 int spu_add_dev_attr(struct device_attribute *attr);
277 void spu_remove_dev_attr(struct device_attribute *attr);
278 
279 int spu_add_dev_attr_group(struct attribute_group *attrs);
280 void spu_remove_dev_attr_group(struct attribute_group *attrs);
281 
282 /*
283  * Notifier blocks:
284  *
285  * oprofile can get notified when a context switch is performed
286  * on an spe. The notifer function that gets called is passed
287  * a pointer to the SPU structure as well as the object-id that
288  * identifies the binary running on that SPU now.
289  *
290  * For a context save, the object-id that is passed is zero,
291  * identifying that the kernel will run from that moment on.
292  *
293  * For a context restore, the object-id is the value written
294  * to object-id spufs file from user space and the notifer
295  * function can assume that spu->ctx is valid.
296  */
297 struct notifier_block;
298 int spu_switch_event_register(struct notifier_block * n);
299 int spu_switch_event_unregister(struct notifier_block * n);
300 
301 extern void notify_spus_active(void);
302 extern void do_notify_spus_active(void);
303 
304 /*
305  * This defines the Local Store, Problem Area and Privilege Area of an SPU.
306  */
307 
308 union mfc_tag_size_class_cmd {
309         struct {
310                 u16 mfc_size;
311                 u16 mfc_tag;
312                 u8  pad;
313                 u8  mfc_rclassid;
314                 u16 mfc_cmd;
315         } u;
316         struct {
317                 u32 mfc_size_tag32;
318                 u32 mfc_class_cmd32;
319         } by32;
320         u64 all64;
321 };
322 
323 struct mfc_cq_sr {
324         u64 mfc_cq_data0_RW;
325         u64 mfc_cq_data1_RW;
326         u64 mfc_cq_data2_RW;
327         u64 mfc_cq_data3_RW;
328 };
329 
330 struct spu_problem {
331 #define MS_SYNC_PENDING         1L
332         u64 spc_mssync_RW;                                      /* 0x0000 */
333         u8  pad_0x0008_0x3000[0x3000 - 0x0008];
334 
335         /* DMA Area */
336         u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
337         u32 mfc_lsa_W;                                          /* 0x3004 */
338         u64 mfc_ea_W;                                           /* 0x3008 */
339         union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
340         u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
341         u32 dma_qstatus_R;                                      /* 0x3104 */
342         u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
343         u32 dma_querytype_RW;                                   /* 0x3204 */
344         u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
345         u32 dma_querymask_RW;                                   /* 0x321c */
346         u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
347         u32 dma_tagstatus_R;                                    /* 0x322c */
348 #define DMA_TAGSTATUS_INTR_ANY  1u
349 #define DMA_TAGSTATUS_INTR_ALL  2u
350         u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
351 
352         /* SPU Control Area */
353         u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
354         u32 pu_mb_R;                                            /* 0x4004 */
355         u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
356         u32 spu_mb_W;                                           /* 0x400c */
357         u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
358         u32 mb_stat_R;                                          /* 0x4014 */
359         u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
360         u32 spu_runcntl_RW;                                     /* 0x401c */
361 #define SPU_RUNCNTL_STOP        0L
362 #define SPU_RUNCNTL_RUNNABLE    1L
363 #define SPU_RUNCNTL_ISOLATE     2L
364         u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
365         u32 spu_status_R;                                       /* 0x4024 */
366 #define SPU_STOP_STATUS_SHIFT           16
367 #define SPU_STATUS_STOPPED              0x0
368 #define SPU_STATUS_RUNNING              0x1
369 #define SPU_STATUS_STOPPED_BY_STOP      0x2
370 #define SPU_STATUS_STOPPED_BY_HALT      0x4
371 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
372 #define SPU_STATUS_SINGLE_STEP          0x10
373 #define SPU_STATUS_INVALID_INSTR        0x20
374 #define SPU_STATUS_INVALID_CH           0x40
375 #define SPU_STATUS_ISOLATED_STATE       0x80
376 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
377 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
378         u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
379         u32 spu_spe_R;                                          /* 0x402c */
380         u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
381         u32 spu_npc_RW;                                         /* 0x4034 */
382         u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
383 
384         /* Signal Notification Area */
385         u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
386         u32 signal_notify1;                                     /* 0x1400c */
387         u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
388         u32 signal_notify2;                                     /* 0x1c00c */
389 } __attribute__ ((aligned(0x20000)));
390 
391 /* SPU Privilege 2 State Area */
392 struct spu_priv2 {
393         /* MFC Registers */
394         u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
395 
396         /* SLB Management Registers */
397         u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
398         u64 slb_index_W;                                        /* 0x1108 */
399 #define SLB_INDEX_MASK                          0x7L
400         u64 slb_esid_RW;                                        /* 0x1110 */
401         u64 slb_vsid_RW;                                        /* 0x1118 */
402 #define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
403 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
404 #define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
405 #define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
406 #define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
407 #define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
408 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
409 #define SLB_VSID_4K_PAGE                (0x0 << 8)
410 #define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
411 #define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
412 #define SLB_VSID_CLASS_MASK             (0x1ull << 7)
413 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
414         u64 slb_invalidate_entry_W;                             /* 0x1120 */
415         u64 slb_invalidate_all_W;                               /* 0x1128 */
416         u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
417 
418         /* Context Save / Restore Area */
419         struct mfc_cq_sr spuq[16];                              /* 0x2000 */
420         struct mfc_cq_sr puq[8];                                /* 0x2200 */
421         u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
422 
423         /* MFC Control */
424         u64 mfc_control_RW;                                     /* 0x3000 */
425 #define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
426 #define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
427 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
428 #define MFC_CNTL_SUSPEND_MASK                   (1ull << 4)
429 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
430 #define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
431 #define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
432 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
433 #define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
434 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
435 #define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
436 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
437 #define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
438 #define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
439 #define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
440 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
441 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
442 #define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
443 #define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
444 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
445 #define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
446 #define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
447 #define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
448         u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
449 
450         /* Interrupt Mailbox */
451         u64 puint_mb_R;                                         /* 0x4000 */
452         u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
453 
454         /* SPU Control */
455         u64 spu_privcntl_RW;                                    /* 0x4040 */
456 #define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
457 #define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
458 #define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
459 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
460 #define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
461 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
462 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
463 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
464         u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
465         u64 spu_lslr_RW;                                        /* 0x4058 */
466         u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
467         u64 spu_chnlcnt_RW;                                     /* 0x4068 */
468         u64 spu_chnldata_RW;                                    /* 0x4070 */
469         u64 spu_cfg_RW;                                         /* 0x4078 */
470         u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
471 
472         /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
473         u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
474         u64 spu_tag_status_query_RW;                            /* 0x5008 */
475 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
476 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
477         u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
478 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
479 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
480         u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
481 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
482 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
483 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
484         u64 spu_atomic_status_RW;                               /* 0x5020 */
485 } __attribute__ ((aligned(0x20000)));
486 
487 /* SPU Privilege 1 State Area */
488 struct spu_priv1 {
489         /* Control and Configuration Area */
490         u64 mfc_sr1_RW;                                         /* 0x000 */
491 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
492 #define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
493 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
494 #define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
495 #define MFC_STATE1_RELOCATE_MASK                0x10ull
496 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
497 #define MFC_STATE1_TABLE_SEARCH_MASK            0x40ull
498         u64 mfc_lpid_RW;                                        /* 0x008 */
499         u64 spu_idr_RW;                                         /* 0x010 */
500         u64 mfc_vr_RO;                                          /* 0x018 */
501 #define MFC_VERSION_BITS                (0xffff << 16)
502 #define MFC_REVISION_BITS               (0xffff)
503 #define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
504 #define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
505         u64 spu_vr_RO;                                          /* 0x020 */
506 #define SPU_VERSION_BITS                (0xffff << 16)
507 #define SPU_REVISION_BITS               (0xffff)
508 #define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
509 #define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
510         u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
511 
512         /* Interrupt Area */
513         u64 int_mask_RW[3];                                     /* 0x100 */
514 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
515 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
516 #define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
517 #define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
518 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
519 #define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
520 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
521 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
522 #define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
523 #define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
524 #define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
525 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
526 #define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR            0x10L
527         u8  pad_0x118_0x140[0x28];                              /* 0x118 */
528         u64 int_stat_RW[3];                                     /* 0x140 */
529 #define CLASS0_DMA_ALIGNMENT_INTR                       0x1L
530 #define CLASS0_INVALID_DMA_COMMAND_INTR                 0x2L
531 #define CLASS0_SPU_ERROR_INTR                           0x4L
532 #define CLASS0_INTR_MASK                                0x7L
533 #define CLASS1_SEGMENT_FAULT_INTR                       0x1L
534 #define CLASS1_STORAGE_FAULT_INTR                       0x2L
535 #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR           0x4L
536 #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR           0x8L
537 #define CLASS1_INTR_MASK                                0xfL
538 #define CLASS2_MAILBOX_INTR                             0x1L
539 #define CLASS2_SPU_STOP_INTR                            0x2L
540 #define CLASS2_SPU_HALT_INTR                            0x4L
541 #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR          0x8L
542 #define CLASS2_MAILBOX_THRESHOLD_INTR                   0x10L
543 #define CLASS2_INTR_MASK                                0x1fL
544         u8  pad_0x158_0x180[0x28];                              /* 0x158 */
545         u64 int_route_RW;                                       /* 0x180 */
546 
547         /* Interrupt Routing */
548         u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
549 
550         /* Atomic Unit Control Area */
551         u64 mfc_atomic_flush_RW;                                /* 0x200 */
552 #define mfc_atomic_flush_enable                 0x1L
553         u8  pad_0x208_0x280[0x78];                              /* 0x208 */
554         u64 resource_allocation_groupID_RW;                     /* 0x280 */
555         u64 resource_allocation_enable_RW;                      /* 0x288 */
556         u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
557 
558         /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
559 
560         u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
561 #define smf_sbi_mask_lsb        56
562 #define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
563 #define smf_sbi_mask            (0x301LL << smf_sbi_shift)
564 #define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
565 #define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
566 #define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
567 #define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
568         u64 smf_ato_signal_sel;                                 /* 0x3d0 */
569 #define smf_ato_mask_lsb        35
570 #define smf_ato_shift           (63 - smf_ato_mask_lsb)
571 #define smf_ato_mask            (0x3LL << smf_ato_shift)
572 #define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
573 #define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
574         u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
575 
576         /* TLB Management Registers */
577         u64 mfc_sdr_RW;                                         /* 0x400 */
578         u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
579         u64 tlb_index_hint_RO;                                  /* 0x500 */
580         u64 tlb_index_W;                                        /* 0x508 */
581         u64 tlb_vpn_RW;                                         /* 0x510 */
582         u64 tlb_rpn_RW;                                         /* 0x518 */
583         u8  pad_0x520_0x540[0x20];                              /* 0x520 */
584         u64 tlb_invalidate_entry_W;                             /* 0x540 */
585         u64 tlb_invalidate_all_W;                               /* 0x548 */
586         u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
587 
588         /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
589         u64 smm_hid;                                            /* 0x580 */
590 #define PAGE_SIZE_MASK          0xf000000000000000ull
591 #define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
592         u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
593 
594         /* MFC Status/Control Area */
595         u64 mfc_accr_RW;                                        /* 0x600 */
596 #define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
597 #define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
598 #define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
599 #define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
600         u8  pad_0x608_0x610[0x8];                               /* 0x608 */
601         u64 mfc_dsisr_RW;                                       /* 0x610 */
602 #define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
603 #define MFC_DSISR_ACCESS_DENIED         (1 << 27)
604 #define MFC_DSISR_ATOMIC                (1 << 26)
605 #define MFC_DSISR_ACCESS_PUT            (1 << 25)
606 #define MFC_DSISR_ADDR_MATCH            (1 << 22)
607 #define MFC_DSISR_LS                    (1 << 17)
608 #define MFC_DSISR_L                     (1 << 16)
609 #define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
610         u8  pad_0x618_0x620[0x8];                               /* 0x618 */
611         u64 mfc_dar_RW;                                         /* 0x620 */
612         u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
613 
614         /* Replacement Management Table (RMT) Area */
615         u64 rmt_index_RW;                                       /* 0x700 */
616         u8  pad_0x708_0x710[0x8];                               /* 0x708 */
617         u64 rmt_data1_RW;                                       /* 0x710 */
618         u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
619 
620         /* Control/Configuration Registers */
621         u64 mfc_dsir_R;                                         /* 0x800 */
622 #define MFC_DSIR_Q                      (1 << 31)
623 #define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
624         u64 mfc_lsacr_RW;                                       /* 0x808 */
625 #define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
626 #define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
627         u64 mfc_lscrr_R;                                        /* 0x810 */
628 #define MFC_LSCRR_Q                     (1 << 31)
629 #define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
630 #define MFC_LSCRR_QI_SHIFT              32
631 #define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
632         u8  pad_0x818_0x820[0x8];                               /* 0x818 */
633         u64 mfc_tclass_id_RW;                                   /* 0x820 */
634 #define MFC_TCLASS_ID_ENABLE            (1L << 0L)
635 #define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
636 #define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
637 #define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
638 #define MFC_TCLASS_QUOTA_2_SHIFT        8L
639 #define MFC_TCLASS_QUOTA_1_SHIFT        16L
640 #define MFC_TCLASS_QUOTA_0_SHIFT        24L
641 #define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
642 #define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
643 #define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
644         u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
645 
646         /* Real Mode Support Registers */
647         u64 mfc_rm_boundary;                                    /* 0x900 */
648         u8  pad_0x908_0x938[0x30];                              /* 0x908 */
649         u64 smf_dma_signal_sel;                                 /* 0x938 */
650 #define mfc_dma1_mask_lsb       41
651 #define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
652 #define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
653 #define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
654 #define mfc_dma2_mask_lsb       43
655 #define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
656 #define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
657 #define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
658         u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
659         u64 smm_signal_sel;                                     /* 0xa38 */
660 #define smm_sig_mask_lsb        12
661 #define smm_sig_shift           (63 - smm_sig_mask_lsb)
662 #define smm_sig_mask            (0x3LL << smm_sig_shift)
663 #define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
664 #define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
665         u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
666 
667         /* DMA Command Error Area */
668         u64 mfc_cer_R;                                          /* 0xc00 */
669 #define MFC_CER_Q               (1 << 31)
670 #define MFC_CER_SPU_QUEUE       MFC_CER_Q
671         u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
672 
673         /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
674         /* DMA Command Error Area */
675         u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
676 #define SPU_ECC_CNTL_E                  (1ull << 0ull)
677 #define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
678 #define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
679 #define SPU_ECC_CNTL_S                  (1ull << 1ull)
680 #define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
681 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
682 #define SPU_ECC_CNTL_B                  (1ull << 2ull)
683 #define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
684 #define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
685 #define SPU_ECC_CNTL_I_SHIFT            3ull
686 #define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
687 #define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
688 #define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
689 #define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
690 #define SPU_ECC_CNTL_D                  (1ull << 5ull)
691 #define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
692 #define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
693         u64 spu_ecc_stat_RW;                                    /* 0x1008 */
694 #define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
695 #define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
696 #define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
697 #define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
698 #define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
699 #define SPU_ECC_DATA_ERROR              (1ull << 5ul)
700 #define SPU_ECC_DMA_ERROR               (1ull << 6ul)
701 #define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
702         u64 spu_ecc_addr_RW;                                    /* 0x1010 */
703         u64 spu_err_mask_RW;                                    /* 0x1018 */
704 #define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
705 #define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
706         u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
707 
708         /* SPU Debug-Trace Bus (DTB) Selection Registers */
709         u64 spu_trig0_sel;                                      /* 0x1028 */
710         u64 spu_trig1_sel;                                      /* 0x1030 */
711         u64 spu_trig2_sel;                                      /* 0x1038 */
712         u64 spu_trig3_sel;                                      /* 0x1040 */
713         u64 spu_trace_sel;                                      /* 0x1048 */
714 #define spu_trace_sel_mask              0x1f1fLL
715 #define spu_trace_sel_bus0_bits         0x1000LL
716 #define spu_trace_sel_bus2_bits         0x0010LL
717         u64 spu_event0_sel;                                     /* 0x1050 */
718         u64 spu_event1_sel;                                     /* 0x1058 */
719         u64 spu_event2_sel;                                     /* 0x1060 */
720         u64 spu_event3_sel;                                     /* 0x1068 */
721         u64 spu_trace_cntl;                                     /* 0x1070 */
722 } __attribute__ ((aligned(0x2000)));
723 
724 #endif /* __KERNEL__ */
725 #endif
726 

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