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TOMOYO Linux Cross Reference
Linux/arch/powerpc/kernel/iommu.c

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  1 /*
  2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  3  * 
  4  * Rewrite, cleanup, new allocation schemes, virtual merging: 
  5  * Copyright (C) 2004 Olof Johansson, IBM Corporation
  6  *               and  Ben. Herrenschmidt, IBM Corporation
  7  *
  8  * Dynamic DMA mapping support, bus-independent parts.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  * 
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  * GNU General Public License for more details.
 19  * 
 20  * You should have received a copy of the GNU General Public License
 21  * along with this program; if not, write to the Free Software
 22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 23  */
 24 
 25 
 26 #include <linux/init.h>
 27 #include <linux/types.h>
 28 #include <linux/slab.h>
 29 #include <linux/mm.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/string.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/bitmap.h>
 34 #include <linux/iommu-helper.h>
 35 #include <linux/crash_dump.h>
 36 #include <linux/hash.h>
 37 #include <linux/fault-inject.h>
 38 #include <linux/pci.h>
 39 #include <linux/iommu.h>
 40 #include <linux/sched.h>
 41 #include <asm/io.h>
 42 #include <asm/prom.h>
 43 #include <asm/iommu.h>
 44 #include <asm/pci-bridge.h>
 45 #include <asm/machdep.h>
 46 #include <asm/kdump.h>
 47 #include <asm/fadump.h>
 48 #include <asm/vio.h>
 49 #include <asm/tce.h>
 50 
 51 #define DBG(...)
 52 
 53 static int novmerge;
 54 
 55 static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
 56 
 57 static int __init setup_iommu(char *str)
 58 {
 59         if (!strcmp(str, "novmerge"))
 60                 novmerge = 1;
 61         else if (!strcmp(str, "vmerge"))
 62                 novmerge = 0;
 63         return 1;
 64 }
 65 
 66 __setup("iommu=", setup_iommu);
 67 
 68 static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
 69 
 70 /*
 71  * We precalculate the hash to avoid doing it on every allocation.
 72  *
 73  * The hash is important to spread CPUs across all the pools. For example,
 74  * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
 75  * with 4 pools all primary threads would map to the same pool.
 76  */
 77 static int __init setup_iommu_pool_hash(void)
 78 {
 79         unsigned int i;
 80 
 81         for_each_possible_cpu(i)
 82                 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
 83 
 84         return 0;
 85 }
 86 subsys_initcall(setup_iommu_pool_hash);
 87 
 88 #ifdef CONFIG_FAIL_IOMMU
 89 
 90 static DECLARE_FAULT_ATTR(fail_iommu);
 91 
 92 static int __init setup_fail_iommu(char *str)
 93 {
 94         return setup_fault_attr(&fail_iommu, str);
 95 }
 96 __setup("fail_iommu=", setup_fail_iommu);
 97 
 98 static bool should_fail_iommu(struct device *dev)
 99 {
100         return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
101 }
102 
103 static int __init fail_iommu_debugfs(void)
104 {
105         struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
106                                                        NULL, &fail_iommu);
107 
108         return PTR_ERR_OR_ZERO(dir);
109 }
110 late_initcall(fail_iommu_debugfs);
111 
112 static ssize_t fail_iommu_show(struct device *dev,
113                                struct device_attribute *attr, char *buf)
114 {
115         return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
116 }
117 
118 static ssize_t fail_iommu_store(struct device *dev,
119                                 struct device_attribute *attr, const char *buf,
120                                 size_t count)
121 {
122         int i;
123 
124         if (count > 0 && sscanf(buf, "%d", &i) > 0)
125                 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
126 
127         return count;
128 }
129 
130 static DEVICE_ATTR_RW(fail_iommu);
131 
132 static int fail_iommu_bus_notify(struct notifier_block *nb,
133                                  unsigned long action, void *data)
134 {
135         struct device *dev = data;
136 
137         if (action == BUS_NOTIFY_ADD_DEVICE) {
138                 if (device_create_file(dev, &dev_attr_fail_iommu))
139                         pr_warn("Unable to create IOMMU fault injection sysfs "
140                                 "entries\n");
141         } else if (action == BUS_NOTIFY_DEL_DEVICE) {
142                 device_remove_file(dev, &dev_attr_fail_iommu);
143         }
144 
145         return 0;
146 }
147 
148 static struct notifier_block fail_iommu_bus_notifier = {
149         .notifier_call = fail_iommu_bus_notify
150 };
151 
152 static int __init fail_iommu_setup(void)
153 {
154 #ifdef CONFIG_PCI
155         bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
156 #endif
157 #ifdef CONFIG_IBMVIO
158         bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
159 #endif
160 
161         return 0;
162 }
163 /*
164  * Must execute after PCI and VIO subsystem have initialised but before
165  * devices are probed.
166  */
167 arch_initcall(fail_iommu_setup);
168 #else
169 static inline bool should_fail_iommu(struct device *dev)
170 {
171         return false;
172 }
173 #endif
174 
175 static unsigned long iommu_range_alloc(struct device *dev,
176                                        struct iommu_table *tbl,
177                                        unsigned long npages,
178                                        unsigned long *handle,
179                                        unsigned long mask,
180                                        unsigned int align_order)
181 { 
182         unsigned long n, end, start;
183         unsigned long limit;
184         int largealloc = npages > 15;
185         int pass = 0;
186         unsigned long align_mask;
187         unsigned long boundary_size;
188         unsigned long flags;
189         unsigned int pool_nr;
190         struct iommu_pool *pool;
191 
192         align_mask = (1ull << align_order) - 1;
193 
194         /* This allocator was derived from x86_64's bit string search */
195 
196         /* Sanity check */
197         if (unlikely(npages == 0)) {
198                 if (printk_ratelimit())
199                         WARN_ON(1);
200                 return IOMMU_MAPPING_ERROR;
201         }
202 
203         if (should_fail_iommu(dev))
204                 return IOMMU_MAPPING_ERROR;
205 
206         /*
207          * We don't need to disable preemption here because any CPU can
208          * safely use any IOMMU pool.
209          */
210         pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
211 
212         if (largealloc)
213                 pool = &(tbl->large_pool);
214         else
215                 pool = &(tbl->pools[pool_nr]);
216 
217         spin_lock_irqsave(&(pool->lock), flags);
218 
219 again:
220         if ((pass == 0) && handle && *handle &&
221             (*handle >= pool->start) && (*handle < pool->end))
222                 start = *handle;
223         else
224                 start = pool->hint;
225 
226         limit = pool->end;
227 
228         /* The case below can happen if we have a small segment appended
229          * to a large, or when the previous alloc was at the very end of
230          * the available space. If so, go back to the initial start.
231          */
232         if (start >= limit)
233                 start = pool->start;
234 
235         if (limit + tbl->it_offset > mask) {
236                 limit = mask - tbl->it_offset + 1;
237                 /* If we're constrained on address range, first try
238                  * at the masked hint to avoid O(n) search complexity,
239                  * but on second pass, start at 0 in pool 0.
240                  */
241                 if ((start & mask) >= limit || pass > 0) {
242                         spin_unlock(&(pool->lock));
243                         pool = &(tbl->pools[0]);
244                         spin_lock(&(pool->lock));
245                         start = pool->start;
246                 } else {
247                         start &= mask;
248                 }
249         }
250 
251         if (dev)
252                 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
253                                       1 << tbl->it_page_shift);
254         else
255                 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
256         /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
257 
258         n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
259                              boundary_size >> tbl->it_page_shift, align_mask);
260         if (n == -1) {
261                 if (likely(pass == 0)) {
262                         /* First try the pool from the start */
263                         pool->hint = pool->start;
264                         pass++;
265                         goto again;
266 
267                 } else if (pass <= tbl->nr_pools) {
268                         /* Now try scanning all the other pools */
269                         spin_unlock(&(pool->lock));
270                         pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
271                         pool = &tbl->pools[pool_nr];
272                         spin_lock(&(pool->lock));
273                         pool->hint = pool->start;
274                         pass++;
275                         goto again;
276 
277                 } else {
278                         /* Give up */
279                         spin_unlock_irqrestore(&(pool->lock), flags);
280                         return IOMMU_MAPPING_ERROR;
281                 }
282         }
283 
284         end = n + npages;
285 
286         /* Bump the hint to a new block for small allocs. */
287         if (largealloc) {
288                 /* Don't bump to new block to avoid fragmentation */
289                 pool->hint = end;
290         } else {
291                 /* Overflow will be taken care of at the next allocation */
292                 pool->hint = (end + tbl->it_blocksize - 1) &
293                                 ~(tbl->it_blocksize - 1);
294         }
295 
296         /* Update handle for SG allocations */
297         if (handle)
298                 *handle = end;
299 
300         spin_unlock_irqrestore(&(pool->lock), flags);
301 
302         return n;
303 }
304 
305 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
306                               void *page, unsigned int npages,
307                               enum dma_data_direction direction,
308                               unsigned long mask, unsigned int align_order,
309                               unsigned long attrs)
310 {
311         unsigned long entry;
312         dma_addr_t ret = IOMMU_MAPPING_ERROR;
313         int build_fail;
314 
315         entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
316 
317         if (unlikely(entry == IOMMU_MAPPING_ERROR))
318                 return IOMMU_MAPPING_ERROR;
319 
320         entry += tbl->it_offset;        /* Offset into real TCE table */
321         ret = entry << tbl->it_page_shift;      /* Set the return dma address */
322 
323         /* Put the TCEs in the HW table */
324         build_fail = tbl->it_ops->set(tbl, entry, npages,
325                                       (unsigned long)page &
326                                       IOMMU_PAGE_MASK(tbl), direction, attrs);
327 
328         /* tbl->it_ops->set() only returns non-zero for transient errors.
329          * Clean up the table bitmap in this case and return
330          * IOMMU_MAPPING_ERROR. For all other errors the functionality is
331          * not altered.
332          */
333         if (unlikely(build_fail)) {
334                 __iommu_free(tbl, ret, npages);
335                 return IOMMU_MAPPING_ERROR;
336         }
337 
338         /* Flush/invalidate TLB caches if necessary */
339         if (tbl->it_ops->flush)
340                 tbl->it_ops->flush(tbl);
341 
342         /* Make sure updates are seen by hardware */
343         mb();
344 
345         return ret;
346 }
347 
348 static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
349                              unsigned int npages)
350 {
351         unsigned long entry, free_entry;
352 
353         entry = dma_addr >> tbl->it_page_shift;
354         free_entry = entry - tbl->it_offset;
355 
356         if (((free_entry + npages) > tbl->it_size) ||
357             (entry < tbl->it_offset)) {
358                 if (printk_ratelimit()) {
359                         printk(KERN_INFO "iommu_free: invalid entry\n");
360                         printk(KERN_INFO "\tentry     = 0x%lx\n", entry); 
361                         printk(KERN_INFO "\tdma_addr  = 0x%llx\n", (u64)dma_addr);
362                         printk(KERN_INFO "\tTable     = 0x%llx\n", (u64)tbl);
363                         printk(KERN_INFO "\tbus#      = 0x%llx\n", (u64)tbl->it_busno);
364                         printk(KERN_INFO "\tsize      = 0x%llx\n", (u64)tbl->it_size);
365                         printk(KERN_INFO "\tstartOff  = 0x%llx\n", (u64)tbl->it_offset);
366                         printk(KERN_INFO "\tindex     = 0x%llx\n", (u64)tbl->it_index);
367                         WARN_ON(1);
368                 }
369 
370                 return false;
371         }
372 
373         return true;
374 }
375 
376 static struct iommu_pool *get_pool(struct iommu_table *tbl,
377                                    unsigned long entry)
378 {
379         struct iommu_pool *p;
380         unsigned long largepool_start = tbl->large_pool.start;
381 
382         /* The large pool is the last pool at the top of the table */
383         if (entry >= largepool_start) {
384                 p = &tbl->large_pool;
385         } else {
386                 unsigned int pool_nr = entry / tbl->poolsize;
387 
388                 BUG_ON(pool_nr > tbl->nr_pools);
389                 p = &tbl->pools[pool_nr];
390         }
391 
392         return p;
393 }
394 
395 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
396                          unsigned int npages)
397 {
398         unsigned long entry, free_entry;
399         unsigned long flags;
400         struct iommu_pool *pool;
401 
402         entry = dma_addr >> tbl->it_page_shift;
403         free_entry = entry - tbl->it_offset;
404 
405         pool = get_pool(tbl, free_entry);
406 
407         if (!iommu_free_check(tbl, dma_addr, npages))
408                 return;
409 
410         tbl->it_ops->clear(tbl, entry, npages);
411 
412         spin_lock_irqsave(&(pool->lock), flags);
413         bitmap_clear(tbl->it_map, free_entry, npages);
414         spin_unlock_irqrestore(&(pool->lock), flags);
415 }
416 
417 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
418                 unsigned int npages)
419 {
420         __iommu_free(tbl, dma_addr, npages);
421 
422         /* Make sure TLB cache is flushed if the HW needs it. We do
423          * not do an mb() here on purpose, it is not needed on any of
424          * the current platforms.
425          */
426         if (tbl->it_ops->flush)
427                 tbl->it_ops->flush(tbl);
428 }
429 
430 int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
431                      struct scatterlist *sglist, int nelems,
432                      unsigned long mask, enum dma_data_direction direction,
433                      unsigned long attrs)
434 {
435         dma_addr_t dma_next = 0, dma_addr;
436         struct scatterlist *s, *outs, *segstart;
437         int outcount, incount, i, build_fail = 0;
438         unsigned int align;
439         unsigned long handle;
440         unsigned int max_seg_size;
441 
442         BUG_ON(direction == DMA_NONE);
443 
444         if ((nelems == 0) || !tbl)
445                 return 0;
446 
447         outs = s = segstart = &sglist[0];
448         outcount = 1;
449         incount = nelems;
450         handle = 0;
451 
452         /* Init first segment length for backout at failure */
453         outs->dma_length = 0;
454 
455         DBG("sg mapping %d elements:\n", nelems);
456 
457         max_seg_size = dma_get_max_seg_size(dev);
458         for_each_sg(sglist, s, nelems, i) {
459                 unsigned long vaddr, npages, entry, slen;
460 
461                 slen = s->length;
462                 /* Sanity check */
463                 if (slen == 0) {
464                         dma_next = 0;
465                         continue;
466                 }
467                 /* Allocate iommu entries for that segment */
468                 vaddr = (unsigned long) sg_virt(s);
469                 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
470                 align = 0;
471                 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
472                     (vaddr & ~PAGE_MASK) == 0)
473                         align = PAGE_SHIFT - tbl->it_page_shift;
474                 entry = iommu_range_alloc(dev, tbl, npages, &handle,
475                                           mask >> tbl->it_page_shift, align);
476 
477                 DBG("  - vaddr: %lx, size: %lx\n", vaddr, slen);
478 
479                 /* Handle failure */
480                 if (unlikely(entry == IOMMU_MAPPING_ERROR)) {
481                         if (!(attrs & DMA_ATTR_NO_WARN) &&
482                             printk_ratelimit())
483                                 dev_info(dev, "iommu_alloc failed, tbl %p "
484                                          "vaddr %lx npages %lu\n", tbl, vaddr,
485                                          npages);
486                         goto failure;
487                 }
488 
489                 /* Convert entry to a dma_addr_t */
490                 entry += tbl->it_offset;
491                 dma_addr = entry << tbl->it_page_shift;
492                 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
493 
494                 DBG("  - %lu pages, entry: %lx, dma_addr: %lx\n",
495                             npages, entry, dma_addr);
496 
497                 /* Insert into HW table */
498                 build_fail = tbl->it_ops->set(tbl, entry, npages,
499                                               vaddr & IOMMU_PAGE_MASK(tbl),
500                                               direction, attrs);
501                 if(unlikely(build_fail))
502                         goto failure;
503 
504                 /* If we are in an open segment, try merging */
505                 if (segstart != s) {
506                         DBG("  - trying merge...\n");
507                         /* We cannot merge if:
508                          * - allocated dma_addr isn't contiguous to previous allocation
509                          */
510                         if (novmerge || (dma_addr != dma_next) ||
511                             (outs->dma_length + s->length > max_seg_size)) {
512                                 /* Can't merge: create a new segment */
513                                 segstart = s;
514                                 outcount++;
515                                 outs = sg_next(outs);
516                                 DBG("    can't merge, new segment.\n");
517                         } else {
518                                 outs->dma_length += s->length;
519                                 DBG("    merged, new len: %ux\n", outs->dma_length);
520                         }
521                 }
522 
523                 if (segstart == s) {
524                         /* This is a new segment, fill entries */
525                         DBG("  - filling new segment.\n");
526                         outs->dma_address = dma_addr;
527                         outs->dma_length = slen;
528                 }
529 
530                 /* Calculate next page pointer for contiguous check */
531                 dma_next = dma_addr + slen;
532 
533                 DBG("  - dma next is: %lx\n", dma_next);
534         }
535 
536         /* Flush/invalidate TLB caches if necessary */
537         if (tbl->it_ops->flush)
538                 tbl->it_ops->flush(tbl);
539 
540         DBG("mapped %d elements:\n", outcount);
541 
542         /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
543          * next entry of the sglist if we didn't fill the list completely
544          */
545         if (outcount < incount) {
546                 outs = sg_next(outs);
547                 outs->dma_address = IOMMU_MAPPING_ERROR;
548                 outs->dma_length = 0;
549         }
550 
551         /* Make sure updates are seen by hardware */
552         mb();
553 
554         return outcount;
555 
556  failure:
557         for_each_sg(sglist, s, nelems, i) {
558                 if (s->dma_length != 0) {
559                         unsigned long vaddr, npages;
560 
561                         vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
562                         npages = iommu_num_pages(s->dma_address, s->dma_length,
563                                                  IOMMU_PAGE_SIZE(tbl));
564                         __iommu_free(tbl, vaddr, npages);
565                         s->dma_address = IOMMU_MAPPING_ERROR;
566                         s->dma_length = 0;
567                 }
568                 if (s == outs)
569                         break;
570         }
571         return 0;
572 }
573 
574 
575 void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
576                         int nelems, enum dma_data_direction direction,
577                         unsigned long attrs)
578 {
579         struct scatterlist *sg;
580 
581         BUG_ON(direction == DMA_NONE);
582 
583         if (!tbl)
584                 return;
585 
586         sg = sglist;
587         while (nelems--) {
588                 unsigned int npages;
589                 dma_addr_t dma_handle = sg->dma_address;
590 
591                 if (sg->dma_length == 0)
592                         break;
593                 npages = iommu_num_pages(dma_handle, sg->dma_length,
594                                          IOMMU_PAGE_SIZE(tbl));
595                 __iommu_free(tbl, dma_handle, npages);
596                 sg = sg_next(sg);
597         }
598 
599         /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
600          * do not do an mb() here, the affected platforms do not need it
601          * when freeing.
602          */
603         if (tbl->it_ops->flush)
604                 tbl->it_ops->flush(tbl);
605 }
606 
607 static void iommu_table_clear(struct iommu_table *tbl)
608 {
609         /*
610          * In case of firmware assisted dump system goes through clean
611          * reboot process at the time of system crash. Hence it's safe to
612          * clear the TCE entries if firmware assisted dump is active.
613          */
614         if (!is_kdump_kernel() || is_fadump_active()) {
615                 /* Clear the table in case firmware left allocations in it */
616                 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
617                 return;
618         }
619 
620 #ifdef CONFIG_CRASH_DUMP
621         if (tbl->it_ops->get) {
622                 unsigned long index, tceval, tcecount = 0;
623 
624                 /* Reserve the existing mappings left by the first kernel. */
625                 for (index = 0; index < tbl->it_size; index++) {
626                         tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
627                         /*
628                          * Freed TCE entry contains 0x7fffffffffffffff on JS20
629                          */
630                         if (tceval && (tceval != 0x7fffffffffffffffUL)) {
631                                 __set_bit(index, tbl->it_map);
632                                 tcecount++;
633                         }
634                 }
635 
636                 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
637                         printk(KERN_WARNING "TCE table is full; freeing ");
638                         printk(KERN_WARNING "%d entries for the kdump boot\n",
639                                 KDUMP_MIN_TCE_ENTRIES);
640                         for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
641                                 index < tbl->it_size; index++)
642                                 __clear_bit(index, tbl->it_map);
643                 }
644         }
645 #endif
646 }
647 
648 /*
649  * Build a iommu_table structure.  This contains a bit map which
650  * is used to manage allocation of the tce space.
651  */
652 struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
653 {
654         unsigned long sz;
655         static int welcomed = 0;
656         struct page *page;
657         unsigned int i;
658         struct iommu_pool *p;
659 
660         BUG_ON(!tbl->it_ops);
661 
662         /* number of bytes needed for the bitmap */
663         sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
664 
665         page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
666         if (!page)
667                 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
668         tbl->it_map = page_address(page);
669         memset(tbl->it_map, 0, sz);
670 
671         /*
672          * Reserve page 0 so it will not be used for any mappings.
673          * This avoids buggy drivers that consider page 0 to be invalid
674          * to crash the machine or even lose data.
675          */
676         if (tbl->it_offset == 0)
677                 set_bit(0, tbl->it_map);
678 
679         /* We only split the IOMMU table if we have 1GB or more of space */
680         if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
681                 tbl->nr_pools = IOMMU_NR_POOLS;
682         else
683                 tbl->nr_pools = 1;
684 
685         /* We reserve the top 1/4 of the table for large allocations */
686         tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
687 
688         for (i = 0; i < tbl->nr_pools; i++) {
689                 p = &tbl->pools[i];
690                 spin_lock_init(&(p->lock));
691                 p->start = tbl->poolsize * i;
692                 p->hint = p->start;
693                 p->end = p->start + tbl->poolsize;
694         }
695 
696         p = &tbl->large_pool;
697         spin_lock_init(&(p->lock));
698         p->start = tbl->poolsize * i;
699         p->hint = p->start;
700         p->end = tbl->it_size;
701 
702         iommu_table_clear(tbl);
703 
704         if (!welcomed) {
705                 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
706                        novmerge ? "disabled" : "enabled");
707                 welcomed = 1;
708         }
709 
710         return tbl;
711 }
712 
713 static void iommu_table_free(struct kref *kref)
714 {
715         unsigned long bitmap_sz;
716         unsigned int order;
717         struct iommu_table *tbl;
718 
719         tbl = container_of(kref, struct iommu_table, it_kref);
720 
721         if (tbl->it_ops->free)
722                 tbl->it_ops->free(tbl);
723 
724         if (!tbl->it_map) {
725                 kfree(tbl);
726                 return;
727         }
728 
729         /*
730          * In case we have reserved the first bit, we should not emit
731          * the warning below.
732          */
733         if (tbl->it_offset == 0)
734                 clear_bit(0, tbl->it_map);
735 
736         /* verify that table contains no entries */
737         if (!bitmap_empty(tbl->it_map, tbl->it_size))
738                 pr_warn("%s: Unexpected TCEs\n", __func__);
739 
740         /* calculate bitmap size in bytes */
741         bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
742 
743         /* free bitmap */
744         order = get_order(bitmap_sz);
745         free_pages((unsigned long) tbl->it_map, order);
746 
747         /* free table */
748         kfree(tbl);
749 }
750 
751 struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl)
752 {
753         if (kref_get_unless_zero(&tbl->it_kref))
754                 return tbl;
755 
756         return NULL;
757 }
758 EXPORT_SYMBOL_GPL(iommu_tce_table_get);
759 
760 int iommu_tce_table_put(struct iommu_table *tbl)
761 {
762         if (WARN_ON(!tbl))
763                 return 0;
764 
765         return kref_put(&tbl->it_kref, iommu_table_free);
766 }
767 EXPORT_SYMBOL_GPL(iommu_tce_table_put);
768 
769 /* Creates TCEs for a user provided buffer.  The user buffer must be
770  * contiguous real kernel storage (not vmalloc).  The address passed here
771  * comprises a page address and offset into that page. The dma_addr_t
772  * returned will point to the same byte within the page as was passed in.
773  */
774 dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
775                           struct page *page, unsigned long offset, size_t size,
776                           unsigned long mask, enum dma_data_direction direction,
777                           unsigned long attrs)
778 {
779         dma_addr_t dma_handle = IOMMU_MAPPING_ERROR;
780         void *vaddr;
781         unsigned long uaddr;
782         unsigned int npages, align;
783 
784         BUG_ON(direction == DMA_NONE);
785 
786         vaddr = page_address(page) + offset;
787         uaddr = (unsigned long)vaddr;
788         npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
789 
790         if (tbl) {
791                 align = 0;
792                 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
793                     ((unsigned long)vaddr & ~PAGE_MASK) == 0)
794                         align = PAGE_SHIFT - tbl->it_page_shift;
795 
796                 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
797                                          mask >> tbl->it_page_shift, align,
798                                          attrs);
799                 if (dma_handle == IOMMU_MAPPING_ERROR) {
800                         if (!(attrs & DMA_ATTR_NO_WARN) &&
801                             printk_ratelimit())  {
802                                 dev_info(dev, "iommu_alloc failed, tbl %p "
803                                          "vaddr %p npages %d\n", tbl, vaddr,
804                                          npages);
805                         }
806                 } else
807                         dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
808         }
809 
810         return dma_handle;
811 }
812 
813 void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
814                       size_t size, enum dma_data_direction direction,
815                       unsigned long attrs)
816 {
817         unsigned int npages;
818 
819         BUG_ON(direction == DMA_NONE);
820 
821         if (tbl) {
822                 npages = iommu_num_pages(dma_handle, size,
823                                          IOMMU_PAGE_SIZE(tbl));
824                 iommu_free(tbl, dma_handle, npages);
825         }
826 }
827 
828 /* Allocates a contiguous real buffer and creates mappings over it.
829  * Returns the virtual address of the buffer and sets dma_handle
830  * to the dma address (mapping) of the first page.
831  */
832 void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
833                            size_t size, dma_addr_t *dma_handle,
834                            unsigned long mask, gfp_t flag, int node)
835 {
836         void *ret = NULL;
837         dma_addr_t mapping;
838         unsigned int order;
839         unsigned int nio_pages, io_order;
840         struct page *page;
841 
842         size = PAGE_ALIGN(size);
843         order = get_order(size);
844 
845         /*
846          * Client asked for way too much space.  This is checked later
847          * anyway.  It is easier to debug here for the drivers than in
848          * the tce tables.
849          */
850         if (order >= IOMAP_MAX_ORDER) {
851                 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
852                          size);
853                 return NULL;
854         }
855 
856         if (!tbl)
857                 return NULL;
858 
859         /* Alloc enough pages (and possibly more) */
860         page = alloc_pages_node(node, flag, order);
861         if (!page)
862                 return NULL;
863         ret = page_address(page);
864         memset(ret, 0, size);
865 
866         /* Set up tces to cover the allocated range */
867         nio_pages = size >> tbl->it_page_shift;
868         io_order = get_iommu_order(size, tbl);
869         mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
870                               mask >> tbl->it_page_shift, io_order, 0);
871         if (mapping == IOMMU_MAPPING_ERROR) {
872                 free_pages((unsigned long)ret, order);
873                 return NULL;
874         }
875         *dma_handle = mapping;
876         return ret;
877 }
878 
879 void iommu_free_coherent(struct iommu_table *tbl, size_t size,
880                          void *vaddr, dma_addr_t dma_handle)
881 {
882         if (tbl) {
883                 unsigned int nio_pages;
884 
885                 size = PAGE_ALIGN(size);
886                 nio_pages = size >> tbl->it_page_shift;
887                 iommu_free(tbl, dma_handle, nio_pages);
888                 size = PAGE_ALIGN(size);
889                 free_pages((unsigned long)vaddr, get_order(size));
890         }
891 }
892 
893 unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
894 {
895         switch (dir) {
896         case DMA_BIDIRECTIONAL:
897                 return TCE_PCI_READ | TCE_PCI_WRITE;
898         case DMA_FROM_DEVICE:
899                 return TCE_PCI_WRITE;
900         case DMA_TO_DEVICE:
901                 return TCE_PCI_READ;
902         default:
903                 return 0;
904         }
905 }
906 EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
907 
908 #ifdef CONFIG_IOMMU_API
909 /*
910  * SPAPR TCE API
911  */
912 static void group_release(void *iommu_data)
913 {
914         struct iommu_table_group *table_group = iommu_data;
915 
916         table_group->group = NULL;
917 }
918 
919 void iommu_register_group(struct iommu_table_group *table_group,
920                 int pci_domain_number, unsigned long pe_num)
921 {
922         struct iommu_group *grp;
923         char *name;
924 
925         grp = iommu_group_alloc();
926         if (IS_ERR(grp)) {
927                 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
928                                 PTR_ERR(grp));
929                 return;
930         }
931         table_group->group = grp;
932         iommu_group_set_iommudata(grp, table_group, group_release);
933         name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
934                         pci_domain_number, pe_num);
935         if (!name)
936                 return;
937         iommu_group_set_name(grp, name);
938         kfree(name);
939 }
940 
941 enum dma_data_direction iommu_tce_direction(unsigned long tce)
942 {
943         if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
944                 return DMA_BIDIRECTIONAL;
945         else if (tce & TCE_PCI_READ)
946                 return DMA_TO_DEVICE;
947         else if (tce & TCE_PCI_WRITE)
948                 return DMA_FROM_DEVICE;
949         else
950                 return DMA_NONE;
951 }
952 EXPORT_SYMBOL_GPL(iommu_tce_direction);
953 
954 void iommu_flush_tce(struct iommu_table *tbl)
955 {
956         /* Flush/invalidate TLB caches if necessary */
957         if (tbl->it_ops->flush)
958                 tbl->it_ops->flush(tbl);
959 
960         /* Make sure updates are seen by hardware */
961         mb();
962 }
963 EXPORT_SYMBOL_GPL(iommu_flush_tce);
964 
965 int iommu_tce_check_ioba(unsigned long page_shift,
966                 unsigned long offset, unsigned long size,
967                 unsigned long ioba, unsigned long npages)
968 {
969         unsigned long mask = (1UL << page_shift) - 1;
970 
971         if (ioba & mask)
972                 return -EINVAL;
973 
974         ioba >>= page_shift;
975         if (ioba < offset)
976                 return -EINVAL;
977 
978         if ((ioba + 1) > (offset + size))
979                 return -EINVAL;
980 
981         return 0;
982 }
983 EXPORT_SYMBOL_GPL(iommu_tce_check_ioba);
984 
985 int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa)
986 {
987         unsigned long mask = (1UL << page_shift) - 1;
988 
989         if (gpa & mask)
990                 return -EINVAL;
991 
992         return 0;
993 }
994 EXPORT_SYMBOL_GPL(iommu_tce_check_gpa);
995 
996 long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
997                 unsigned long *hpa, enum dma_data_direction *direction)
998 {
999         long ret;
1000 
1001         ret = tbl->it_ops->exchange(tbl, entry, hpa, direction);
1002 
1003         if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1004                         (*direction == DMA_BIDIRECTIONAL)))
1005                 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
1006 
1007         /* if (unlikely(ret))
1008                 pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
1009                         __func__, hwaddr, entry << tbl->it_page_shift,
1010                                 hwaddr, ret); */
1011 
1012         return ret;
1013 }
1014 EXPORT_SYMBOL_GPL(iommu_tce_xchg);
1015 
1016 #ifdef CONFIG_PPC_BOOK3S_64
1017 long iommu_tce_xchg_rm(struct iommu_table *tbl, unsigned long entry,
1018                 unsigned long *hpa, enum dma_data_direction *direction)
1019 {
1020         long ret;
1021 
1022         ret = tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
1023 
1024         if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1025                         (*direction == DMA_BIDIRECTIONAL))) {
1026                 struct page *pg = realmode_pfn_to_page(*hpa >> PAGE_SHIFT);
1027 
1028                 if (likely(pg)) {
1029                         SetPageDirty(pg);
1030                 } else {
1031                         tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
1032                         ret = -EFAULT;
1033                 }
1034         }
1035 
1036         return ret;
1037 }
1038 EXPORT_SYMBOL_GPL(iommu_tce_xchg_rm);
1039 #endif
1040 
1041 int iommu_take_ownership(struct iommu_table *tbl)
1042 {
1043         unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1044         int ret = 0;
1045 
1046         /*
1047          * VFIO does not control TCE entries allocation and the guest
1048          * can write new TCEs on top of existing ones so iommu_tce_build()
1049          * must be able to release old pages. This functionality
1050          * requires exchange() callback defined so if it is not
1051          * implemented, we disallow taking ownership over the table.
1052          */
1053         if (!tbl->it_ops->exchange)
1054                 return -EINVAL;
1055 
1056         spin_lock_irqsave(&tbl->large_pool.lock, flags);
1057         for (i = 0; i < tbl->nr_pools; i++)
1058                 spin_lock(&tbl->pools[i].lock);
1059 
1060         if (tbl->it_offset == 0)
1061                 clear_bit(0, tbl->it_map);
1062 
1063         if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1064                 pr_err("iommu_tce: it_map is not empty");
1065                 ret = -EBUSY;
1066                 /* Restore bit#0 set by iommu_init_table() */
1067                 if (tbl->it_offset == 0)
1068                         set_bit(0, tbl->it_map);
1069         } else {
1070                 memset(tbl->it_map, 0xff, sz);
1071         }
1072 
1073         for (i = 0; i < tbl->nr_pools; i++)
1074                 spin_unlock(&tbl->pools[i].lock);
1075         spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1076 
1077         return ret;
1078 }
1079 EXPORT_SYMBOL_GPL(iommu_take_ownership);
1080 
1081 void iommu_release_ownership(struct iommu_table *tbl)
1082 {
1083         unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1084 
1085         spin_lock_irqsave(&tbl->large_pool.lock, flags);
1086         for (i = 0; i < tbl->nr_pools; i++)
1087                 spin_lock(&tbl->pools[i].lock);
1088 
1089         memset(tbl->it_map, 0, sz);
1090 
1091         /* Restore bit#0 set by iommu_init_table() */
1092         if (tbl->it_offset == 0)
1093                 set_bit(0, tbl->it_map);
1094 
1095         for (i = 0; i < tbl->nr_pools; i++)
1096                 spin_unlock(&tbl->pools[i].lock);
1097         spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1098 }
1099 EXPORT_SYMBOL_GPL(iommu_release_ownership);
1100 
1101 int iommu_add_device(struct device *dev)
1102 {
1103         struct iommu_table *tbl;
1104         struct iommu_table_group_link *tgl;
1105 
1106         /*
1107          * The sysfs entries should be populated before
1108          * binding IOMMU group. If sysfs entries isn't
1109          * ready, we simply bail.
1110          */
1111         if (!device_is_registered(dev))
1112                 return -ENOENT;
1113 
1114         if (dev->iommu_group) {
1115                 pr_debug("%s: Skipping device %s with iommu group %d\n",
1116                          __func__, dev_name(dev),
1117                          iommu_group_id(dev->iommu_group));
1118                 return -EBUSY;
1119         }
1120 
1121         tbl = get_iommu_table_base(dev);
1122         if (!tbl) {
1123                 pr_debug("%s: Skipping device %s with no tbl\n",
1124                          __func__, dev_name(dev));
1125                 return 0;
1126         }
1127 
1128         tgl = list_first_entry_or_null(&tbl->it_group_list,
1129                         struct iommu_table_group_link, next);
1130         if (!tgl) {
1131                 pr_debug("%s: Skipping device %s with no group\n",
1132                          __func__, dev_name(dev));
1133                 return 0;
1134         }
1135         pr_debug("%s: Adding %s to iommu group %d\n",
1136                  __func__, dev_name(dev),
1137                  iommu_group_id(tgl->table_group->group));
1138 
1139         if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
1140                 pr_err("%s: Invalid IOMMU page size %lx (%lx) on %s\n",
1141                        __func__, IOMMU_PAGE_SIZE(tbl),
1142                        PAGE_SIZE, dev_name(dev));
1143                 return -EINVAL;
1144         }
1145 
1146         return iommu_group_add_device(tgl->table_group->group, dev);
1147 }
1148 EXPORT_SYMBOL_GPL(iommu_add_device);
1149 
1150 void iommu_del_device(struct device *dev)
1151 {
1152         /*
1153          * Some devices might not have IOMMU table and group
1154          * and we needn't detach them from the associated
1155          * IOMMU groups
1156          */
1157         if (!dev->iommu_group) {
1158                 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1159                          dev_name(dev));
1160                 return;
1161         }
1162 
1163         iommu_group_remove_device(dev);
1164 }
1165 EXPORT_SYMBOL_GPL(iommu_del_device);
1166 
1167 static int tce_iommu_bus_notifier(struct notifier_block *nb,
1168                 unsigned long action, void *data)
1169 {
1170         struct device *dev = data;
1171 
1172         switch (action) {
1173         case BUS_NOTIFY_ADD_DEVICE:
1174                 return iommu_add_device(dev);
1175         case BUS_NOTIFY_DEL_DEVICE:
1176                 if (dev->iommu_group)
1177                         iommu_del_device(dev);
1178                 return 0;
1179         default:
1180                 return 0;
1181         }
1182 }
1183 
1184 static struct notifier_block tce_iommu_bus_nb = {
1185         .notifier_call = tce_iommu_bus_notifier,
1186 };
1187 
1188 int __init tce_iommu_bus_notifier_init(void)
1189 {
1190         bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
1191         return 0;
1192 }
1193 #endif /* CONFIG_IOMMU_API */
1194 

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