~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/powerpc/kernel/iommu.c

Version: ~ [ linux-5.8 ] ~ [ linux-5.7.12 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.55 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.136 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.191 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.232 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.232 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  4  * 
  5  * Rewrite, cleanup, new allocation schemes, virtual merging: 
  6  * Copyright (C) 2004 Olof Johansson, IBM Corporation
  7  *               and  Ben. Herrenschmidt, IBM Corporation
  8  *
  9  * Dynamic DMA mapping support, bus-independent parts.
 10  */
 11 
 12 
 13 #include <linux/init.h>
 14 #include <linux/types.h>
 15 #include <linux/slab.h>
 16 #include <linux/mm.h>
 17 #include <linux/spinlock.h>
 18 #include <linux/string.h>
 19 #include <linux/dma-mapping.h>
 20 #include <linux/bitmap.h>
 21 #include <linux/iommu-helper.h>
 22 #include <linux/crash_dump.h>
 23 #include <linux/hash.h>
 24 #include <linux/fault-inject.h>
 25 #include <linux/pci.h>
 26 #include <linux/iommu.h>
 27 #include <linux/sched.h>
 28 #include <asm/io.h>
 29 #include <asm/prom.h>
 30 #include <asm/iommu.h>
 31 #include <asm/pci-bridge.h>
 32 #include <asm/machdep.h>
 33 #include <asm/kdump.h>
 34 #include <asm/fadump.h>
 35 #include <asm/vio.h>
 36 #include <asm/tce.h>
 37 #include <asm/mmu_context.h>
 38 
 39 #define DBG(...)
 40 
 41 static int novmerge;
 42 
 43 static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
 44 
 45 static int __init setup_iommu(char *str)
 46 {
 47         if (!strcmp(str, "novmerge"))
 48                 novmerge = 1;
 49         else if (!strcmp(str, "vmerge"))
 50                 novmerge = 0;
 51         return 1;
 52 }
 53 
 54 __setup("iommu=", setup_iommu);
 55 
 56 static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
 57 
 58 /*
 59  * We precalculate the hash to avoid doing it on every allocation.
 60  *
 61  * The hash is important to spread CPUs across all the pools. For example,
 62  * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
 63  * with 4 pools all primary threads would map to the same pool.
 64  */
 65 static int __init setup_iommu_pool_hash(void)
 66 {
 67         unsigned int i;
 68 
 69         for_each_possible_cpu(i)
 70                 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
 71 
 72         return 0;
 73 }
 74 subsys_initcall(setup_iommu_pool_hash);
 75 
 76 #ifdef CONFIG_FAIL_IOMMU
 77 
 78 static DECLARE_FAULT_ATTR(fail_iommu);
 79 
 80 static int __init setup_fail_iommu(char *str)
 81 {
 82         return setup_fault_attr(&fail_iommu, str);
 83 }
 84 __setup("fail_iommu=", setup_fail_iommu);
 85 
 86 static bool should_fail_iommu(struct device *dev)
 87 {
 88         return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
 89 }
 90 
 91 static int __init fail_iommu_debugfs(void)
 92 {
 93         struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
 94                                                        NULL, &fail_iommu);
 95 
 96         return PTR_ERR_OR_ZERO(dir);
 97 }
 98 late_initcall(fail_iommu_debugfs);
 99 
100 static ssize_t fail_iommu_show(struct device *dev,
101                                struct device_attribute *attr, char *buf)
102 {
103         return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
104 }
105 
106 static ssize_t fail_iommu_store(struct device *dev,
107                                 struct device_attribute *attr, const char *buf,
108                                 size_t count)
109 {
110         int i;
111 
112         if (count > 0 && sscanf(buf, "%d", &i) > 0)
113                 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
114 
115         return count;
116 }
117 
118 static DEVICE_ATTR_RW(fail_iommu);
119 
120 static int fail_iommu_bus_notify(struct notifier_block *nb,
121                                  unsigned long action, void *data)
122 {
123         struct device *dev = data;
124 
125         if (action == BUS_NOTIFY_ADD_DEVICE) {
126                 if (device_create_file(dev, &dev_attr_fail_iommu))
127                         pr_warn("Unable to create IOMMU fault injection sysfs "
128                                 "entries\n");
129         } else if (action == BUS_NOTIFY_DEL_DEVICE) {
130                 device_remove_file(dev, &dev_attr_fail_iommu);
131         }
132 
133         return 0;
134 }
135 
136 static struct notifier_block fail_iommu_bus_notifier = {
137         .notifier_call = fail_iommu_bus_notify
138 };
139 
140 static int __init fail_iommu_setup(void)
141 {
142 #ifdef CONFIG_PCI
143         bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
144 #endif
145 #ifdef CONFIG_IBMVIO
146         bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
147 #endif
148 
149         return 0;
150 }
151 /*
152  * Must execute after PCI and VIO subsystem have initialised but before
153  * devices are probed.
154  */
155 arch_initcall(fail_iommu_setup);
156 #else
157 static inline bool should_fail_iommu(struct device *dev)
158 {
159         return false;
160 }
161 #endif
162 
163 static unsigned long iommu_range_alloc(struct device *dev,
164                                        struct iommu_table *tbl,
165                                        unsigned long npages,
166                                        unsigned long *handle,
167                                        unsigned long mask,
168                                        unsigned int align_order)
169 { 
170         unsigned long n, end, start;
171         unsigned long limit;
172         int largealloc = npages > 15;
173         int pass = 0;
174         unsigned long align_mask;
175         unsigned long boundary_size;
176         unsigned long flags;
177         unsigned int pool_nr;
178         struct iommu_pool *pool;
179 
180         align_mask = (1ull << align_order) - 1;
181 
182         /* This allocator was derived from x86_64's bit string search */
183 
184         /* Sanity check */
185         if (unlikely(npages == 0)) {
186                 if (printk_ratelimit())
187                         WARN_ON(1);
188                 return DMA_MAPPING_ERROR;
189         }
190 
191         if (should_fail_iommu(dev))
192                 return DMA_MAPPING_ERROR;
193 
194         /*
195          * We don't need to disable preemption here because any CPU can
196          * safely use any IOMMU pool.
197          */
198         pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
199 
200         if (largealloc)
201                 pool = &(tbl->large_pool);
202         else
203                 pool = &(tbl->pools[pool_nr]);
204 
205         spin_lock_irqsave(&(pool->lock), flags);
206 
207 again:
208         if ((pass == 0) && handle && *handle &&
209             (*handle >= pool->start) && (*handle < pool->end))
210                 start = *handle;
211         else
212                 start = pool->hint;
213 
214         limit = pool->end;
215 
216         /* The case below can happen if we have a small segment appended
217          * to a large, or when the previous alloc was at the very end of
218          * the available space. If so, go back to the initial start.
219          */
220         if (start >= limit)
221                 start = pool->start;
222 
223         if (limit + tbl->it_offset > mask) {
224                 limit = mask - tbl->it_offset + 1;
225                 /* If we're constrained on address range, first try
226                  * at the masked hint to avoid O(n) search complexity,
227                  * but on second pass, start at 0 in pool 0.
228                  */
229                 if ((start & mask) >= limit || pass > 0) {
230                         spin_unlock(&(pool->lock));
231                         pool = &(tbl->pools[0]);
232                         spin_lock(&(pool->lock));
233                         start = pool->start;
234                 } else {
235                         start &= mask;
236                 }
237         }
238 
239         if (dev)
240                 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
241                                       1 << tbl->it_page_shift);
242         else
243                 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
244         /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
245 
246         n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
247                              boundary_size >> tbl->it_page_shift, align_mask);
248         if (n == -1) {
249                 if (likely(pass == 0)) {
250                         /* First try the pool from the start */
251                         pool->hint = pool->start;
252                         pass++;
253                         goto again;
254 
255                 } else if (pass <= tbl->nr_pools) {
256                         /* Now try scanning all the other pools */
257                         spin_unlock(&(pool->lock));
258                         pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
259                         pool = &tbl->pools[pool_nr];
260                         spin_lock(&(pool->lock));
261                         pool->hint = pool->start;
262                         pass++;
263                         goto again;
264 
265                 } else {
266                         /* Give up */
267                         spin_unlock_irqrestore(&(pool->lock), flags);
268                         return DMA_MAPPING_ERROR;
269                 }
270         }
271 
272         end = n + npages;
273 
274         /* Bump the hint to a new block for small allocs. */
275         if (largealloc) {
276                 /* Don't bump to new block to avoid fragmentation */
277                 pool->hint = end;
278         } else {
279                 /* Overflow will be taken care of at the next allocation */
280                 pool->hint = (end + tbl->it_blocksize - 1) &
281                                 ~(tbl->it_blocksize - 1);
282         }
283 
284         /* Update handle for SG allocations */
285         if (handle)
286                 *handle = end;
287 
288         spin_unlock_irqrestore(&(pool->lock), flags);
289 
290         return n;
291 }
292 
293 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
294                               void *page, unsigned int npages,
295                               enum dma_data_direction direction,
296                               unsigned long mask, unsigned int align_order,
297                               unsigned long attrs)
298 {
299         unsigned long entry;
300         dma_addr_t ret = DMA_MAPPING_ERROR;
301         int build_fail;
302 
303         entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
304 
305         if (unlikely(entry == DMA_MAPPING_ERROR))
306                 return DMA_MAPPING_ERROR;
307 
308         entry += tbl->it_offset;        /* Offset into real TCE table */
309         ret = entry << tbl->it_page_shift;      /* Set the return dma address */
310 
311         /* Put the TCEs in the HW table */
312         build_fail = tbl->it_ops->set(tbl, entry, npages,
313                                       (unsigned long)page &
314                                       IOMMU_PAGE_MASK(tbl), direction, attrs);
315 
316         /* tbl->it_ops->set() only returns non-zero for transient errors.
317          * Clean up the table bitmap in this case and return
318          * DMA_MAPPING_ERROR. For all other errors the functionality is
319          * not altered.
320          */
321         if (unlikely(build_fail)) {
322                 __iommu_free(tbl, ret, npages);
323                 return DMA_MAPPING_ERROR;
324         }
325 
326         /* Flush/invalidate TLB caches if necessary */
327         if (tbl->it_ops->flush)
328                 tbl->it_ops->flush(tbl);
329 
330         /* Make sure updates are seen by hardware */
331         mb();
332 
333         return ret;
334 }
335 
336 static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
337                              unsigned int npages)
338 {
339         unsigned long entry, free_entry;
340 
341         entry = dma_addr >> tbl->it_page_shift;
342         free_entry = entry - tbl->it_offset;
343 
344         if (((free_entry + npages) > tbl->it_size) ||
345             (entry < tbl->it_offset)) {
346                 if (printk_ratelimit()) {
347                         printk(KERN_INFO "iommu_free: invalid entry\n");
348                         printk(KERN_INFO "\tentry     = 0x%lx\n", entry); 
349                         printk(KERN_INFO "\tdma_addr  = 0x%llx\n", (u64)dma_addr);
350                         printk(KERN_INFO "\tTable     = 0x%llx\n", (u64)tbl);
351                         printk(KERN_INFO "\tbus#      = 0x%llx\n", (u64)tbl->it_busno);
352                         printk(KERN_INFO "\tsize      = 0x%llx\n", (u64)tbl->it_size);
353                         printk(KERN_INFO "\tstartOff  = 0x%llx\n", (u64)tbl->it_offset);
354                         printk(KERN_INFO "\tindex     = 0x%llx\n", (u64)tbl->it_index);
355                         WARN_ON(1);
356                 }
357 
358                 return false;
359         }
360 
361         return true;
362 }
363 
364 static struct iommu_pool *get_pool(struct iommu_table *tbl,
365                                    unsigned long entry)
366 {
367         struct iommu_pool *p;
368         unsigned long largepool_start = tbl->large_pool.start;
369 
370         /* The large pool is the last pool at the top of the table */
371         if (entry >= largepool_start) {
372                 p = &tbl->large_pool;
373         } else {
374                 unsigned int pool_nr = entry / tbl->poolsize;
375 
376                 BUG_ON(pool_nr > tbl->nr_pools);
377                 p = &tbl->pools[pool_nr];
378         }
379 
380         return p;
381 }
382 
383 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
384                          unsigned int npages)
385 {
386         unsigned long entry, free_entry;
387         unsigned long flags;
388         struct iommu_pool *pool;
389 
390         entry = dma_addr >> tbl->it_page_shift;
391         free_entry = entry - tbl->it_offset;
392 
393         pool = get_pool(tbl, free_entry);
394 
395         if (!iommu_free_check(tbl, dma_addr, npages))
396                 return;
397 
398         tbl->it_ops->clear(tbl, entry, npages);
399 
400         spin_lock_irqsave(&(pool->lock), flags);
401         bitmap_clear(tbl->it_map, free_entry, npages);
402         spin_unlock_irqrestore(&(pool->lock), flags);
403 }
404 
405 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
406                 unsigned int npages)
407 {
408         __iommu_free(tbl, dma_addr, npages);
409 
410         /* Make sure TLB cache is flushed if the HW needs it. We do
411          * not do an mb() here on purpose, it is not needed on any of
412          * the current platforms.
413          */
414         if (tbl->it_ops->flush)
415                 tbl->it_ops->flush(tbl);
416 }
417 
418 int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
419                      struct scatterlist *sglist, int nelems,
420                      unsigned long mask, enum dma_data_direction direction,
421                      unsigned long attrs)
422 {
423         dma_addr_t dma_next = 0, dma_addr;
424         struct scatterlist *s, *outs, *segstart;
425         int outcount, incount, i, build_fail = 0;
426         unsigned int align;
427         unsigned long handle;
428         unsigned int max_seg_size;
429 
430         BUG_ON(direction == DMA_NONE);
431 
432         if ((nelems == 0) || !tbl)
433                 return 0;
434 
435         outs = s = segstart = &sglist[0];
436         outcount = 1;
437         incount = nelems;
438         handle = 0;
439 
440         /* Init first segment length for backout at failure */
441         outs->dma_length = 0;
442 
443         DBG("sg mapping %d elements:\n", nelems);
444 
445         max_seg_size = dma_get_max_seg_size(dev);
446         for_each_sg(sglist, s, nelems, i) {
447                 unsigned long vaddr, npages, entry, slen;
448 
449                 slen = s->length;
450                 /* Sanity check */
451                 if (slen == 0) {
452                         dma_next = 0;
453                         continue;
454                 }
455                 /* Allocate iommu entries for that segment */
456                 vaddr = (unsigned long) sg_virt(s);
457                 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
458                 align = 0;
459                 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
460                     (vaddr & ~PAGE_MASK) == 0)
461                         align = PAGE_SHIFT - tbl->it_page_shift;
462                 entry = iommu_range_alloc(dev, tbl, npages, &handle,
463                                           mask >> tbl->it_page_shift, align);
464 
465                 DBG("  - vaddr: %lx, size: %lx\n", vaddr, slen);
466 
467                 /* Handle failure */
468                 if (unlikely(entry == DMA_MAPPING_ERROR)) {
469                         if (!(attrs & DMA_ATTR_NO_WARN) &&
470                             printk_ratelimit())
471                                 dev_info(dev, "iommu_alloc failed, tbl %p "
472                                          "vaddr %lx npages %lu\n", tbl, vaddr,
473                                          npages);
474                         goto failure;
475                 }
476 
477                 /* Convert entry to a dma_addr_t */
478                 entry += tbl->it_offset;
479                 dma_addr = entry << tbl->it_page_shift;
480                 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
481 
482                 DBG("  - %lu pages, entry: %lx, dma_addr: %lx\n",
483                             npages, entry, dma_addr);
484 
485                 /* Insert into HW table */
486                 build_fail = tbl->it_ops->set(tbl, entry, npages,
487                                               vaddr & IOMMU_PAGE_MASK(tbl),
488                                               direction, attrs);
489                 if(unlikely(build_fail))
490                         goto failure;
491 
492                 /* If we are in an open segment, try merging */
493                 if (segstart != s) {
494                         DBG("  - trying merge...\n");
495                         /* We cannot merge if:
496                          * - allocated dma_addr isn't contiguous to previous allocation
497                          */
498                         if (novmerge || (dma_addr != dma_next) ||
499                             (outs->dma_length + s->length > max_seg_size)) {
500                                 /* Can't merge: create a new segment */
501                                 segstart = s;
502                                 outcount++;
503                                 outs = sg_next(outs);
504                                 DBG("    can't merge, new segment.\n");
505                         } else {
506                                 outs->dma_length += s->length;
507                                 DBG("    merged, new len: %ux\n", outs->dma_length);
508                         }
509                 }
510 
511                 if (segstart == s) {
512                         /* This is a new segment, fill entries */
513                         DBG("  - filling new segment.\n");
514                         outs->dma_address = dma_addr;
515                         outs->dma_length = slen;
516                 }
517 
518                 /* Calculate next page pointer for contiguous check */
519                 dma_next = dma_addr + slen;
520 
521                 DBG("  - dma next is: %lx\n", dma_next);
522         }
523 
524         /* Flush/invalidate TLB caches if necessary */
525         if (tbl->it_ops->flush)
526                 tbl->it_ops->flush(tbl);
527 
528         DBG("mapped %d elements:\n", outcount);
529 
530         /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
531          * next entry of the sglist if we didn't fill the list completely
532          */
533         if (outcount < incount) {
534                 outs = sg_next(outs);
535                 outs->dma_address = DMA_MAPPING_ERROR;
536                 outs->dma_length = 0;
537         }
538 
539         /* Make sure updates are seen by hardware */
540         mb();
541 
542         return outcount;
543 
544  failure:
545         for_each_sg(sglist, s, nelems, i) {
546                 if (s->dma_length != 0) {
547                         unsigned long vaddr, npages;
548 
549                         vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
550                         npages = iommu_num_pages(s->dma_address, s->dma_length,
551                                                  IOMMU_PAGE_SIZE(tbl));
552                         __iommu_free(tbl, vaddr, npages);
553                         s->dma_address = DMA_MAPPING_ERROR;
554                         s->dma_length = 0;
555                 }
556                 if (s == outs)
557                         break;
558         }
559         return 0;
560 }
561 
562 
563 void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
564                         int nelems, enum dma_data_direction direction,
565                         unsigned long attrs)
566 {
567         struct scatterlist *sg;
568 
569         BUG_ON(direction == DMA_NONE);
570 
571         if (!tbl)
572                 return;
573 
574         sg = sglist;
575         while (nelems--) {
576                 unsigned int npages;
577                 dma_addr_t dma_handle = sg->dma_address;
578 
579                 if (sg->dma_length == 0)
580                         break;
581                 npages = iommu_num_pages(dma_handle, sg->dma_length,
582                                          IOMMU_PAGE_SIZE(tbl));
583                 __iommu_free(tbl, dma_handle, npages);
584                 sg = sg_next(sg);
585         }
586 
587         /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
588          * do not do an mb() here, the affected platforms do not need it
589          * when freeing.
590          */
591         if (tbl->it_ops->flush)
592                 tbl->it_ops->flush(tbl);
593 }
594 
595 static void iommu_table_clear(struct iommu_table *tbl)
596 {
597         /*
598          * In case of firmware assisted dump system goes through clean
599          * reboot process at the time of system crash. Hence it's safe to
600          * clear the TCE entries if firmware assisted dump is active.
601          */
602         if (!is_kdump_kernel() || is_fadump_active()) {
603                 /* Clear the table in case firmware left allocations in it */
604                 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
605                 return;
606         }
607 
608 #ifdef CONFIG_CRASH_DUMP
609         if (tbl->it_ops->get) {
610                 unsigned long index, tceval, tcecount = 0;
611 
612                 /* Reserve the existing mappings left by the first kernel. */
613                 for (index = 0; index < tbl->it_size; index++) {
614                         tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
615                         /*
616                          * Freed TCE entry contains 0x7fffffffffffffff on JS20
617                          */
618                         if (tceval && (tceval != 0x7fffffffffffffffUL)) {
619                                 __set_bit(index, tbl->it_map);
620                                 tcecount++;
621                         }
622                 }
623 
624                 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
625                         printk(KERN_WARNING "TCE table is full; freeing ");
626                         printk(KERN_WARNING "%d entries for the kdump boot\n",
627                                 KDUMP_MIN_TCE_ENTRIES);
628                         for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
629                                 index < tbl->it_size; index++)
630                                 __clear_bit(index, tbl->it_map);
631                 }
632         }
633 #endif
634 }
635 
636 /*
637  * Build a iommu_table structure.  This contains a bit map which
638  * is used to manage allocation of the tce space.
639  */
640 struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
641 {
642         unsigned long sz;
643         static int welcomed = 0;
644         struct page *page;
645         unsigned int i;
646         struct iommu_pool *p;
647 
648         BUG_ON(!tbl->it_ops);
649 
650         /* number of bytes needed for the bitmap */
651         sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
652 
653         page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
654         if (!page)
655                 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
656         tbl->it_map = page_address(page);
657         memset(tbl->it_map, 0, sz);
658 
659         /*
660          * Reserve page 0 so it will not be used for any mappings.
661          * This avoids buggy drivers that consider page 0 to be invalid
662          * to crash the machine or even lose data.
663          */
664         if (tbl->it_offset == 0)
665                 set_bit(0, tbl->it_map);
666 
667         /* We only split the IOMMU table if we have 1GB or more of space */
668         if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
669                 tbl->nr_pools = IOMMU_NR_POOLS;
670         else
671                 tbl->nr_pools = 1;
672 
673         /* We reserve the top 1/4 of the table for large allocations */
674         tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
675 
676         for (i = 0; i < tbl->nr_pools; i++) {
677                 p = &tbl->pools[i];
678                 spin_lock_init(&(p->lock));
679                 p->start = tbl->poolsize * i;
680                 p->hint = p->start;
681                 p->end = p->start + tbl->poolsize;
682         }
683 
684         p = &tbl->large_pool;
685         spin_lock_init(&(p->lock));
686         p->start = tbl->poolsize * i;
687         p->hint = p->start;
688         p->end = tbl->it_size;
689 
690         iommu_table_clear(tbl);
691 
692         if (!welcomed) {
693                 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
694                        novmerge ? "disabled" : "enabled");
695                 welcomed = 1;
696         }
697 
698         return tbl;
699 }
700 
701 static void iommu_table_free(struct kref *kref)
702 {
703         unsigned long bitmap_sz;
704         unsigned int order;
705         struct iommu_table *tbl;
706 
707         tbl = container_of(kref, struct iommu_table, it_kref);
708 
709         if (tbl->it_ops->free)
710                 tbl->it_ops->free(tbl);
711 
712         if (!tbl->it_map) {
713                 kfree(tbl);
714                 return;
715         }
716 
717         /*
718          * In case we have reserved the first bit, we should not emit
719          * the warning below.
720          */
721         if (tbl->it_offset == 0)
722                 clear_bit(0, tbl->it_map);
723 
724         /* verify that table contains no entries */
725         if (!bitmap_empty(tbl->it_map, tbl->it_size))
726                 pr_warn("%s: Unexpected TCEs\n", __func__);
727 
728         /* calculate bitmap size in bytes */
729         bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
730 
731         /* free bitmap */
732         order = get_order(bitmap_sz);
733         free_pages((unsigned long) tbl->it_map, order);
734 
735         /* free table */
736         kfree(tbl);
737 }
738 
739 struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl)
740 {
741         if (kref_get_unless_zero(&tbl->it_kref))
742                 return tbl;
743 
744         return NULL;
745 }
746 EXPORT_SYMBOL_GPL(iommu_tce_table_get);
747 
748 int iommu_tce_table_put(struct iommu_table *tbl)
749 {
750         if (WARN_ON(!tbl))
751                 return 0;
752 
753         return kref_put(&tbl->it_kref, iommu_table_free);
754 }
755 EXPORT_SYMBOL_GPL(iommu_tce_table_put);
756 
757 /* Creates TCEs for a user provided buffer.  The user buffer must be
758  * contiguous real kernel storage (not vmalloc).  The address passed here
759  * comprises a page address and offset into that page. The dma_addr_t
760  * returned will point to the same byte within the page as was passed in.
761  */
762 dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
763                           struct page *page, unsigned long offset, size_t size,
764                           unsigned long mask, enum dma_data_direction direction,
765                           unsigned long attrs)
766 {
767         dma_addr_t dma_handle = DMA_MAPPING_ERROR;
768         void *vaddr;
769         unsigned long uaddr;
770         unsigned int npages, align;
771 
772         BUG_ON(direction == DMA_NONE);
773 
774         vaddr = page_address(page) + offset;
775         uaddr = (unsigned long)vaddr;
776 
777         if (tbl) {
778                 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
779                 align = 0;
780                 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
781                     ((unsigned long)vaddr & ~PAGE_MASK) == 0)
782                         align = PAGE_SHIFT - tbl->it_page_shift;
783 
784                 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
785                                          mask >> tbl->it_page_shift, align,
786                                          attrs);
787                 if (dma_handle == DMA_MAPPING_ERROR) {
788                         if (!(attrs & DMA_ATTR_NO_WARN) &&
789                             printk_ratelimit())  {
790                                 dev_info(dev, "iommu_alloc failed, tbl %p "
791                                          "vaddr %p npages %d\n", tbl, vaddr,
792                                          npages);
793                         }
794                 } else
795                         dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
796         }
797 
798         return dma_handle;
799 }
800 
801 void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
802                       size_t size, enum dma_data_direction direction,
803                       unsigned long attrs)
804 {
805         unsigned int npages;
806 
807         BUG_ON(direction == DMA_NONE);
808 
809         if (tbl) {
810                 npages = iommu_num_pages(dma_handle, size,
811                                          IOMMU_PAGE_SIZE(tbl));
812                 iommu_free(tbl, dma_handle, npages);
813         }
814 }
815 
816 /* Allocates a contiguous real buffer and creates mappings over it.
817  * Returns the virtual address of the buffer and sets dma_handle
818  * to the dma address (mapping) of the first page.
819  */
820 void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
821                            size_t size, dma_addr_t *dma_handle,
822                            unsigned long mask, gfp_t flag, int node)
823 {
824         void *ret = NULL;
825         dma_addr_t mapping;
826         unsigned int order;
827         unsigned int nio_pages, io_order;
828         struct page *page;
829 
830         size = PAGE_ALIGN(size);
831         order = get_order(size);
832 
833         /*
834          * Client asked for way too much space.  This is checked later
835          * anyway.  It is easier to debug here for the drivers than in
836          * the tce tables.
837          */
838         if (order >= IOMAP_MAX_ORDER) {
839                 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
840                          size);
841                 return NULL;
842         }
843 
844         if (!tbl)
845                 return NULL;
846 
847         /* Alloc enough pages (and possibly more) */
848         page = alloc_pages_node(node, flag, order);
849         if (!page)
850                 return NULL;
851         ret = page_address(page);
852         memset(ret, 0, size);
853 
854         /* Set up tces to cover the allocated range */
855         nio_pages = size >> tbl->it_page_shift;
856         io_order = get_iommu_order(size, tbl);
857         mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
858                               mask >> tbl->it_page_shift, io_order, 0);
859         if (mapping == DMA_MAPPING_ERROR) {
860                 free_pages((unsigned long)ret, order);
861                 return NULL;
862         }
863         *dma_handle = mapping;
864         return ret;
865 }
866 
867 void iommu_free_coherent(struct iommu_table *tbl, size_t size,
868                          void *vaddr, dma_addr_t dma_handle)
869 {
870         if (tbl) {
871                 unsigned int nio_pages;
872 
873                 size = PAGE_ALIGN(size);
874                 nio_pages = size >> tbl->it_page_shift;
875                 iommu_free(tbl, dma_handle, nio_pages);
876                 size = PAGE_ALIGN(size);
877                 free_pages((unsigned long)vaddr, get_order(size));
878         }
879 }
880 
881 unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
882 {
883         switch (dir) {
884         case DMA_BIDIRECTIONAL:
885                 return TCE_PCI_READ | TCE_PCI_WRITE;
886         case DMA_FROM_DEVICE:
887                 return TCE_PCI_WRITE;
888         case DMA_TO_DEVICE:
889                 return TCE_PCI_READ;
890         default:
891                 return 0;
892         }
893 }
894 EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
895 
896 #ifdef CONFIG_IOMMU_API
897 /*
898  * SPAPR TCE API
899  */
900 static void group_release(void *iommu_data)
901 {
902         struct iommu_table_group *table_group = iommu_data;
903 
904         table_group->group = NULL;
905 }
906 
907 void iommu_register_group(struct iommu_table_group *table_group,
908                 int pci_domain_number, unsigned long pe_num)
909 {
910         struct iommu_group *grp;
911         char *name;
912 
913         grp = iommu_group_alloc();
914         if (IS_ERR(grp)) {
915                 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
916                                 PTR_ERR(grp));
917                 return;
918         }
919         table_group->group = grp;
920         iommu_group_set_iommudata(grp, table_group, group_release);
921         name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
922                         pci_domain_number, pe_num);
923         if (!name)
924                 return;
925         iommu_group_set_name(grp, name);
926         kfree(name);
927 }
928 
929 enum dma_data_direction iommu_tce_direction(unsigned long tce)
930 {
931         if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
932                 return DMA_BIDIRECTIONAL;
933         else if (tce & TCE_PCI_READ)
934                 return DMA_TO_DEVICE;
935         else if (tce & TCE_PCI_WRITE)
936                 return DMA_FROM_DEVICE;
937         else
938                 return DMA_NONE;
939 }
940 EXPORT_SYMBOL_GPL(iommu_tce_direction);
941 
942 void iommu_flush_tce(struct iommu_table *tbl)
943 {
944         /* Flush/invalidate TLB caches if necessary */
945         if (tbl->it_ops->flush)
946                 tbl->it_ops->flush(tbl);
947 
948         /* Make sure updates are seen by hardware */
949         mb();
950 }
951 EXPORT_SYMBOL_GPL(iommu_flush_tce);
952 
953 int iommu_tce_check_ioba(unsigned long page_shift,
954                 unsigned long offset, unsigned long size,
955                 unsigned long ioba, unsigned long npages)
956 {
957         unsigned long mask = (1UL << page_shift) - 1;
958 
959         if (ioba & mask)
960                 return -EINVAL;
961 
962         ioba >>= page_shift;
963         if (ioba < offset)
964                 return -EINVAL;
965 
966         if ((ioba + 1) > (offset + size))
967                 return -EINVAL;
968 
969         return 0;
970 }
971 EXPORT_SYMBOL_GPL(iommu_tce_check_ioba);
972 
973 int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa)
974 {
975         unsigned long mask = (1UL << page_shift) - 1;
976 
977         if (gpa & mask)
978                 return -EINVAL;
979 
980         return 0;
981 }
982 EXPORT_SYMBOL_GPL(iommu_tce_check_gpa);
983 
984 long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl,
985                 unsigned long entry, unsigned long *hpa,
986                 enum dma_data_direction *direction)
987 {
988         long ret;
989         unsigned long size = 0;
990 
991         ret = tbl->it_ops->exchange(tbl, entry, hpa, direction);
992 
993         if (!ret && ((*direction == DMA_FROM_DEVICE) ||
994                         (*direction == DMA_BIDIRECTIONAL)) &&
995                         !mm_iommu_is_devmem(mm, *hpa, tbl->it_page_shift,
996                                         &size))
997                 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
998 
999         /* if (unlikely(ret))
1000                 pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
1001                         __func__, hwaddr, entry << tbl->it_page_shift,
1002                                 hwaddr, ret); */
1003 
1004         return ret;
1005 }
1006 EXPORT_SYMBOL_GPL(iommu_tce_xchg);
1007 
1008 int iommu_take_ownership(struct iommu_table *tbl)
1009 {
1010         unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1011         int ret = 0;
1012 
1013         /*
1014          * VFIO does not control TCE entries allocation and the guest
1015          * can write new TCEs on top of existing ones so iommu_tce_build()
1016          * must be able to release old pages. This functionality
1017          * requires exchange() callback defined so if it is not
1018          * implemented, we disallow taking ownership over the table.
1019          */
1020         if (!tbl->it_ops->exchange)
1021                 return -EINVAL;
1022 
1023         spin_lock_irqsave(&tbl->large_pool.lock, flags);
1024         for (i = 0; i < tbl->nr_pools; i++)
1025                 spin_lock(&tbl->pools[i].lock);
1026 
1027         if (tbl->it_offset == 0)
1028                 clear_bit(0, tbl->it_map);
1029 
1030         if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1031                 pr_err("iommu_tce: it_map is not empty");
1032                 ret = -EBUSY;
1033                 /* Restore bit#0 set by iommu_init_table() */
1034                 if (tbl->it_offset == 0)
1035                         set_bit(0, tbl->it_map);
1036         } else {
1037                 memset(tbl->it_map, 0xff, sz);
1038         }
1039 
1040         for (i = 0; i < tbl->nr_pools; i++)
1041                 spin_unlock(&tbl->pools[i].lock);
1042         spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1043 
1044         return ret;
1045 }
1046 EXPORT_SYMBOL_GPL(iommu_take_ownership);
1047 
1048 void iommu_release_ownership(struct iommu_table *tbl)
1049 {
1050         unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1051 
1052         spin_lock_irqsave(&tbl->large_pool.lock, flags);
1053         for (i = 0; i < tbl->nr_pools; i++)
1054                 spin_lock(&tbl->pools[i].lock);
1055 
1056         memset(tbl->it_map, 0, sz);
1057 
1058         /* Restore bit#0 set by iommu_init_table() */
1059         if (tbl->it_offset == 0)
1060                 set_bit(0, tbl->it_map);
1061 
1062         for (i = 0; i < tbl->nr_pools; i++)
1063                 spin_unlock(&tbl->pools[i].lock);
1064         spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1065 }
1066 EXPORT_SYMBOL_GPL(iommu_release_ownership);
1067 
1068 int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
1069 {
1070         /*
1071          * The sysfs entries should be populated before
1072          * binding IOMMU group. If sysfs entries isn't
1073          * ready, we simply bail.
1074          */
1075         if (!device_is_registered(dev))
1076                 return -ENOENT;
1077 
1078         if (device_iommu_mapped(dev)) {
1079                 pr_debug("%s: Skipping device %s with iommu group %d\n",
1080                          __func__, dev_name(dev),
1081                          iommu_group_id(dev->iommu_group));
1082                 return -EBUSY;
1083         }
1084 
1085         pr_debug("%s: Adding %s to iommu group %d\n",
1086                  __func__, dev_name(dev),  iommu_group_id(table_group->group));
1087 
1088         return iommu_group_add_device(table_group->group, dev);
1089 }
1090 EXPORT_SYMBOL_GPL(iommu_add_device);
1091 
1092 void iommu_del_device(struct device *dev)
1093 {
1094         /*
1095          * Some devices might not have IOMMU table and group
1096          * and we needn't detach them from the associated
1097          * IOMMU groups
1098          */
1099         if (!device_iommu_mapped(dev)) {
1100                 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1101                          dev_name(dev));
1102                 return;
1103         }
1104 
1105         iommu_group_remove_device(dev);
1106 }
1107 EXPORT_SYMBOL_GPL(iommu_del_device);
1108 #endif /* CONFIG_IOMMU_API */
1109 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp