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TOMOYO Linux Cross Reference
Linux/arch/powerpc/kernel/pci-common.c

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  1 /*
  2  * Contains common pci routines for ALL ppc platform
  3  * (based on pci_32.c and pci_64.c)
  4  *
  5  * Port for PPC64 David Engebretsen, IBM Corp.
  6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
  7  *
  8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
  9  *   Rework, based on alpha PCI code.
 10  *
 11  * Common pmac/prep/chrp pci routines. -- Cort
 12  *
 13  * This program is free software; you can redistribute it and/or
 14  * modify it under the terms of the GNU General Public License
 15  * as published by the Free Software Foundation; either version
 16  * 2 of the License, or (at your option) any later version.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/pci.h>
 21 #include <linux/string.h>
 22 #include <linux/init.h>
 23 #include <linux/bootmem.h>
 24 #include <linux/export.h>
 25 #include <linux/of_address.h>
 26 #include <linux/of_pci.h>
 27 #include <linux/mm.h>
 28 #include <linux/list.h>
 29 #include <linux/syscalls.h>
 30 #include <linux/irq.h>
 31 #include <linux/vmalloc.h>
 32 #include <linux/slab.h>
 33 
 34 #include <asm/processor.h>
 35 #include <asm/io.h>
 36 #include <asm/prom.h>
 37 #include <asm/pci-bridge.h>
 38 #include <asm/byteorder.h>
 39 #include <asm/machdep.h>
 40 #include <asm/ppc-pci.h>
 41 #include <asm/firmware.h>
 42 #include <asm/eeh.h>
 43 
 44 static DEFINE_SPINLOCK(hose_spinlock);
 45 LIST_HEAD(hose_list);
 46 
 47 /* XXX kill that some day ... */
 48 static int global_phb_number;           /* Global phb counter */
 49 
 50 /* ISA Memory physical address */
 51 resource_size_t isa_mem_base;
 52 
 53 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
 54 unsigned int pci_flags = 0;
 55 
 56 
 57 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 58 
 59 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
 60 {
 61         pci_dma_ops = dma_ops;
 62 }
 63 
 64 struct dma_map_ops *get_pci_dma_ops(void)
 65 {
 66         return pci_dma_ops;
 67 }
 68 EXPORT_SYMBOL(get_pci_dma_ops);
 69 
 70 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
 71 {
 72         struct pci_controller *phb;
 73 
 74         phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
 75         if (phb == NULL)
 76                 return NULL;
 77         spin_lock(&hose_spinlock);
 78         phb->global_number = global_phb_number++;
 79         list_add_tail(&phb->list_node, &hose_list);
 80         spin_unlock(&hose_spinlock);
 81         phb->dn = dev;
 82         phb->is_dynamic = mem_init_done;
 83 #ifdef CONFIG_PPC64
 84         if (dev) {
 85                 int nid = of_node_to_nid(dev);
 86 
 87                 if (nid < 0 || !node_online(nid))
 88                         nid = -1;
 89 
 90                 PHB_SET_NODE(phb, nid);
 91         }
 92 #endif
 93         return phb;
 94 }
 95 
 96 void pcibios_free_controller(struct pci_controller *phb)
 97 {
 98         spin_lock(&hose_spinlock);
 99         list_del(&phb->list_node);
100         spin_unlock(&hose_spinlock);
101 
102         if (phb->is_dynamic)
103                 kfree(phb);
104 }
105 
106 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
107 {
108 #ifdef CONFIG_PPC64
109         return hose->pci_io_size;
110 #else
111         return resource_size(&hose->io_resource);
112 #endif
113 }
114 
115 int pcibios_vaddr_is_ioport(void __iomem *address)
116 {
117         int ret = 0;
118         struct pci_controller *hose;
119         resource_size_t size;
120 
121         spin_lock(&hose_spinlock);
122         list_for_each_entry(hose, &hose_list, list_node) {
123                 size = pcibios_io_size(hose);
124                 if (address >= hose->io_base_virt &&
125                     address < (hose->io_base_virt + size)) {
126                         ret = 1;
127                         break;
128                 }
129         }
130         spin_unlock(&hose_spinlock);
131         return ret;
132 }
133 
134 unsigned long pci_address_to_pio(phys_addr_t address)
135 {
136         struct pci_controller *hose;
137         resource_size_t size;
138         unsigned long ret = ~0;
139 
140         spin_lock(&hose_spinlock);
141         list_for_each_entry(hose, &hose_list, list_node) {
142                 size = pcibios_io_size(hose);
143                 if (address >= hose->io_base_phys &&
144                     address < (hose->io_base_phys + size)) {
145                         unsigned long base =
146                                 (unsigned long)hose->io_base_virt - _IO_BASE;
147                         ret = base + (address - hose->io_base_phys);
148                         break;
149                 }
150         }
151         spin_unlock(&hose_spinlock);
152 
153         return ret;
154 }
155 EXPORT_SYMBOL_GPL(pci_address_to_pio);
156 
157 /*
158  * Return the domain number for this bus.
159  */
160 int pci_domain_nr(struct pci_bus *bus)
161 {
162         struct pci_controller *hose = pci_bus_to_host(bus);
163 
164         return hose->global_number;
165 }
166 EXPORT_SYMBOL(pci_domain_nr);
167 
168 /* This routine is meant to be used early during boot, when the
169  * PCI bus numbers have not yet been assigned, and you need to
170  * issue PCI config cycles to an OF device.
171  * It could also be used to "fix" RTAS config cycles if you want
172  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
173  * config cycles.
174  */
175 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
176 {
177         while(node) {
178                 struct pci_controller *hose, *tmp;
179                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
180                         if (hose->dn == node)
181                                 return hose;
182                 node = node->parent;
183         }
184         return NULL;
185 }
186 
187 static ssize_t pci_show_devspec(struct device *dev,
188                 struct device_attribute *attr, char *buf)
189 {
190         struct pci_dev *pdev;
191         struct device_node *np;
192 
193         pdev = to_pci_dev (dev);
194         np = pci_device_to_OF_node(pdev);
195         if (np == NULL || np->full_name == NULL)
196                 return 0;
197         return sprintf(buf, "%s", np->full_name);
198 }
199 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
200 
201 /* Add sysfs properties */
202 int pcibios_add_platform_entries(struct pci_dev *pdev)
203 {
204         return device_create_file(&pdev->dev, &dev_attr_devspec);
205 }
206 
207 char __devinit *pcibios_setup(char *str)
208 {
209         return str;
210 }
211 
212 /*
213  * Reads the interrupt pin to determine if interrupt is use by card.
214  * If the interrupt is used, then gets the interrupt line from the
215  * openfirmware and sets it in the pci_dev and pci_config line.
216  */
217 int pci_read_irq_line(struct pci_dev *pci_dev)
218 {
219         struct of_irq oirq;
220         unsigned int virq;
221 
222         /* The current device-tree that iSeries generates from the HV
223          * PCI informations doesn't contain proper interrupt routing,
224          * and all the fallback would do is print out crap, so we
225          * don't attempt to resolve the interrupts here at all, some
226          * iSeries specific fixup does it.
227          *
228          * In the long run, we will hopefully fix the generated device-tree
229          * instead.
230          */
231 #ifdef CONFIG_PPC_ISERIES
232         if (firmware_has_feature(FW_FEATURE_ISERIES))
233                 return -1;
234 #endif
235 
236         pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
237 
238 #ifdef DEBUG
239         memset(&oirq, 0xff, sizeof(oirq));
240 #endif
241         /* Try to get a mapping from the device-tree */
242         if (of_irq_map_pci(pci_dev, &oirq)) {
243                 u8 line, pin;
244 
245                 /* If that fails, lets fallback to what is in the config
246                  * space and map that through the default controller. We
247                  * also set the type to level low since that's what PCI
248                  * interrupts are. If your platform does differently, then
249                  * either provide a proper interrupt tree or don't use this
250                  * function.
251                  */
252                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
253                         return -1;
254                 if (pin == 0)
255                         return -1;
256                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
257                     line == 0xff || line == 0) {
258                         return -1;
259                 }
260                 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
261                          line, pin);
262 
263                 virq = irq_create_mapping(NULL, line);
264                 if (virq != NO_IRQ)
265                         irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
266         } else {
267                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
268                          oirq.size, oirq.specifier[0], oirq.specifier[1],
269                          oirq.controller ? oirq.controller->full_name :
270                          "<default>");
271 
272                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
273                                              oirq.size);
274         }
275         if(virq == NO_IRQ) {
276                 pr_debug(" Failed to map !\n");
277                 return -1;
278         }
279 
280         pr_debug(" Mapped to linux irq %d\n", virq);
281 
282         pci_dev->irq = virq;
283 
284         return 0;
285 }
286 EXPORT_SYMBOL(pci_read_irq_line);
287 
288 /*
289  * Platform support for /proc/bus/pci/X/Y mmap()s,
290  * modelled on the sparc64 implementation by Dave Miller.
291  *  -- paulus.
292  */
293 
294 /*
295  * Adjust vm_pgoff of VMA such that it is the physical page offset
296  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
297  *
298  * Basically, the user finds the base address for his device which he wishes
299  * to mmap.  They read the 32-bit value from the config space base register,
300  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
301  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
302  *
303  * Returns negative error code on failure, zero on success.
304  */
305 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
306                                                resource_size_t *offset,
307                                                enum pci_mmap_state mmap_state)
308 {
309         struct pci_controller *hose = pci_bus_to_host(dev->bus);
310         unsigned long io_offset = 0;
311         int i, res_bit;
312 
313         if (hose == 0)
314                 return NULL;            /* should never happen */
315 
316         /* If memory, add on the PCI bridge address offset */
317         if (mmap_state == pci_mmap_mem) {
318 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
319                 *offset += hose->pci_mem_offset;
320 #endif
321                 res_bit = IORESOURCE_MEM;
322         } else {
323                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
324                 *offset += io_offset;
325                 res_bit = IORESOURCE_IO;
326         }
327 
328         /*
329          * Check that the offset requested corresponds to one of the
330          * resources of the device.
331          */
332         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
333                 struct resource *rp = &dev->resource[i];
334                 int flags = rp->flags;
335 
336                 /* treat ROM as memory (should be already) */
337                 if (i == PCI_ROM_RESOURCE)
338                         flags |= IORESOURCE_MEM;
339 
340                 /* Active and same type? */
341                 if ((flags & res_bit) == 0)
342                         continue;
343 
344                 /* In the range of this resource? */
345                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
346                         continue;
347 
348                 /* found it! construct the final physical address */
349                 if (mmap_state == pci_mmap_io)
350                         *offset += hose->io_base_phys - io_offset;
351                 return rp;
352         }
353 
354         return NULL;
355 }
356 
357 /*
358  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
359  * device mapping.
360  */
361 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
362                                       pgprot_t protection,
363                                       enum pci_mmap_state mmap_state,
364                                       int write_combine)
365 {
366 
367         /* Write combine is always 0 on non-memory space mappings. On
368          * memory space, if the user didn't pass 1, we check for a
369          * "prefetchable" resource. This is a bit hackish, but we use
370          * this to workaround the inability of /sysfs to provide a write
371          * combine bit
372          */
373         if (mmap_state != pci_mmap_mem)
374                 write_combine = 0;
375         else if (write_combine == 0) {
376                 if (rp->flags & IORESOURCE_PREFETCH)
377                         write_combine = 1;
378         }
379 
380         /* XXX would be nice to have a way to ask for write-through */
381         if (write_combine)
382                 return pgprot_noncached_wc(protection);
383         else
384                 return pgprot_noncached(protection);
385 }
386 
387 /*
388  * This one is used by /dev/mem and fbdev who have no clue about the
389  * PCI device, it tries to find the PCI device first and calls the
390  * above routine
391  */
392 pgprot_t pci_phys_mem_access_prot(struct file *file,
393                                   unsigned long pfn,
394                                   unsigned long size,
395                                   pgprot_t prot)
396 {
397         struct pci_dev *pdev = NULL;
398         struct resource *found = NULL;
399         resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
400         int i;
401 
402         if (page_is_ram(pfn))
403                 return prot;
404 
405         prot = pgprot_noncached(prot);
406         for_each_pci_dev(pdev) {
407                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
408                         struct resource *rp = &pdev->resource[i];
409                         int flags = rp->flags;
410 
411                         /* Active and same type? */
412                         if ((flags & IORESOURCE_MEM) == 0)
413                                 continue;
414                         /* In the range of this resource? */
415                         if (offset < (rp->start & PAGE_MASK) ||
416                             offset > rp->end)
417                                 continue;
418                         found = rp;
419                         break;
420                 }
421                 if (found)
422                         break;
423         }
424         if (found) {
425                 if (found->flags & IORESOURCE_PREFETCH)
426                         prot = pgprot_noncached_wc(prot);
427                 pci_dev_put(pdev);
428         }
429 
430         pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
431                  (unsigned long long)offset, pgprot_val(prot));
432 
433         return prot;
434 }
435 
436 
437 /*
438  * Perform the actual remap of the pages for a PCI device mapping, as
439  * appropriate for this architecture.  The region in the process to map
440  * is described by vm_start and vm_end members of VMA, the base physical
441  * address is found in vm_pgoff.
442  * The pci device structure is provided so that architectures may make mapping
443  * decisions on a per-device or per-bus basis.
444  *
445  * Returns a negative error code on failure, zero on success.
446  */
447 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
448                         enum pci_mmap_state mmap_state, int write_combine)
449 {
450         resource_size_t offset =
451                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
452         struct resource *rp;
453         int ret;
454 
455         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
456         if (rp == NULL)
457                 return -EINVAL;
458 
459         vma->vm_pgoff = offset >> PAGE_SHIFT;
460         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
461                                                   vma->vm_page_prot,
462                                                   mmap_state, write_combine);
463 
464         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
465                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
466 
467         return ret;
468 }
469 
470 /* This provides legacy IO read access on a bus */
471 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
472 {
473         unsigned long offset;
474         struct pci_controller *hose = pci_bus_to_host(bus);
475         struct resource *rp = &hose->io_resource;
476         void __iomem *addr;
477 
478         /* Check if port can be supported by that bus. We only check
479          * the ranges of the PHB though, not the bus itself as the rules
480          * for forwarding legacy cycles down bridges are not our problem
481          * here. So if the host bridge supports it, we do it.
482          */
483         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
484         offset += port;
485 
486         if (!(rp->flags & IORESOURCE_IO))
487                 return -ENXIO;
488         if (offset < rp->start || (offset + size) > rp->end)
489                 return -ENXIO;
490         addr = hose->io_base_virt + port;
491 
492         switch(size) {
493         case 1:
494                 *((u8 *)val) = in_8(addr);
495                 return 1;
496         case 2:
497                 if (port & 1)
498                         return -EINVAL;
499                 *((u16 *)val) = in_le16(addr);
500                 return 2;
501         case 4:
502                 if (port & 3)
503                         return -EINVAL;
504                 *((u32 *)val) = in_le32(addr);
505                 return 4;
506         }
507         return -EINVAL;
508 }
509 
510 /* This provides legacy IO write access on a bus */
511 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
512 {
513         unsigned long offset;
514         struct pci_controller *hose = pci_bus_to_host(bus);
515         struct resource *rp = &hose->io_resource;
516         void __iomem *addr;
517 
518         /* Check if port can be supported by that bus. We only check
519          * the ranges of the PHB though, not the bus itself as the rules
520          * for forwarding legacy cycles down bridges are not our problem
521          * here. So if the host bridge supports it, we do it.
522          */
523         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
524         offset += port;
525 
526         if (!(rp->flags & IORESOURCE_IO))
527                 return -ENXIO;
528         if (offset < rp->start || (offset + size) > rp->end)
529                 return -ENXIO;
530         addr = hose->io_base_virt + port;
531 
532         /* WARNING: The generic code is idiotic. It gets passed a pointer
533          * to what can be a 1, 2 or 4 byte quantity and always reads that
534          * as a u32, which means that we have to correct the location of
535          * the data read within those 32 bits for size 1 and 2
536          */
537         switch(size) {
538         case 1:
539                 out_8(addr, val >> 24);
540                 return 1;
541         case 2:
542                 if (port & 1)
543                         return -EINVAL;
544                 out_le16(addr, val >> 16);
545                 return 2;
546         case 4:
547                 if (port & 3)
548                         return -EINVAL;
549                 out_le32(addr, val);
550                 return 4;
551         }
552         return -EINVAL;
553 }
554 
555 /* This provides legacy IO or memory mmap access on a bus */
556 int pci_mmap_legacy_page_range(struct pci_bus *bus,
557                                struct vm_area_struct *vma,
558                                enum pci_mmap_state mmap_state)
559 {
560         struct pci_controller *hose = pci_bus_to_host(bus);
561         resource_size_t offset =
562                 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
563         resource_size_t size = vma->vm_end - vma->vm_start;
564         struct resource *rp;
565 
566         pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
567                  pci_domain_nr(bus), bus->number,
568                  mmap_state == pci_mmap_mem ? "MEM" : "IO",
569                  (unsigned long long)offset,
570                  (unsigned long long)(offset + size - 1));
571 
572         if (mmap_state == pci_mmap_mem) {
573                 /* Hack alert !
574                  *
575                  * Because X is lame and can fail starting if it gets an error trying
576                  * to mmap legacy_mem (instead of just moving on without legacy memory
577                  * access) we fake it here by giving it anonymous memory, effectively
578                  * behaving just like /dev/zero
579                  */
580                 if ((offset + size) > hose->isa_mem_size) {
581                         printk(KERN_DEBUG
582                                "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
583                                current->comm, current->pid, pci_domain_nr(bus), bus->number);
584                         if (vma->vm_flags & VM_SHARED)
585                                 return shmem_zero_setup(vma);
586                         return 0;
587                 }
588                 offset += hose->isa_mem_phys;
589         } else {
590                 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
591                 unsigned long roffset = offset + io_offset;
592                 rp = &hose->io_resource;
593                 if (!(rp->flags & IORESOURCE_IO))
594                         return -ENXIO;
595                 if (roffset < rp->start || (roffset + size) > rp->end)
596                         return -ENXIO;
597                 offset += hose->io_base_phys;
598         }
599         pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
600 
601         vma->vm_pgoff = offset >> PAGE_SHIFT;
602         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
603         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
604                                vma->vm_end - vma->vm_start,
605                                vma->vm_page_prot);
606 }
607 
608 void pci_resource_to_user(const struct pci_dev *dev, int bar,
609                           const struct resource *rsrc,
610                           resource_size_t *start, resource_size_t *end)
611 {
612         struct pci_controller *hose = pci_bus_to_host(dev->bus);
613         resource_size_t offset = 0;
614 
615         if (hose == NULL)
616                 return;
617 
618         if (rsrc->flags & IORESOURCE_IO)
619                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
620 
621         /* We pass a fully fixed up address to userland for MMIO instead of
622          * a BAR value because X is lame and expects to be able to use that
623          * to pass to /dev/mem !
624          *
625          * That means that we'll have potentially 64 bits values where some
626          * userland apps only expect 32 (like X itself since it thinks only
627          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
628          * 32 bits CHRPs :-(
629          *
630          * Hopefully, the sysfs insterface is immune to that gunk. Once X
631          * has been fixed (and the fix spread enough), we can re-enable the
632          * 2 lines below and pass down a BAR value to userland. In that case
633          * we'll also have to re-enable the matching code in
634          * __pci_mmap_make_offset().
635          *
636          * BenH.
637          */
638 #if 0
639         else if (rsrc->flags & IORESOURCE_MEM)
640                 offset = hose->pci_mem_offset;
641 #endif
642 
643         *start = rsrc->start - offset;
644         *end = rsrc->end - offset;
645 }
646 
647 /**
648  * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
649  * @hose: newly allocated pci_controller to be setup
650  * @dev: device node of the host bridge
651  * @primary: set if primary bus (32 bits only, soon to be deprecated)
652  *
653  * This function will parse the "ranges" property of a PCI host bridge device
654  * node and setup the resource mapping of a pci controller based on its
655  * content.
656  *
657  * Life would be boring if it wasn't for a few issues that we have to deal
658  * with here:
659  *
660  *   - We can only cope with one IO space range and up to 3 Memory space
661  *     ranges. However, some machines (thanks Apple !) tend to split their
662  *     space into lots of small contiguous ranges. So we have to coalesce.
663  *
664  *   - We can only cope with all memory ranges having the same offset
665  *     between CPU addresses and PCI addresses. Unfortunately, some bridges
666  *     are setup for a large 1:1 mapping along with a small "window" which
667  *     maps PCI address 0 to some arbitrary high address of the CPU space in
668  *     order to give access to the ISA memory hole.
669  *     The way out of here that I've chosen for now is to always set the
670  *     offset based on the first resource found, then override it if we
671  *     have a different offset and the previous was set by an ISA hole.
672  *
673  *   - Some busses have IO space not starting at 0, which causes trouble with
674  *     the way we do our IO resource renumbering. The code somewhat deals with
675  *     it for 64 bits but I would expect problems on 32 bits.
676  *
677  *   - Some 32 bits platforms such as 4xx can have physical space larger than
678  *     32 bits so we need to use 64 bits values for the parsing
679  */
680 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
681                                             struct device_node *dev,
682                                             int primary)
683 {
684         const u32 *ranges;
685         int rlen;
686         int pna = of_n_addr_cells(dev);
687         int np = pna + 5;
688         int memno = 0, isa_hole = -1;
689         u32 pci_space;
690         unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
691         unsigned long long isa_mb = 0;
692         struct resource *res;
693 
694         printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
695                dev->full_name, primary ? "(primary)" : "");
696 
697         /* Get ranges property */
698         ranges = of_get_property(dev, "ranges", &rlen);
699         if (ranges == NULL)
700                 return;
701 
702         /* Parse it */
703         while ((rlen -= np * 4) >= 0) {
704                 /* Read next ranges element */
705                 pci_space = ranges[0];
706                 pci_addr = of_read_number(ranges + 1, 2);
707                 cpu_addr = of_translate_address(dev, ranges + 3);
708                 size = of_read_number(ranges + pna + 3, 2);
709                 ranges += np;
710 
711                 /* If we failed translation or got a zero-sized region
712                  * (some FW try to feed us with non sensical zero sized regions
713                  * such as power3 which look like some kind of attempt at exposing
714                  * the VGA memory hole)
715                  */
716                 if (cpu_addr == OF_BAD_ADDR || size == 0)
717                         continue;
718 
719                 /* Now consume following elements while they are contiguous */
720                 for (; rlen >= np * sizeof(u32);
721                      ranges += np, rlen -= np * 4) {
722                         if (ranges[0] != pci_space)
723                                 break;
724                         pci_next = of_read_number(ranges + 1, 2);
725                         cpu_next = of_translate_address(dev, ranges + 3);
726                         if (pci_next != pci_addr + size ||
727                             cpu_next != cpu_addr + size)
728                                 break;
729                         size += of_read_number(ranges + pna + 3, 2);
730                 }
731 
732                 /* Act based on address space type */
733                 res = NULL;
734                 switch ((pci_space >> 24) & 0x3) {
735                 case 1:         /* PCI IO space */
736                         printk(KERN_INFO
737                                "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
738                                cpu_addr, cpu_addr + size - 1, pci_addr);
739 
740                         /* We support only one IO range */
741                         if (hose->pci_io_size) {
742                                 printk(KERN_INFO
743                                        " \\--> Skipped (too many) !\n");
744                                 continue;
745                         }
746 #ifdef CONFIG_PPC32
747                         /* On 32 bits, limit I/O space to 16MB */
748                         if (size > 0x01000000)
749                                 size = 0x01000000;
750 
751                         /* 32 bits needs to map IOs here */
752                         hose->io_base_virt = ioremap(cpu_addr, size);
753 
754                         /* Expect trouble if pci_addr is not 0 */
755                         if (primary)
756                                 isa_io_base =
757                                         (unsigned long)hose->io_base_virt;
758 #endif /* CONFIG_PPC32 */
759                         /* pci_io_size and io_base_phys always represent IO
760                          * space starting at 0 so we factor in pci_addr
761                          */
762                         hose->pci_io_size = pci_addr + size;
763                         hose->io_base_phys = cpu_addr - pci_addr;
764 
765                         /* Build resource */
766                         res = &hose->io_resource;
767                         res->flags = IORESOURCE_IO;
768                         res->start = pci_addr;
769                         break;
770                 case 2:         /* PCI Memory space */
771                 case 3:         /* PCI 64 bits Memory space */
772                         printk(KERN_INFO
773                                " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
774                                cpu_addr, cpu_addr + size - 1, pci_addr,
775                                (pci_space & 0x40000000) ? "Prefetch" : "");
776 
777                         /* We support only 3 memory ranges */
778                         if (memno >= 3) {
779                                 printk(KERN_INFO
780                                        " \\--> Skipped (too many) !\n");
781                                 continue;
782                         }
783                         /* Handles ISA memory hole space here */
784                         if (pci_addr == 0) {
785                                 isa_mb = cpu_addr;
786                                 isa_hole = memno;
787                                 if (primary || isa_mem_base == 0)
788                                         isa_mem_base = cpu_addr;
789                                 hose->isa_mem_phys = cpu_addr;
790                                 hose->isa_mem_size = size;
791                         }
792 
793                         /* We get the PCI/Mem offset from the first range or
794                          * the, current one if the offset came from an ISA
795                          * hole. If they don't match, bugger.
796                          */
797                         if (memno == 0 ||
798                             (isa_hole >= 0 && pci_addr != 0 &&
799                              hose->pci_mem_offset == isa_mb))
800                                 hose->pci_mem_offset = cpu_addr - pci_addr;
801                         else if (pci_addr != 0 &&
802                                  hose->pci_mem_offset != cpu_addr - pci_addr) {
803                                 printk(KERN_INFO
804                                        " \\--> Skipped (offset mismatch) !\n");
805                                 continue;
806                         }
807 
808                         /* Build resource */
809                         res = &hose->mem_resources[memno++];
810                         res->flags = IORESOURCE_MEM;
811                         if (pci_space & 0x40000000)
812                                 res->flags |= IORESOURCE_PREFETCH;
813                         res->start = cpu_addr;
814                         break;
815                 }
816                 if (res != NULL) {
817                         res->name = dev->full_name;
818                         res->end = res->start + size - 1;
819                         res->parent = NULL;
820                         res->sibling = NULL;
821                         res->child = NULL;
822                 }
823         }
824 
825         /* If there's an ISA hole and the pci_mem_offset is -not- matching
826          * the ISA hole offset, then we need to remove the ISA hole from
827          * the resource list for that brige
828          */
829         if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
830                 unsigned int next = isa_hole + 1;
831                 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
832                 if (next < memno)
833                         memmove(&hose->mem_resources[isa_hole],
834                                 &hose->mem_resources[next],
835                                 sizeof(struct resource) * (memno - next));
836                 hose->mem_resources[--memno].flags = 0;
837         }
838 }
839 
840 /* Decide whether to display the domain number in /proc */
841 int pci_proc_domain(struct pci_bus *bus)
842 {
843         struct pci_controller *hose = pci_bus_to_host(bus);
844 
845         if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
846                 return 0;
847         if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
848                 return hose->global_number != 0;
849         return 1;
850 }
851 
852 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
853                              struct resource *res)
854 {
855         resource_size_t offset = 0, mask = (resource_size_t)-1;
856         struct pci_controller *hose = pci_bus_to_host(dev->bus);
857 
858         if (!hose)
859                 return;
860         if (res->flags & IORESOURCE_IO) {
861                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
862                 mask = 0xffffffffu;
863         } else if (res->flags & IORESOURCE_MEM)
864                 offset = hose->pci_mem_offset;
865 
866         region->start = (res->start - offset) & mask;
867         region->end = (res->end - offset) & mask;
868 }
869 EXPORT_SYMBOL(pcibios_resource_to_bus);
870 
871 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
872                              struct pci_bus_region *region)
873 {
874         resource_size_t offset = 0, mask = (resource_size_t)-1;
875         struct pci_controller *hose = pci_bus_to_host(dev->bus);
876 
877         if (!hose)
878                 return;
879         if (res->flags & IORESOURCE_IO) {
880                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
881                 mask = 0xffffffffu;
882         } else if (res->flags & IORESOURCE_MEM)
883                 offset = hose->pci_mem_offset;
884         res->start = (region->start + offset) & mask;
885         res->end = (region->end + offset) & mask;
886 }
887 EXPORT_SYMBOL(pcibios_bus_to_resource);
888 
889 /* Fixup a bus resource into a linux resource */
890 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
891 {
892         struct pci_controller *hose = pci_bus_to_host(dev->bus);
893         resource_size_t offset = 0, mask = (resource_size_t)-1;
894 
895         if (res->flags & IORESOURCE_IO) {
896                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
897                 mask = 0xffffffffu;
898         } else if (res->flags & IORESOURCE_MEM)
899                 offset = hose->pci_mem_offset;
900 
901         res->start = (res->start + offset) & mask;
902         res->end = (res->end + offset) & mask;
903 }
904 
905 
906 /* This header fixup will do the resource fixup for all devices as they are
907  * probed, but not for bridge ranges
908  */
909 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
910 {
911         struct pci_controller *hose = pci_bus_to_host(dev->bus);
912         int i;
913 
914         if (!hose) {
915                 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
916                        pci_name(dev));
917                 return;
918         }
919         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
920                 struct resource *res = dev->resource + i;
921                 if (!res->flags)
922                         continue;
923                 /* On platforms that have PCI_PROBE_ONLY set, we don't
924                  * consider 0 as an unassigned BAR value. It's technically
925                  * a valid value, but linux doesn't like it... so when we can
926                  * re-assign things, we do so, but if we can't, we keep it
927                  * around and hope for the best...
928                  */
929                 if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) {
930                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
931                                  pci_name(dev), i,
932                                  (unsigned long long)res->start,
933                                  (unsigned long long)res->end,
934                                  (unsigned int)res->flags);
935                         res->end -= res->start;
936                         res->start = 0;
937                         res->flags |= IORESOURCE_UNSET;
938                         continue;
939                 }
940 
941                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
942                          pci_name(dev), i,
943                          (unsigned long long)res->start,\
944                          (unsigned long long)res->end,
945                          (unsigned int)res->flags);
946 
947                 fixup_resource(res, dev);
948 
949                 pr_debug("PCI:%s            %016llx-%016llx\n",
950                          pci_name(dev),
951                          (unsigned long long)res->start,
952                          (unsigned long long)res->end);
953         }
954 
955         /* Call machine specific resource fixup */
956         if (ppc_md.pcibios_fixup_resources)
957                 ppc_md.pcibios_fixup_resources(dev);
958 }
959 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
960 
961 /* This function tries to figure out if a bridge resource has been initialized
962  * by the firmware or not. It doesn't have to be absolutely bullet proof, but
963  * things go more smoothly when it gets it right. It should covers cases such
964  * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
965  */
966 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
967                                                            struct resource *res)
968 {
969         struct pci_controller *hose = pci_bus_to_host(bus);
970         struct pci_dev *dev = bus->self;
971         resource_size_t offset;
972         u16 command;
973         int i;
974 
975         /* We don't do anything if PCI_PROBE_ONLY is set */
976         if (pci_has_flag(PCI_PROBE_ONLY))
977                 return 0;
978 
979         /* Job is a bit different between memory and IO */
980         if (res->flags & IORESOURCE_MEM) {
981                 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
982                  * initialized by somebody
983                  */
984                 if (res->start != hose->pci_mem_offset)
985                         return 0;
986 
987                 /* The BAR is 0, let's check if memory decoding is enabled on
988                  * the bridge. If not, we consider it unassigned
989                  */
990                 pci_read_config_word(dev, PCI_COMMAND, &command);
991                 if ((command & PCI_COMMAND_MEMORY) == 0)
992                         return 1;
993 
994                 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
995                  * resources covers that starting address (0 then it's good enough for
996                  * us for memory
997                  */
998                 for (i = 0; i < 3; i++) {
999                         if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
1000                             hose->mem_resources[i].start == hose->pci_mem_offset)
1001                                 return 0;
1002                 }
1003 
1004                 /* Well, it starts at 0 and we know it will collide so we may as
1005                  * well consider it as unassigned. That covers the Apple case.
1006                  */
1007                 return 1;
1008         } else {
1009                 /* If the BAR is non-0, then we consider it assigned */
1010                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1011                 if (((res->start - offset) & 0xfffffffful) != 0)
1012                         return 0;
1013 
1014                 /* Here, we are a bit different than memory as typically IO space
1015                  * starting at low addresses -is- valid. What we do instead if that
1016                  * we consider as unassigned anything that doesn't have IO enabled
1017                  * in the PCI command register, and that's it.
1018                  */
1019                 pci_read_config_word(dev, PCI_COMMAND, &command);
1020                 if (command & PCI_COMMAND_IO)
1021                         return 0;
1022 
1023                 /* It's starting at 0 and IO is disabled in the bridge, consider
1024                  * it unassigned
1025                  */
1026                 return 1;
1027         }
1028 }
1029 
1030 /* Fixup resources of a PCI<->PCI bridge */
1031 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1032 {
1033         struct resource *res;
1034         int i;
1035 
1036         struct pci_dev *dev = bus->self;
1037 
1038         pci_bus_for_each_resource(bus, res, i) {
1039                 if (!res || !res->flags)
1040                         continue;
1041                 if (i >= 3 && bus->self->transparent)
1042                         continue;
1043 
1044                 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1045                          pci_name(dev), i,
1046                          (unsigned long long)res->start,\
1047                          (unsigned long long)res->end,
1048                          (unsigned int)res->flags);
1049 
1050                 /* Perform fixup */
1051                 fixup_resource(res, dev);
1052 
1053                 /* Try to detect uninitialized P2P bridge resources,
1054                  * and clear them out so they get re-assigned later
1055                  */
1056                 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1057                         res->flags = 0;
1058                         pr_debug("PCI:%s            (unassigned)\n", pci_name(dev));
1059                 } else {
1060 
1061                         pr_debug("PCI:%s            %016llx-%016llx\n",
1062                                  pci_name(dev),
1063                                  (unsigned long long)res->start,
1064                                  (unsigned long long)res->end);
1065                 }
1066         }
1067 }
1068 
1069 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1070 {
1071         /* Fix up the bus resources for P2P bridges */
1072         if (bus->self != NULL)
1073                 pcibios_fixup_bridge(bus);
1074 
1075         /* Platform specific bus fixups. This is currently only used
1076          * by fsl_pci and I'm hoping to get rid of it at some point
1077          */
1078         if (ppc_md.pcibios_fixup_bus)
1079                 ppc_md.pcibios_fixup_bus(bus);
1080 
1081         /* Setup bus DMA mappings */
1082         if (ppc_md.pci_dma_bus_setup)
1083                 ppc_md.pci_dma_bus_setup(bus);
1084 }
1085 
1086 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1087 {
1088         struct pci_dev *dev;
1089 
1090         pr_debug("PCI: Fixup bus devices %d (%s)\n",
1091                  bus->number, bus->self ? pci_name(bus->self) : "PHB");
1092 
1093         list_for_each_entry(dev, &bus->devices, bus_list) {
1094                 /* Cardbus can call us to add new devices to a bus, so ignore
1095                  * those who are already fully discovered
1096                  */
1097                 if (dev->is_added)
1098                         continue;
1099 
1100                 /* Fixup NUMA node as it may not be setup yet by the generic
1101                  * code and is needed by the DMA init
1102                  */
1103                 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1104 
1105                 /* Hook up default DMA ops */
1106                 set_dma_ops(&dev->dev, pci_dma_ops);
1107                 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1108 
1109                 /* Additional platform DMA/iommu setup */
1110                 if (ppc_md.pci_dma_dev_setup)
1111                         ppc_md.pci_dma_dev_setup(dev);
1112 
1113                 /* Read default IRQs and fixup if necessary */
1114                 pci_read_irq_line(dev);
1115                 if (ppc_md.pci_irq_fixup)
1116                         ppc_md.pci_irq_fixup(dev);
1117         }
1118 }
1119 
1120 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1121 {
1122         /* When called from the generic PCI probe, read PCI<->PCI bridge
1123          * bases. This is -not- called when generating the PCI tree from
1124          * the OF device-tree.
1125          */
1126         if (bus->self != NULL)
1127                 pci_read_bridge_bases(bus);
1128 
1129         /* Now fixup the bus bus */
1130         pcibios_setup_bus_self(bus);
1131 
1132         /* Now fixup devices on that bus */
1133         pcibios_setup_bus_devices(bus);
1134 }
1135 EXPORT_SYMBOL(pcibios_fixup_bus);
1136 
1137 void __devinit pci_fixup_cardbus(struct pci_bus *bus)
1138 {
1139         /* Now fixup devices on that bus */
1140         pcibios_setup_bus_devices(bus);
1141 }
1142 
1143 
1144 static int skip_isa_ioresource_align(struct pci_dev *dev)
1145 {
1146         if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1147             !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1148                 return 1;
1149         return 0;
1150 }
1151 
1152 /*
1153  * We need to avoid collisions with `mirrored' VGA ports
1154  * and other strange ISA hardware, so we always want the
1155  * addresses to be allocated in the 0x000-0x0ff region
1156  * modulo 0x400.
1157  *
1158  * Why? Because some silly external IO cards only decode
1159  * the low 10 bits of the IO address. The 0x00-0xff region
1160  * is reserved for motherboard devices that decode all 16
1161  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1162  * but we want to try to avoid allocating at 0x2900-0x2bff
1163  * which might have be mirrored at 0x0100-0x03ff..
1164  */
1165 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1166                                 resource_size_t size, resource_size_t align)
1167 {
1168         struct pci_dev *dev = data;
1169         resource_size_t start = res->start;
1170 
1171         if (res->flags & IORESOURCE_IO) {
1172                 if (skip_isa_ioresource_align(dev))
1173                         return start;
1174                 if (start & 0x300)
1175                         start = (start + 0x3ff) & ~0x3ff;
1176         }
1177 
1178         return start;
1179 }
1180 EXPORT_SYMBOL(pcibios_align_resource);
1181 
1182 /*
1183  * Reparent resource children of pr that conflict with res
1184  * under res, and make res replace those children.
1185  */
1186 static int reparent_resources(struct resource *parent,
1187                                      struct resource *res)
1188 {
1189         struct resource *p, **pp;
1190         struct resource **firstpp = NULL;
1191 
1192         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1193                 if (p->end < res->start)
1194                         continue;
1195                 if (res->end < p->start)
1196                         break;
1197                 if (p->start < res->start || p->end > res->end)
1198                         return -1;      /* not completely contained */
1199                 if (firstpp == NULL)
1200                         firstpp = pp;
1201         }
1202         if (firstpp == NULL)
1203                 return -1;      /* didn't find any conflicting entries? */
1204         res->parent = parent;
1205         res->child = *firstpp;
1206         res->sibling = *pp;
1207         *firstpp = res;
1208         *pp = NULL;
1209         for (p = res->child; p != NULL; p = p->sibling) {
1210                 p->parent = res;
1211                 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1212                          p->name,
1213                          (unsigned long long)p->start,
1214                          (unsigned long long)p->end, res->name);
1215         }
1216         return 0;
1217 }
1218 
1219 /*
1220  *  Handle resources of PCI devices.  If the world were perfect, we could
1221  *  just allocate all the resource regions and do nothing more.  It isn't.
1222  *  On the other hand, we cannot just re-allocate all devices, as it would
1223  *  require us to know lots of host bridge internals.  So we attempt to
1224  *  keep as much of the original configuration as possible, but tweak it
1225  *  when it's found to be wrong.
1226  *
1227  *  Known BIOS problems we have to work around:
1228  *      - I/O or memory regions not configured
1229  *      - regions configured, but not enabled in the command register
1230  *      - bogus I/O addresses above 64K used
1231  *      - expansion ROMs left enabled (this may sound harmless, but given
1232  *        the fact the PCI specs explicitly allow address decoders to be
1233  *        shared between expansion ROMs and other resource regions, it's
1234  *        at least dangerous)
1235  *
1236  *  Our solution:
1237  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1238  *          This gives us fixed barriers on where we can allocate.
1239  *      (2) Allocate resources for all enabled devices.  If there is
1240  *          a collision, just mark the resource as unallocated. Also
1241  *          disable expansion ROMs during this step.
1242  *      (3) Try to allocate resources for disabled devices.  If the
1243  *          resources were assigned correctly, everything goes well,
1244  *          if they weren't, they won't disturb allocation of other
1245  *          resources.
1246  *      (4) Assign new addresses to resources which were either
1247  *          not configured at all or misconfigured.  If explicitly
1248  *          requested by the user, configure expansion ROM address
1249  *          as well.
1250  */
1251 
1252 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1253 {
1254         struct pci_bus *b;
1255         int i;
1256         struct resource *res, *pr;
1257 
1258         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1259                  pci_domain_nr(bus), bus->number);
1260 
1261         pci_bus_for_each_resource(bus, res, i) {
1262                 if (!res || !res->flags || res->start > res->end || res->parent)
1263                         continue;
1264                 if (bus->parent == NULL)
1265                         pr = (res->flags & IORESOURCE_IO) ?
1266                                 &ioport_resource : &iomem_resource;
1267                 else {
1268                         /* Don't bother with non-root busses when
1269                          * re-assigning all resources. We clear the
1270                          * resource flags as if they were colliding
1271                          * and as such ensure proper re-allocation
1272                          * later.
1273                          */
1274                         if (pci_has_flag(PCI_REASSIGN_ALL_RSRC))
1275                                 goto clear_resource;
1276                         pr = pci_find_parent_resource(bus->self, res);
1277                         if (pr == res) {
1278                                 /* this happens when the generic PCI
1279                                  * code (wrongly) decides that this
1280                                  * bridge is transparent  -- paulus
1281                                  */
1282                                 continue;
1283                         }
1284                 }
1285 
1286                 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1287                          "[0x%x], parent %p (%s)\n",
1288                          bus->self ? pci_name(bus->self) : "PHB",
1289                          bus->number, i,
1290                          (unsigned long long)res->start,
1291                          (unsigned long long)res->end,
1292                          (unsigned int)res->flags,
1293                          pr, (pr && pr->name) ? pr->name : "nil");
1294 
1295                 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1296                         if (request_resource(pr, res) == 0)
1297                                 continue;
1298                         /*
1299                          * Must be a conflict with an existing entry.
1300                          * Move that entry (or entries) under the
1301                          * bridge resource and try again.
1302                          */
1303                         if (reparent_resources(pr, res) == 0)
1304                                 continue;
1305                 }
1306                 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1307                        "%d of PCI bridge %d, will remap\n", i, bus->number);
1308 clear_resource:
1309                 res->start = res->end = 0;
1310                 res->flags = 0;
1311         }
1312 
1313         list_for_each_entry(b, &bus->children, node)
1314                 pcibios_allocate_bus_resources(b);
1315 }
1316 
1317 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1318 {
1319         struct resource *pr, *r = &dev->resource[idx];
1320 
1321         pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1322                  pci_name(dev), idx,
1323                  (unsigned long long)r->start,
1324                  (unsigned long long)r->end,
1325                  (unsigned int)r->flags);
1326 
1327         pr = pci_find_parent_resource(dev, r);
1328         if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1329             request_resource(pr, r) < 0) {
1330                 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1331                        " of device %s, will remap\n", idx, pci_name(dev));
1332                 if (pr)
1333                         pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
1334                                  pr,
1335                                  (unsigned long long)pr->start,
1336                                  (unsigned long long)pr->end,
1337                                  (unsigned int)pr->flags);
1338                 /* We'll assign a new address later */
1339                 r->flags |= IORESOURCE_UNSET;
1340                 r->end -= r->start;
1341                 r->start = 0;
1342         }
1343 }
1344 
1345 static void __init pcibios_allocate_resources(int pass)
1346 {
1347         struct pci_dev *dev = NULL;
1348         int idx, disabled;
1349         u16 command;
1350         struct resource *r;
1351 
1352         for_each_pci_dev(dev) {
1353                 pci_read_config_word(dev, PCI_COMMAND, &command);
1354                 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1355                         r = &dev->resource[idx];
1356                         if (r->parent)          /* Already allocated */
1357                                 continue;
1358                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
1359                                 continue;       /* Not assigned at all */
1360                         /* We only allocate ROMs on pass 1 just in case they
1361                          * have been screwed up by firmware
1362                          */
1363                         if (idx == PCI_ROM_RESOURCE )
1364                                 disabled = 1;
1365                         if (r->flags & IORESOURCE_IO)
1366                                 disabled = !(command & PCI_COMMAND_IO);
1367                         else
1368                                 disabled = !(command & PCI_COMMAND_MEMORY);
1369                         if (pass == disabled)
1370                                 alloc_resource(dev, idx);
1371                 }
1372                 if (pass)
1373                         continue;
1374                 r = &dev->resource[PCI_ROM_RESOURCE];
1375                 if (r->flags) {
1376                         /* Turn the ROM off, leave the resource region,
1377                          * but keep it unregistered.
1378                          */
1379                         u32 reg;
1380                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1381                         if (reg & PCI_ROM_ADDRESS_ENABLE) {
1382                                 pr_debug("PCI: Switching off ROM of %s\n",
1383                                          pci_name(dev));
1384                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
1385                                 pci_write_config_dword(dev, dev->rom_base_reg,
1386                                                        reg & ~PCI_ROM_ADDRESS_ENABLE);
1387                         }
1388                 }
1389         }
1390 }
1391 
1392 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1393 {
1394         struct pci_controller *hose = pci_bus_to_host(bus);
1395         resource_size_t offset;
1396         struct resource *res, *pres;
1397         int i;
1398 
1399         pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1400 
1401         /* Check for IO */
1402         if (!(hose->io_resource.flags & IORESOURCE_IO))
1403                 goto no_io;
1404         offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1405         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1406         BUG_ON(res == NULL);
1407         res->name = "Legacy IO";
1408         res->flags = IORESOURCE_IO;
1409         res->start = offset;
1410         res->end = (offset + 0xfff) & 0xfffffffful;
1411         pr_debug("Candidate legacy IO: %pR\n", res);
1412         if (request_resource(&hose->io_resource, res)) {
1413                 printk(KERN_DEBUG
1414                        "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1415                        pci_domain_nr(bus), bus->number, res);
1416                 kfree(res);
1417         }
1418 
1419  no_io:
1420         /* Check for memory */
1421         offset = hose->pci_mem_offset;
1422         pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1423         for (i = 0; i < 3; i++) {
1424                 pres = &hose->mem_resources[i];
1425                 if (!(pres->flags & IORESOURCE_MEM))
1426                         continue;
1427                 pr_debug("hose mem res: %pR\n", pres);
1428                 if ((pres->start - offset) <= 0xa0000 &&
1429                     (pres->end - offset) >= 0xbffff)
1430                         break;
1431         }
1432         if (i >= 3)
1433                 return;
1434         res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1435         BUG_ON(res == NULL);
1436         res->name = "Legacy VGA memory";
1437         res->flags = IORESOURCE_MEM;
1438         res->start = 0xa0000 + offset;
1439         res->end = 0xbffff + offset;
1440         pr_debug("Candidate VGA memory: %pR\n", res);
1441         if (request_resource(pres, res)) {
1442                 printk(KERN_DEBUG
1443                        "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1444                        pci_domain_nr(bus), bus->number, res);
1445                 kfree(res);
1446         }
1447 }
1448 
1449 void __init pcibios_resource_survey(void)
1450 {
1451         struct pci_bus *b;
1452 
1453         /* Allocate and assign resources. If we re-assign everything, then
1454          * we skip the allocate phase
1455          */
1456         list_for_each_entry(b, &pci_root_buses, node)
1457                 pcibios_allocate_bus_resources(b);
1458 
1459         if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1460                 pcibios_allocate_resources(0);
1461                 pcibios_allocate_resources(1);
1462         }
1463 
1464         /* Before we start assigning unassigned resource, we try to reserve
1465          * the low IO area and the VGA memory area if they intersect the
1466          * bus available resources to avoid allocating things on top of them
1467          */
1468         if (!pci_has_flag(PCI_PROBE_ONLY)) {
1469                 list_for_each_entry(b, &pci_root_buses, node)
1470                         pcibios_reserve_legacy_regions(b);
1471         }
1472 
1473         /* Now, if the platform didn't decide to blindly trust the firmware,
1474          * we proceed to assigning things that were left unassigned
1475          */
1476         if (!pci_has_flag(PCI_PROBE_ONLY)) {
1477                 pr_debug("PCI: Assigning unassigned resources...\n");
1478                 pci_assign_unassigned_resources();
1479         }
1480 
1481         /* Call machine dependent fixup */
1482         if (ppc_md.pcibios_fixup)
1483                 ppc_md.pcibios_fixup();
1484 }
1485 
1486 #ifdef CONFIG_HOTPLUG
1487 
1488 /* This is used by the PCI hotplug driver to allocate resource
1489  * of newly plugged busses. We can try to consolidate with the
1490  * rest of the code later, for now, keep it as-is as our main
1491  * resource allocation function doesn't deal with sub-trees yet.
1492  */
1493 void pcibios_claim_one_bus(struct pci_bus *bus)
1494 {
1495         struct pci_dev *dev;
1496         struct pci_bus *child_bus;
1497 
1498         list_for_each_entry(dev, &bus->devices, bus_list) {
1499                 int i;
1500 
1501                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1502                         struct resource *r = &dev->resource[i];
1503 
1504                         if (r->parent || !r->start || !r->flags)
1505                                 continue;
1506 
1507                         pr_debug("PCI: Claiming %s: "
1508                                  "Resource %d: %016llx..%016llx [%x]\n",
1509                                  pci_name(dev), i,
1510                                  (unsigned long long)r->start,
1511                                  (unsigned long long)r->end,
1512                                  (unsigned int)r->flags);
1513 
1514                         pci_claim_resource(dev, i);
1515                 }
1516         }
1517 
1518         list_for_each_entry(child_bus, &bus->children, node)
1519                 pcibios_claim_one_bus(child_bus);
1520 }
1521 
1522 
1523 /* pcibios_finish_adding_to_bus
1524  *
1525  * This is to be called by the hotplug code after devices have been
1526  * added to a bus, this include calling it for a PHB that is just
1527  * being added
1528  */
1529 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1530 {
1531         pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1532                  pci_domain_nr(bus), bus->number);
1533 
1534         /* Allocate bus and devices resources */
1535         pcibios_allocate_bus_resources(bus);
1536         pcibios_claim_one_bus(bus);
1537 
1538         /* Add new devices to global lists.  Register in proc, sysfs. */
1539         pci_bus_add_devices(bus);
1540 
1541         /* Fixup EEH */
1542         eeh_add_device_tree_late(bus);
1543 }
1544 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1545 
1546 #endif /* CONFIG_HOTPLUG */
1547 
1548 int pcibios_enable_device(struct pci_dev *dev, int mask)
1549 {
1550         if (ppc_md.pcibios_enable_device_hook)
1551                 if (ppc_md.pcibios_enable_device_hook(dev))
1552                         return -EINVAL;
1553 
1554         return pci_enable_resources(dev, mask);
1555 }
1556 
1557 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1558 {
1559         struct pci_bus *bus = hose->bus;
1560         struct resource *res;
1561         int i;
1562 
1563         /* Hookup PHB IO resource */
1564         bus->resource[0] = res = &hose->io_resource;
1565 
1566         if (!res->flags) {
1567                 printk(KERN_WARNING "PCI: I/O resource not set for host"
1568                        " bridge %s (domain %d)\n",
1569                        hose->dn->full_name, hose->global_number);
1570 #ifdef CONFIG_PPC32
1571                 /* Workaround for lack of IO resource only on 32-bit */
1572                 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1573                 res->end = res->start + IO_SPACE_LIMIT;
1574                 res->flags = IORESOURCE_IO;
1575 #endif /* CONFIG_PPC32 */
1576         }
1577 
1578         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
1579                  (unsigned long long)res->start,
1580                  (unsigned long long)res->end,
1581                  (unsigned long)res->flags);
1582 
1583         /* Hookup PHB Memory resources */
1584         for (i = 0; i < 3; ++i) {
1585                 res = &hose->mem_resources[i];
1586                 if (!res->flags) {
1587                         if (i > 0)
1588                                 continue;
1589                         printk(KERN_ERR "PCI: Memory resource 0 not set for "
1590                                "host bridge %s (domain %d)\n",
1591                                hose->dn->full_name, hose->global_number);
1592 #ifdef CONFIG_PPC32
1593                         /* Workaround for lack of MEM resource only on 32-bit */
1594                         res->start = hose->pci_mem_offset;
1595                         res->end = (resource_size_t)-1LL;
1596                         res->flags = IORESOURCE_MEM;
1597 #endif /* CONFIG_PPC32 */
1598                 }
1599                 bus->resource[i+1] = res;
1600 
1601                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1602                          (unsigned long long)res->start,
1603                          (unsigned long long)res->end,
1604                          (unsigned long)res->flags);
1605         }
1606 
1607         pr_debug("PCI: PHB MEM offset     = %016llx\n",
1608                  (unsigned long long)hose->pci_mem_offset);
1609         pr_debug("PCI: PHB IO  offset     = %08lx\n",
1610                  (unsigned long)hose->io_base_virt - _IO_BASE);
1611 
1612 }
1613 
1614 /*
1615  * Null PCI config access functions, for the case when we can't
1616  * find a hose.
1617  */
1618 #define NULL_PCI_OP(rw, size, type)                                     \
1619 static int                                                              \
1620 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1621 {                                                                       \
1622         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1623 }
1624 
1625 static int
1626 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1627                  int len, u32 *val)
1628 {
1629         return PCIBIOS_DEVICE_NOT_FOUND;
1630 }
1631 
1632 static int
1633 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1634                   int len, u32 val)
1635 {
1636         return PCIBIOS_DEVICE_NOT_FOUND;
1637 }
1638 
1639 static struct pci_ops null_pci_ops =
1640 {
1641         .read = null_read_config,
1642         .write = null_write_config,
1643 };
1644 
1645 /*
1646  * These functions are used early on before PCI scanning is done
1647  * and all of the pci_dev and pci_bus structures have been created.
1648  */
1649 static struct pci_bus *
1650 fake_pci_bus(struct pci_controller *hose, int busnr)
1651 {
1652         static struct pci_bus bus;
1653 
1654         if (hose == 0) {
1655                 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1656         }
1657         bus.number = busnr;
1658         bus.sysdata = hose;
1659         bus.ops = hose? hose->ops: &null_pci_ops;
1660         return &bus;
1661 }
1662 
1663 #define EARLY_PCI_OP(rw, size, type)                                    \
1664 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1665                                int devfn, int offset, type value)       \
1666 {                                                                       \
1667         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1668                                             devfn, offset, value);      \
1669 }
1670 
1671 EARLY_PCI_OP(read, byte, u8 *)
1672 EARLY_PCI_OP(read, word, u16 *)
1673 EARLY_PCI_OP(read, dword, u32 *)
1674 EARLY_PCI_OP(write, byte, u8)
1675 EARLY_PCI_OP(write, word, u16)
1676 EARLY_PCI_OP(write, dword, u32)
1677 
1678 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1679 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1680                           int cap)
1681 {
1682         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1683 }
1684 
1685 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1686 {
1687         struct pci_controller *hose = bus->sysdata;
1688 
1689         return of_node_get(hose->dn);
1690 }
1691 
1692 /**
1693  * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1694  * @hose: Pointer to the PCI host controller instance structure
1695  */
1696 void __devinit pcibios_scan_phb(struct pci_controller *hose)
1697 {
1698         struct pci_bus *bus;
1699         struct device_node *node = hose->dn;
1700         int mode;
1701 
1702         pr_debug("PCI: Scanning PHB %s\n",
1703                  node ? node->full_name : "<NO NAME>");
1704 
1705         /* Create an empty bus for the toplevel */
1706         bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
1707         if (bus == NULL) {
1708                 pr_err("Failed to create bus for PCI domain %04x\n",
1709                         hose->global_number);
1710                 return;
1711         }
1712         bus->secondary = hose->first_busno;
1713         hose->bus = bus;
1714 
1715         /* Get some IO space for the new PHB */
1716         pcibios_setup_phb_io_space(hose);
1717 
1718         /* Wire up PHB bus resources */
1719         pcibios_setup_phb_resources(hose);
1720 
1721         /* Get probe mode and perform scan */
1722         mode = PCI_PROBE_NORMAL;
1723         if (node && ppc_md.pci_probe_mode)
1724                 mode = ppc_md.pci_probe_mode(bus);
1725         pr_debug("    probe mode: %d\n", mode);
1726         if (mode == PCI_PROBE_DEVTREE) {
1727                 bus->subordinate = hose->last_busno;
1728                 of_scan_bus(node, bus);
1729         }
1730 
1731         if (mode == PCI_PROBE_NORMAL)
1732                 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1733 
1734         /* Configure PCI Express settings */
1735         if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1736                 struct pci_bus *child;
1737                 list_for_each_entry(child, &bus->children, node) {
1738                         struct pci_dev *self = child->self;
1739                         if (!self)
1740                                 continue;
1741                         pcie_bus_configure_settings(child, self->pcie_mpss);
1742                 }
1743         }
1744 }
1745 
1746 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1747 {
1748         int i, class = dev->class >> 8;
1749 
1750         if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1751              class == PCI_CLASS_BRIDGE_OTHER) &&
1752                 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1753                 (dev->bus->parent == NULL)) {
1754                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1755                         dev->resource[i].start = 0;
1756                         dev->resource[i].end = 0;
1757                         dev->resource[i].flags = 0;
1758                 }
1759         }
1760 }
1761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1763 

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