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Linux/arch/powerpc/mm/book3s64/hash_utils.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
  4  *   {mikejc|engebret}@us.ibm.com
  5  *
  6  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
  7  *
  8  * SMP scalability work:
  9  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
 10  * 
 11  *    Module name: htab.c
 12  *
 13  *    Description:
 14  *      PowerPC Hashed Page Table functions
 15  */
 16 
 17 #undef DEBUG
 18 #undef DEBUG_LOW
 19 
 20 #define pr_fmt(fmt) "hash-mmu: " fmt
 21 #include <linux/spinlock.h>
 22 #include <linux/errno.h>
 23 #include <linux/sched/mm.h>
 24 #include <linux/proc_fs.h>
 25 #include <linux/stat.h>
 26 #include <linux/sysctl.h>
 27 #include <linux/export.h>
 28 #include <linux/ctype.h>
 29 #include <linux/cache.h>
 30 #include <linux/init.h>
 31 #include <linux/signal.h>
 32 #include <linux/memblock.h>
 33 #include <linux/context_tracking.h>
 34 #include <linux/libfdt.h>
 35 #include <linux/pkeys.h>
 36 #include <linux/hugetlb.h>
 37 #include <linux/cpu.h>
 38 
 39 #include <asm/debugfs.h>
 40 #include <asm/processor.h>
 41 #include <asm/pgtable.h>
 42 #include <asm/mmu.h>
 43 #include <asm/mmu_context.h>
 44 #include <asm/page.h>
 45 #include <asm/types.h>
 46 #include <linux/uaccess.h>
 47 #include <asm/machdep.h>
 48 #include <asm/prom.h>
 49 #include <asm/io.h>
 50 #include <asm/eeh.h>
 51 #include <asm/tlb.h>
 52 #include <asm/cacheflush.h>
 53 #include <asm/cputable.h>
 54 #include <asm/sections.h>
 55 #include <asm/copro.h>
 56 #include <asm/udbg.h>
 57 #include <asm/code-patching.h>
 58 #include <asm/fadump.h>
 59 #include <asm/firmware.h>
 60 #include <asm/tm.h>
 61 #include <asm/trace.h>
 62 #include <asm/ps3.h>
 63 #include <asm/pte-walk.h>
 64 #include <asm/asm-prototypes.h>
 65 #include <asm/ultravisor.h>
 66 
 67 #include <mm/mmu_decl.h>
 68 
 69 #ifdef DEBUG
 70 #define DBG(fmt...) udbg_printf(fmt)
 71 #else
 72 #define DBG(fmt...)
 73 #endif
 74 
 75 #ifdef DEBUG_LOW
 76 #define DBG_LOW(fmt...) udbg_printf(fmt)
 77 #else
 78 #define DBG_LOW(fmt...)
 79 #endif
 80 
 81 #define KB (1024)
 82 #define MB (1024*KB)
 83 #define GB (1024L*MB)
 84 
 85 /*
 86  * Note:  pte   --> Linux PTE
 87  *        HPTE  --> PowerPC Hashed Page Table Entry
 88  *
 89  * Execution context:
 90  *   htab_initialize is called with the MMU off (of course), but
 91  *   the kernel has been copied down to zero so it can directly
 92  *   reference global data.  At this point it is very difficult
 93  *   to print debug info.
 94  *
 95  */
 96 
 97 static unsigned long _SDR1;
 98 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 99 EXPORT_SYMBOL_GPL(mmu_psize_defs);
100 
101 u8 hpte_page_sizes[1 << LP_BITS];
102 EXPORT_SYMBOL_GPL(hpte_page_sizes);
103 
104 struct hash_pte *htab_address;
105 unsigned long htab_size_bytes;
106 unsigned long htab_hash_mask;
107 EXPORT_SYMBOL_GPL(htab_hash_mask);
108 int mmu_linear_psize = MMU_PAGE_4K;
109 EXPORT_SYMBOL_GPL(mmu_linear_psize);
110 int mmu_virtual_psize = MMU_PAGE_4K;
111 int mmu_vmalloc_psize = MMU_PAGE_4K;
112 #ifdef CONFIG_SPARSEMEM_VMEMMAP
113 int mmu_vmemmap_psize = MMU_PAGE_4K;
114 #endif
115 int mmu_io_psize = MMU_PAGE_4K;
116 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
117 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
118 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
119 u16 mmu_slb_size = 64;
120 EXPORT_SYMBOL_GPL(mmu_slb_size);
121 #ifdef CONFIG_PPC_64K_PAGES
122 int mmu_ci_restrictions;
123 #endif
124 #ifdef CONFIG_DEBUG_PAGEALLOC
125 static u8 *linear_map_hash_slots;
126 static unsigned long linear_map_hash_count;
127 static DEFINE_SPINLOCK(linear_map_hash_lock);
128 #endif /* CONFIG_DEBUG_PAGEALLOC */
129 struct mmu_hash_ops mmu_hash_ops;
130 EXPORT_SYMBOL(mmu_hash_ops);
131 
132 /*
133  * These are definitions of page sizes arrays to be used when none
134  * is provided by the firmware.
135  */
136 
137 /*
138  * Fallback (4k pages only)
139  */
140 static struct mmu_psize_def mmu_psize_defaults[] = {
141         [MMU_PAGE_4K] = {
142                 .shift  = 12,
143                 .sllp   = 0,
144                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
145                 .avpnm  = 0,
146                 .tlbiel = 0,
147         },
148 };
149 
150 /*
151  * POWER4, GPUL, POWER5
152  *
153  * Support for 16Mb large pages
154  */
155 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
156         [MMU_PAGE_4K] = {
157                 .shift  = 12,
158                 .sllp   = 0,
159                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
160                 .avpnm  = 0,
161                 .tlbiel = 1,
162         },
163         [MMU_PAGE_16M] = {
164                 .shift  = 24,
165                 .sllp   = SLB_VSID_L,
166                 .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
167                             [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
168                 .avpnm  = 0x1UL,
169                 .tlbiel = 0,
170         },
171 };
172 
173 /*
174  * 'R' and 'C' update notes:
175  *  - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
176  *     create writeable HPTEs without C set, because the hcall H_PROTECT
177  *     that we use in that case will not update C
178  *  - The above is however not a problem, because we also don't do that
179  *     fancy "no flush" variant of eviction and we use H_REMOVE which will
180  *     do the right thing and thus we don't have the race I described earlier
181  *
182  *    - Under bare metal,  we do have the race, so we need R and C set
183  *    - We make sure R is always set and never lost
184  *    - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
185  */
186 unsigned long htab_convert_pte_flags(unsigned long pteflags)
187 {
188         unsigned long rflags = 0;
189 
190         /* _PAGE_EXEC -> NOEXEC */
191         if ((pteflags & _PAGE_EXEC) == 0)
192                 rflags |= HPTE_R_N;
193         /*
194          * PPP bits:
195          * Linux uses slb key 0 for kernel and 1 for user.
196          * kernel RW areas are mapped with PPP=0b000
197          * User area is mapped with PPP=0b010 for read/write
198          * or PPP=0b011 for read-only (including writeable but clean pages).
199          */
200         if (pteflags & _PAGE_PRIVILEGED) {
201                 /*
202                  * Kernel read only mapped with ppp bits 0b110
203                  */
204                 if (!(pteflags & _PAGE_WRITE)) {
205                         if (mmu_has_feature(MMU_FTR_KERNEL_RO))
206                                 rflags |= (HPTE_R_PP0 | 0x2);
207                         else
208                                 rflags |= 0x3;
209                 }
210         } else {
211                 if (pteflags & _PAGE_RWX)
212                         rflags |= 0x2;
213                 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
214                         rflags |= 0x1;
215         }
216         /*
217          * We can't allow hardware to update hpte bits. Hence always
218          * set 'R' bit and set 'C' if it is a write fault
219          */
220         rflags |=  HPTE_R_R;
221 
222         if (pteflags & _PAGE_DIRTY)
223                 rflags |= HPTE_R_C;
224         /*
225          * Add in WIG bits
226          */
227 
228         if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
229                 rflags |= HPTE_R_I;
230         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
231                 rflags |= (HPTE_R_I | HPTE_R_G);
232         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
233                 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
234         else
235                 /*
236                  * Add memory coherence if cache inhibited is not set
237                  */
238                 rflags |= HPTE_R_M;
239 
240         rflags |= pte_to_hpte_pkey_bits(pteflags);
241         return rflags;
242 }
243 
244 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
245                       unsigned long pstart, unsigned long prot,
246                       int psize, int ssize)
247 {
248         unsigned long vaddr, paddr;
249         unsigned int step, shift;
250         int ret = 0;
251 
252         shift = mmu_psize_defs[psize].shift;
253         step = 1 << shift;
254 
255         prot = htab_convert_pte_flags(prot);
256 
257         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
258             vstart, vend, pstart, prot, psize, ssize);
259 
260         for (vaddr = vstart, paddr = pstart; vaddr < vend;
261              vaddr += step, paddr += step) {
262                 unsigned long hash, hpteg;
263                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
264                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
265                 unsigned long tprot = prot;
266                 bool secondary_hash = false;
267 
268                 /*
269                  * If we hit a bad address return error.
270                  */
271                 if (!vsid)
272                         return -1;
273                 /* Make kernel text executable */
274                 if (overlaps_kernel_text(vaddr, vaddr + step))
275                         tprot &= ~HPTE_R_N;
276 
277                 /*
278                  * If relocatable, check if it overlaps interrupt vectors that
279                  * are copied down to real 0. For relocatable kernel
280                  * (e.g. kdump case) we copy interrupt vectors down to real
281                  * address 0. Mark that region as executable. This is
282                  * because on p8 system with relocation on exception feature
283                  * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
284                  * in order to execute the interrupt handlers in virtual
285                  * mode the vector region need to be marked as executable.
286                  */
287                 if ((PHYSICAL_START > MEMORY_START) &&
288                         overlaps_interrupt_vector_text(vaddr, vaddr + step))
289                                 tprot &= ~HPTE_R_N;
290 
291                 hash = hpt_hash(vpn, shift, ssize);
292                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
293 
294                 BUG_ON(!mmu_hash_ops.hpte_insert);
295 repeat:
296                 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
297                                                HPTE_V_BOLTED, psize, psize,
298                                                ssize);
299                 if (ret == -1) {
300                         /*
301                          * Try to to keep bolted entries in primary.
302                          * Remove non bolted entries and try insert again
303                          */
304                         ret = mmu_hash_ops.hpte_remove(hpteg);
305                         if (ret != -1)
306                                 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
307                                                                HPTE_V_BOLTED, psize, psize,
308                                                                ssize);
309                         if (ret == -1 && !secondary_hash) {
310                                 secondary_hash = true;
311                                 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
312                                 goto repeat;
313                         }
314                 }
315 
316                 if (ret < 0)
317                         break;
318 
319                 cond_resched();
320 #ifdef CONFIG_DEBUG_PAGEALLOC
321                 if (debug_pagealloc_enabled() &&
322                         (paddr >> PAGE_SHIFT) < linear_map_hash_count)
323                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
324 #endif /* CONFIG_DEBUG_PAGEALLOC */
325         }
326         return ret < 0 ? ret : 0;
327 }
328 
329 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
330                       int psize, int ssize)
331 {
332         unsigned long vaddr;
333         unsigned int step, shift;
334         int rc;
335         int ret = 0;
336 
337         shift = mmu_psize_defs[psize].shift;
338         step = 1 << shift;
339 
340         if (!mmu_hash_ops.hpte_removebolted)
341                 return -ENODEV;
342 
343         for (vaddr = vstart; vaddr < vend; vaddr += step) {
344                 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
345                 if (rc == -ENOENT) {
346                         ret = -ENOENT;
347                         continue;
348                 }
349                 if (rc < 0)
350                         return rc;
351         }
352 
353         return ret;
354 }
355 
356 static bool disable_1tb_segments = false;
357 
358 static int __init parse_disable_1tb_segments(char *p)
359 {
360         disable_1tb_segments = true;
361         return 0;
362 }
363 early_param("disable_1tb_segments", parse_disable_1tb_segments);
364 
365 static int __init htab_dt_scan_seg_sizes(unsigned long node,
366                                          const char *uname, int depth,
367                                          void *data)
368 {
369         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
370         const __be32 *prop;
371         int size = 0;
372 
373         /* We are scanning "cpu" nodes only */
374         if (type == NULL || strcmp(type, "cpu") != 0)
375                 return 0;
376 
377         prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
378         if (prop == NULL)
379                 return 0;
380         for (; size >= 4; size -= 4, ++prop) {
381                 if (be32_to_cpu(prop[0]) == 40) {
382                         DBG("1T segment support detected\n");
383 
384                         if (disable_1tb_segments) {
385                                 DBG("1T segments disabled by command line\n");
386                                 break;
387                         }
388 
389                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
390                         return 1;
391                 }
392         }
393         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
394         return 0;
395 }
396 
397 static int __init get_idx_from_shift(unsigned int shift)
398 {
399         int idx = -1;
400 
401         switch (shift) {
402         case 0xc:
403                 idx = MMU_PAGE_4K;
404                 break;
405         case 0x10:
406                 idx = MMU_PAGE_64K;
407                 break;
408         case 0x14:
409                 idx = MMU_PAGE_1M;
410                 break;
411         case 0x18:
412                 idx = MMU_PAGE_16M;
413                 break;
414         case 0x22:
415                 idx = MMU_PAGE_16G;
416                 break;
417         }
418         return idx;
419 }
420 
421 static int __init htab_dt_scan_page_sizes(unsigned long node,
422                                           const char *uname, int depth,
423                                           void *data)
424 {
425         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
426         const __be32 *prop;
427         int size = 0;
428 
429         /* We are scanning "cpu" nodes only */
430         if (type == NULL || strcmp(type, "cpu") != 0)
431                 return 0;
432 
433         prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
434         if (!prop)
435                 return 0;
436 
437         pr_info("Page sizes from device-tree:\n");
438         size /= 4;
439         cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
440         while(size > 0) {
441                 unsigned int base_shift = be32_to_cpu(prop[0]);
442                 unsigned int slbenc = be32_to_cpu(prop[1]);
443                 unsigned int lpnum = be32_to_cpu(prop[2]);
444                 struct mmu_psize_def *def;
445                 int idx, base_idx;
446 
447                 size -= 3; prop += 3;
448                 base_idx = get_idx_from_shift(base_shift);
449                 if (base_idx < 0) {
450                         /* skip the pte encoding also */
451                         prop += lpnum * 2; size -= lpnum * 2;
452                         continue;
453                 }
454                 def = &mmu_psize_defs[base_idx];
455                 if (base_idx == MMU_PAGE_16M)
456                         cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
457 
458                 def->shift = base_shift;
459                 if (base_shift <= 23)
460                         def->avpnm = 0;
461                 else
462                         def->avpnm = (1 << (base_shift - 23)) - 1;
463                 def->sllp = slbenc;
464                 /*
465                  * We don't know for sure what's up with tlbiel, so
466                  * for now we only set it for 4K and 64K pages
467                  */
468                 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
469                         def->tlbiel = 1;
470                 else
471                         def->tlbiel = 0;
472 
473                 while (size > 0 && lpnum) {
474                         unsigned int shift = be32_to_cpu(prop[0]);
475                         int penc  = be32_to_cpu(prop[1]);
476 
477                         prop += 2; size -= 2;
478                         lpnum--;
479 
480                         idx = get_idx_from_shift(shift);
481                         if (idx < 0)
482                                 continue;
483 
484                         if (penc == -1)
485                                 pr_err("Invalid penc for base_shift=%d "
486                                        "shift=%d\n", base_shift, shift);
487 
488                         def->penc[idx] = penc;
489                         pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
490                                 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
491                                 base_shift, shift, def->sllp,
492                                 def->avpnm, def->tlbiel, def->penc[idx]);
493                 }
494         }
495 
496         return 1;
497 }
498 
499 #ifdef CONFIG_HUGETLB_PAGE
500 /*
501  * Scan for 16G memory blocks that have been set aside for huge pages
502  * and reserve those blocks for 16G huge pages.
503  */
504 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
505                                         const char *uname, int depth,
506                                         void *data) {
507         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
508         const __be64 *addr_prop;
509         const __be32 *page_count_prop;
510         unsigned int expected_pages;
511         long unsigned int phys_addr;
512         long unsigned int block_size;
513 
514         /* We are scanning "memory" nodes only */
515         if (type == NULL || strcmp(type, "memory") != 0)
516                 return 0;
517 
518         /*
519          * This property is the log base 2 of the number of virtual pages that
520          * will represent this memory block.
521          */
522         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
523         if (page_count_prop == NULL)
524                 return 0;
525         expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
526         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
527         if (addr_prop == NULL)
528                 return 0;
529         phys_addr = be64_to_cpu(addr_prop[0]);
530         block_size = be64_to_cpu(addr_prop[1]);
531         if (block_size != (16 * GB))
532                 return 0;
533         printk(KERN_INFO "Huge page(16GB) memory: "
534                         "addr = 0x%lX size = 0x%lX pages = %d\n",
535                         phys_addr, block_size, expected_pages);
536         if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
537                 memblock_reserve(phys_addr, block_size * expected_pages);
538                 pseries_add_gpage(phys_addr, block_size, expected_pages);
539         }
540         return 0;
541 }
542 #endif /* CONFIG_HUGETLB_PAGE */
543 
544 static void mmu_psize_set_default_penc(void)
545 {
546         int bpsize, apsize;
547         for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
548                 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
549                         mmu_psize_defs[bpsize].penc[apsize] = -1;
550 }
551 
552 #ifdef CONFIG_PPC_64K_PAGES
553 
554 static bool might_have_hea(void)
555 {
556         /*
557          * The HEA ethernet adapter requires awareness of the
558          * GX bus. Without that awareness we can easily assume
559          * we will never see an HEA ethernet device.
560          */
561 #ifdef CONFIG_IBMEBUS
562         return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
563                 firmware_has_feature(FW_FEATURE_SPLPAR);
564 #else
565         return false;
566 #endif
567 }
568 
569 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
570 
571 static void __init htab_scan_page_sizes(void)
572 {
573         int rc;
574 
575         /* se the invalid penc to -1 */
576         mmu_psize_set_default_penc();
577 
578         /* Default to 4K pages only */
579         memcpy(mmu_psize_defs, mmu_psize_defaults,
580                sizeof(mmu_psize_defaults));
581 
582         /*
583          * Try to find the available page sizes in the device-tree
584          */
585         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
586         if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
587                 /*
588                  * Nothing in the device-tree, but the CPU supports 16M pages,
589                  * so let's fallback on a known size list for 16M capable CPUs.
590                  */
591                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
592                        sizeof(mmu_psize_defaults_gp));
593         }
594 
595 #ifdef CONFIG_HUGETLB_PAGE
596         if (!hugetlb_disabled) {
597                 /* Reserve 16G huge page memory sections for huge pages */
598                 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
599         }
600 #endif /* CONFIG_HUGETLB_PAGE */
601 }
602 
603 /*
604  * Fill in the hpte_page_sizes[] array.
605  * We go through the mmu_psize_defs[] array looking for all the
606  * supported base/actual page size combinations.  Each combination
607  * has a unique pagesize encoding (penc) value in the low bits of
608  * the LP field of the HPTE.  For actual page sizes less than 1MB,
609  * some of the upper LP bits are used for RPN bits, meaning that
610  * we need to fill in several entries in hpte_page_sizes[].
611  *
612  * In diagrammatic form, with r = RPN bits and z = page size bits:
613  *        PTE LP     actual page size
614  *    rrrr rrrz         >=8KB
615  *    rrrr rrzz         >=16KB
616  *    rrrr rzzz         >=32KB
617  *    rrrr zzzz         >=64KB
618  *    ...
619  *
620  * The zzzz bits are implementation-specific but are chosen so that
621  * no encoding for a larger page size uses the same value in its
622  * low-order N bits as the encoding for the 2^(12+N) byte page size
623  * (if it exists).
624  */
625 static void init_hpte_page_sizes(void)
626 {
627         long int ap, bp;
628         long int shift, penc;
629 
630         for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
631                 if (!mmu_psize_defs[bp].shift)
632                         continue;       /* not a supported page size */
633                 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
634                         penc = mmu_psize_defs[bp].penc[ap];
635                         if (penc == -1 || !mmu_psize_defs[ap].shift)
636                                 continue;
637                         shift = mmu_psize_defs[ap].shift - LP_SHIFT;
638                         if (shift <= 0)
639                                 continue;       /* should never happen */
640                         /*
641                          * For page sizes less than 1MB, this loop
642                          * replicates the entry for all possible values
643                          * of the rrrr bits.
644                          */
645                         while (penc < (1 << LP_BITS)) {
646                                 hpte_page_sizes[penc] = (ap << 4) | bp;
647                                 penc += 1 << shift;
648                         }
649                 }
650         }
651 }
652 
653 static void __init htab_init_page_sizes(void)
654 {
655         bool aligned = true;
656         init_hpte_page_sizes();
657 
658         if (!debug_pagealloc_enabled()) {
659                 /*
660                  * Pick a size for the linear mapping. Currently, we only
661                  * support 16M, 1M and 4K which is the default
662                  */
663                 if (IS_ENABLED(STRICT_KERNEL_RWX) &&
664                     (unsigned long)_stext % 0x1000000) {
665                         if (mmu_psize_defs[MMU_PAGE_16M].shift)
666                                 pr_warn("Kernel not 16M aligned, "
667                                         "disabling 16M linear map alignment");
668                         aligned = false;
669                 }
670 
671                 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
672                         mmu_linear_psize = MMU_PAGE_16M;
673                 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
674                         mmu_linear_psize = MMU_PAGE_1M;
675         }
676 
677 #ifdef CONFIG_PPC_64K_PAGES
678         /*
679          * Pick a size for the ordinary pages. Default is 4K, we support
680          * 64K for user mappings and vmalloc if supported by the processor.
681          * We only use 64k for ioremap if the processor
682          * (and firmware) support cache-inhibited large pages.
683          * If not, we use 4k and set mmu_ci_restrictions so that
684          * hash_page knows to switch processes that use cache-inhibited
685          * mappings to 4k pages.
686          */
687         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
688                 mmu_virtual_psize = MMU_PAGE_64K;
689                 mmu_vmalloc_psize = MMU_PAGE_64K;
690                 if (mmu_linear_psize == MMU_PAGE_4K)
691                         mmu_linear_psize = MMU_PAGE_64K;
692                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
693                         /*
694                          * When running on pSeries using 64k pages for ioremap
695                          * would stop us accessing the HEA ethernet. So if we
696                          * have the chance of ever seeing one, stay at 4k.
697                          */
698                         if (!might_have_hea())
699                                 mmu_io_psize = MMU_PAGE_64K;
700                 } else
701                         mmu_ci_restrictions = 1;
702         }
703 #endif /* CONFIG_PPC_64K_PAGES */
704 
705 #ifdef CONFIG_SPARSEMEM_VMEMMAP
706         /*
707          * We try to use 16M pages for vmemmap if that is supported
708          * and we have at least 1G of RAM at boot
709          */
710         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
711             memblock_phys_mem_size() >= 0x40000000)
712                 mmu_vmemmap_psize = MMU_PAGE_16M;
713         else
714                 mmu_vmemmap_psize = mmu_virtual_psize;
715 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
716 
717         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
718                "virtual = %d, io = %d"
719 #ifdef CONFIG_SPARSEMEM_VMEMMAP
720                ", vmemmap = %d"
721 #endif
722                "\n",
723                mmu_psize_defs[mmu_linear_psize].shift,
724                mmu_psize_defs[mmu_virtual_psize].shift,
725                mmu_psize_defs[mmu_io_psize].shift
726 #ifdef CONFIG_SPARSEMEM_VMEMMAP
727                ,mmu_psize_defs[mmu_vmemmap_psize].shift
728 #endif
729                );
730 }
731 
732 static int __init htab_dt_scan_pftsize(unsigned long node,
733                                        const char *uname, int depth,
734                                        void *data)
735 {
736         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
737         const __be32 *prop;
738 
739         /* We are scanning "cpu" nodes only */
740         if (type == NULL || strcmp(type, "cpu") != 0)
741                 return 0;
742 
743         prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
744         if (prop != NULL) {
745                 /* pft_size[0] is the NUMA CEC cookie */
746                 ppc64_pft_size = be32_to_cpu(prop[1]);
747                 return 1;
748         }
749         return 0;
750 }
751 
752 unsigned htab_shift_for_mem_size(unsigned long mem_size)
753 {
754         unsigned memshift = __ilog2(mem_size);
755         unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
756         unsigned pteg_shift;
757 
758         /* round mem_size up to next power of 2 */
759         if ((1UL << memshift) < mem_size)
760                 memshift += 1;
761 
762         /* aim for 2 pages / pteg */
763         pteg_shift = memshift - (pshift + 1);
764 
765         /*
766          * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
767          * size permitted by the architecture.
768          */
769         return max(pteg_shift + 7, 18U);
770 }
771 
772 static unsigned long __init htab_get_table_size(void)
773 {
774         /*
775          * If hash size isn't already provided by the platform, we try to
776          * retrieve it from the device-tree. If it's not there neither, we
777          * calculate it now based on the total RAM size
778          */
779         if (ppc64_pft_size == 0)
780                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
781         if (ppc64_pft_size)
782                 return 1UL << ppc64_pft_size;
783 
784         return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
785 }
786 
787 #ifdef CONFIG_MEMORY_HOTPLUG
788 int resize_hpt_for_hotplug(unsigned long new_mem_size)
789 {
790         unsigned target_hpt_shift;
791 
792         if (!mmu_hash_ops.resize_hpt)
793                 return 0;
794 
795         target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
796 
797         /*
798          * To avoid lots of HPT resizes if memory size is fluctuating
799          * across a boundary, we deliberately have some hysterisis
800          * here: we immediately increase the HPT size if the target
801          * shift exceeds the current shift, but we won't attempt to
802          * reduce unless the target shift is at least 2 below the
803          * current shift
804          */
805         if (target_hpt_shift > ppc64_pft_size ||
806             target_hpt_shift < ppc64_pft_size - 1)
807                 return mmu_hash_ops.resize_hpt(target_hpt_shift);
808 
809         return 0;
810 }
811 
812 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
813 {
814         int rc;
815 
816         if (end >= H_VMALLOC_START) {
817                 pr_warn("Outside the supported range\n");
818                 return -1;
819         }
820 
821         rc = htab_bolt_mapping(start, end, __pa(start),
822                                pgprot_val(PAGE_KERNEL), mmu_linear_psize,
823                                mmu_kernel_ssize);
824 
825         if (rc < 0) {
826                 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
827                                               mmu_kernel_ssize);
828                 BUG_ON(rc2 && (rc2 != -ENOENT));
829         }
830         return rc;
831 }
832 
833 int hash__remove_section_mapping(unsigned long start, unsigned long end)
834 {
835         int rc = htab_remove_mapping(start, end, mmu_linear_psize,
836                                      mmu_kernel_ssize);
837         WARN_ON(rc < 0);
838         return rc;
839 }
840 #endif /* CONFIG_MEMORY_HOTPLUG */
841 
842 static void __init hash_init_partition_table(phys_addr_t hash_table,
843                                              unsigned long htab_size)
844 {
845         mmu_partition_table_init();
846 
847         /*
848          * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
849          * For now, UPRT is 0 and we have no segment table.
850          */
851         htab_size =  __ilog2(htab_size) - 18;
852         mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
853         pr_info("Partition table %p\n", partition_tb);
854 }
855 
856 static void __init htab_initialize(void)
857 {
858         unsigned long table;
859         unsigned long pteg_count;
860         unsigned long prot;
861         unsigned long base = 0, size = 0;
862         struct memblock_region *reg;
863 
864         DBG(" -> htab_initialize()\n");
865 
866         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
867                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
868                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
869                 printk(KERN_INFO "Using 1TB segments\n");
870         }
871 
872         /*
873          * Calculate the required size of the htab.  We want the number of
874          * PTEGs to equal one half the number of real pages.
875          */ 
876         htab_size_bytes = htab_get_table_size();
877         pteg_count = htab_size_bytes >> 7;
878 
879         htab_hash_mask = pteg_count - 1;
880 
881         if (firmware_has_feature(FW_FEATURE_LPAR) ||
882             firmware_has_feature(FW_FEATURE_PS3_LV1)) {
883                 /* Using a hypervisor which owns the htab */
884                 htab_address = NULL;
885                 _SDR1 = 0; 
886 #ifdef CONFIG_FA_DUMP
887                 /*
888                  * If firmware assisted dump is active firmware preserves
889                  * the contents of htab along with entire partition memory.
890                  * Clear the htab if firmware assisted dump is active so
891                  * that we dont end up using old mappings.
892                  */
893                 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
894                         mmu_hash_ops.hpte_clear_all();
895 #endif
896         } else {
897                 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
898 
899 #ifdef CONFIG_PPC_CELL
900                 /*
901                  * Cell may require the hash table down low when using the
902                  * Axon IOMMU in order to fit the dynamic region over it, see
903                  * comments in cell/iommu.c
904                  */
905                 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
906                         limit = 0x80000000;
907                         pr_info("Hash table forced below 2G for Axon IOMMU\n");
908                 }
909 #endif /* CONFIG_PPC_CELL */
910 
911                 table = memblock_phys_alloc_range(htab_size_bytes,
912                                                   htab_size_bytes,
913                                                   0, limit);
914                 if (!table)
915                         panic("ERROR: Failed to allocate %pa bytes below %pa\n",
916                               &htab_size_bytes, &limit);
917 
918                 DBG("Hash table allocated at %lx, size: %lx\n", table,
919                     htab_size_bytes);
920 
921                 htab_address = __va(table);
922 
923                 /* htab absolute addr + encoded htabsize */
924                 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
925 
926                 /* Initialize the HPT with no entries */
927                 memset((void *)table, 0, htab_size_bytes);
928 
929                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
930                         /* Set SDR1 */
931                         mtspr(SPRN_SDR1, _SDR1);
932                 else
933                         hash_init_partition_table(table, htab_size_bytes);
934         }
935 
936         prot = pgprot_val(PAGE_KERNEL);
937 
938 #ifdef CONFIG_DEBUG_PAGEALLOC
939         if (debug_pagealloc_enabled()) {
940                 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
941                 linear_map_hash_slots = memblock_alloc_try_nid(
942                                 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
943                                 ppc64_rma_size, NUMA_NO_NODE);
944                 if (!linear_map_hash_slots)
945                         panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
946                               __func__, linear_map_hash_count, &ppc64_rma_size);
947         }
948 #endif /* CONFIG_DEBUG_PAGEALLOC */
949 
950         /* create bolted the linear mapping in the hash table */
951         for_each_memblock(memory, reg) {
952                 base = (unsigned long)__va(reg->base);
953                 size = reg->size;
954 
955                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
956                     base, size, prot);
957 
958                 if ((base + size) >= H_VMALLOC_START) {
959                         pr_warn("Outside the supported range\n");
960                         continue;
961                 }
962 
963                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
964                                 prot, mmu_linear_psize, mmu_kernel_ssize));
965         }
966         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
967 
968         /*
969          * If we have a memory_limit and we've allocated TCEs then we need to
970          * explicitly map the TCE area at the top of RAM. We also cope with the
971          * case that the TCEs start below memory_limit.
972          * tce_alloc_start/end are 16MB aligned so the mapping should work
973          * for either 4K or 16MB pages.
974          */
975         if (tce_alloc_start) {
976                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
977                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
978 
979                 if (base + size >= tce_alloc_start)
980                         tce_alloc_start = base + size + 1;
981 
982                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
983                                          __pa(tce_alloc_start), prot,
984                                          mmu_linear_psize, mmu_kernel_ssize));
985         }
986 
987 
988         DBG(" <- htab_initialize()\n");
989 }
990 #undef KB
991 #undef MB
992 
993 void __init hash__early_init_devtree(void)
994 {
995         /* Initialize segment sizes */
996         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
997 
998         /* Initialize page sizes */
999         htab_scan_page_sizes();
1000 }
1001 
1002 static struct hash_mm_context init_hash_mm_context;
1003 void __init hash__early_init_mmu(void)
1004 {
1005 #ifndef CONFIG_PPC_64K_PAGES
1006         /*
1007          * We have code in __hash_page_4K() and elsewhere, which assumes it can
1008          * do the following:
1009          *   new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1010          *
1011          * Where the slot number is between 0-15, and values of 8-15 indicate
1012          * the secondary bucket. For that code to work H_PAGE_F_SECOND and
1013          * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1014          * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1015          * with a BUILD_BUG_ON().
1016          */
1017         BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul  << (H_PAGE_F_GIX_SHIFT + 3)));
1018 #endif /* CONFIG_PPC_64K_PAGES */
1019 
1020         htab_init_page_sizes();
1021 
1022         /*
1023          * initialize page table size
1024          */
1025         __pte_frag_nr = H_PTE_FRAG_NR;
1026         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1027         __pmd_frag_nr = H_PMD_FRAG_NR;
1028         __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1029 
1030         __pte_index_size = H_PTE_INDEX_SIZE;
1031         __pmd_index_size = H_PMD_INDEX_SIZE;
1032         __pud_index_size = H_PUD_INDEX_SIZE;
1033         __pgd_index_size = H_PGD_INDEX_SIZE;
1034         __pud_cache_index = H_PUD_CACHE_INDEX;
1035         __pte_table_size = H_PTE_TABLE_SIZE;
1036         __pmd_table_size = H_PMD_TABLE_SIZE;
1037         __pud_table_size = H_PUD_TABLE_SIZE;
1038         __pgd_table_size = H_PGD_TABLE_SIZE;
1039         /*
1040          * 4k use hugepd format, so for hash set then to
1041          * zero
1042          */
1043         __pmd_val_bits = HASH_PMD_VAL_BITS;
1044         __pud_val_bits = HASH_PUD_VAL_BITS;
1045         __pgd_val_bits = HASH_PGD_VAL_BITS;
1046 
1047         __kernel_virt_start = H_KERN_VIRT_START;
1048         __vmalloc_start = H_VMALLOC_START;
1049         __vmalloc_end = H_VMALLOC_END;
1050         __kernel_io_start = H_KERN_IO_START;
1051         __kernel_io_end = H_KERN_IO_END;
1052         vmemmap = (struct page *)H_VMEMMAP_START;
1053         ioremap_bot = IOREMAP_BASE;
1054 
1055 #ifdef CONFIG_PCI
1056         pci_io_base = ISA_IO_BASE;
1057 #endif
1058 
1059         /* Select appropriate backend */
1060         if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1061                 ps3_early_mm_init();
1062         else if (firmware_has_feature(FW_FEATURE_LPAR))
1063                 hpte_init_pseries();
1064         else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1065                 hpte_init_native();
1066 
1067         if (!mmu_hash_ops.hpte_insert)
1068                 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1069 
1070         /*
1071          * Initialize the MMU Hash table and create the linear mapping
1072          * of memory. Has to be done before SLB initialization as this is
1073          * currently where the page size encoding is obtained.
1074          */
1075         htab_initialize();
1076 
1077         init_mm.context.hash_context = &init_hash_mm_context;
1078         mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1079 
1080         pr_info("Initializing hash mmu with SLB\n");
1081         /* Initialize SLB management */
1082         slb_initialize();
1083 
1084         if (cpu_has_feature(CPU_FTR_ARCH_206)
1085                         && cpu_has_feature(CPU_FTR_HVMODE))
1086                 tlbiel_all();
1087 }
1088 
1089 #ifdef CONFIG_SMP
1090 void hash__early_init_mmu_secondary(void)
1091 {
1092         /* Initialize hash table for that CPU */
1093         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1094 
1095                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1096                         mtspr(SPRN_SDR1, _SDR1);
1097                 else
1098                         set_ptcr_when_no_uv(__pa(partition_tb) |
1099                                             (PATB_SIZE_SHIFT - 12));
1100         }
1101         /* Initialize SLB */
1102         slb_initialize();
1103 
1104         if (cpu_has_feature(CPU_FTR_ARCH_206)
1105                         && cpu_has_feature(CPU_FTR_HVMODE))
1106                 tlbiel_all();
1107 }
1108 #endif /* CONFIG_SMP */
1109 
1110 /*
1111  * Called by asm hashtable.S for doing lazy icache flush
1112  */
1113 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1114 {
1115         struct page *page;
1116 
1117         if (!pfn_valid(pte_pfn(pte)))
1118                 return pp;
1119 
1120         page = pte_page(pte);
1121 
1122         /* page is dirty */
1123         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1124                 if (trap == 0x400) {
1125                         flush_dcache_icache_page(page);
1126                         set_bit(PG_arch_1, &page->flags);
1127                 } else
1128                         pp |= HPTE_R_N;
1129         }
1130         return pp;
1131 }
1132 
1133 #ifdef CONFIG_PPC_MM_SLICES
1134 static unsigned int get_paca_psize(unsigned long addr)
1135 {
1136         unsigned char *psizes;
1137         unsigned long index, mask_index;
1138 
1139         if (addr < SLICE_LOW_TOP) {
1140                 psizes = get_paca()->mm_ctx_low_slices_psize;
1141                 index = GET_LOW_SLICE_INDEX(addr);
1142         } else {
1143                 psizes = get_paca()->mm_ctx_high_slices_psize;
1144                 index = GET_HIGH_SLICE_INDEX(addr);
1145         }
1146         mask_index = index & 0x1;
1147         return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1148 }
1149 
1150 #else
1151 unsigned int get_paca_psize(unsigned long addr)
1152 {
1153         return get_paca()->mm_ctx_user_psize;
1154 }
1155 #endif
1156 
1157 /*
1158  * Demote a segment to using 4k pages.
1159  * For now this makes the whole process use 4k pages.
1160  */
1161 #ifdef CONFIG_PPC_64K_PAGES
1162 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1163 {
1164         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1165                 return;
1166         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1167         copro_flush_all_slbs(mm);
1168         if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1169 
1170                 copy_mm_to_paca(mm);
1171                 slb_flush_and_restore_bolted();
1172         }
1173 }
1174 #endif /* CONFIG_PPC_64K_PAGES */
1175 
1176 #ifdef CONFIG_PPC_SUBPAGE_PROT
1177 /*
1178  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1179  * Userspace sets the subpage permissions using the subpage_prot system call.
1180  *
1181  * Result is 0: full permissions, _PAGE_RW: read-only,
1182  * _PAGE_RWX: no access.
1183  */
1184 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1185 {
1186         struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1187         u32 spp = 0;
1188         u32 **sbpm, *sbpp;
1189 
1190         if (!spt)
1191                 return 0;
1192 
1193         if (ea >= spt->maxaddr)
1194                 return 0;
1195         if (ea < 0x100000000UL) {
1196                 /* addresses below 4GB use spt->low_prot */
1197                 sbpm = spt->low_prot;
1198         } else {
1199                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1200                 if (!sbpm)
1201                         return 0;
1202         }
1203         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1204         if (!sbpp)
1205                 return 0;
1206         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1207 
1208         /* extract 2-bit bitfield for this 4k subpage */
1209         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1210 
1211         /*
1212          * 0 -> full premission
1213          * 1 -> Read only
1214          * 2 -> no access.
1215          * We return the flag that need to be cleared.
1216          */
1217         spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1218         return spp;
1219 }
1220 
1221 #else /* CONFIG_PPC_SUBPAGE_PROT */
1222 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1223 {
1224         return 0;
1225 }
1226 #endif
1227 
1228 void hash_failure_debug(unsigned long ea, unsigned long access,
1229                         unsigned long vsid, unsigned long trap,
1230                         int ssize, int psize, int lpsize, unsigned long pte)
1231 {
1232         if (!printk_ratelimit())
1233                 return;
1234         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1235                 ea, access, current->comm);
1236         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1237                 trap, vsid, ssize, psize, lpsize, pte);
1238 }
1239 
1240 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1241                              int psize, bool user_region)
1242 {
1243         if (user_region) {
1244                 if (psize != get_paca_psize(ea)) {
1245                         copy_mm_to_paca(mm);
1246                         slb_flush_and_restore_bolted();
1247                 }
1248         } else if (get_paca()->vmalloc_sllp !=
1249                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1250                 get_paca()->vmalloc_sllp =
1251                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1252                 slb_vmalloc_update();
1253         }
1254 }
1255 
1256 /*
1257  * Result code is:
1258  *  0 - handled
1259  *  1 - normal page fault
1260  * -1 - critical hash insertion error
1261  * -2 - access not permitted by subpage protection mechanism
1262  */
1263 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1264                  unsigned long access, unsigned long trap,
1265                  unsigned long flags)
1266 {
1267         bool is_thp;
1268         enum ctx_state prev_state = exception_enter();
1269         pgd_t *pgdir;
1270         unsigned long vsid;
1271         pte_t *ptep;
1272         unsigned hugeshift;
1273         int rc, user_region = 0;
1274         int psize, ssize;
1275 
1276         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1277                 ea, access, trap);
1278         trace_hash_fault(ea, access, trap);
1279 
1280         /* Get region & vsid */
1281         switch (get_region_id(ea)) {
1282         case USER_REGION_ID:
1283                 user_region = 1;
1284                 if (! mm) {
1285                         DBG_LOW(" user region with no mm !\n");
1286                         rc = 1;
1287                         goto bail;
1288                 }
1289                 psize = get_slice_psize(mm, ea);
1290                 ssize = user_segment_size(ea);
1291                 vsid = get_user_vsid(&mm->context, ea, ssize);
1292                 break;
1293         case VMALLOC_REGION_ID:
1294                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1295                 psize = mmu_vmalloc_psize;
1296                 ssize = mmu_kernel_ssize;
1297                 break;
1298 
1299         case IO_REGION_ID:
1300                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1301                 psize = mmu_io_psize;
1302                 ssize = mmu_kernel_ssize;
1303                 break;
1304         default:
1305                 /*
1306                  * Not a valid range
1307                  * Send the problem up to do_page_fault()
1308                  */
1309                 rc = 1;
1310                 goto bail;
1311         }
1312         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1313 
1314         /* Bad address. */
1315         if (!vsid) {
1316                 DBG_LOW("Bad address!\n");
1317                 rc = 1;
1318                 goto bail;
1319         }
1320         /* Get pgdir */
1321         pgdir = mm->pgd;
1322         if (pgdir == NULL) {
1323                 rc = 1;
1324                 goto bail;
1325         }
1326 
1327         /* Check CPU locality */
1328         if (user_region && mm_is_thread_local(mm))
1329                 flags |= HPTE_LOCAL_UPDATE;
1330 
1331 #ifndef CONFIG_PPC_64K_PAGES
1332         /*
1333          * If we use 4K pages and our psize is not 4K, then we might
1334          * be hitting a special driver mapping, and need to align the
1335          * address before we fetch the PTE.
1336          *
1337          * It could also be a hugepage mapping, in which case this is
1338          * not necessary, but it's not harmful, either.
1339          */
1340         if (psize != MMU_PAGE_4K)
1341                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1342 #endif /* CONFIG_PPC_64K_PAGES */
1343 
1344         /* Get PTE and page size from page tables */
1345         ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1346         if (ptep == NULL || !pte_present(*ptep)) {
1347                 DBG_LOW(" no PTE !\n");
1348                 rc = 1;
1349                 goto bail;
1350         }
1351 
1352         /* Add _PAGE_PRESENT to the required access perm */
1353         access |= _PAGE_PRESENT;
1354 
1355         /*
1356          * Pre-check access permissions (will be re-checked atomically
1357          * in __hash_page_XX but this pre-check is a fast path
1358          */
1359         if (!check_pte_access(access, pte_val(*ptep))) {
1360                 DBG_LOW(" no access !\n");
1361                 rc = 1;
1362                 goto bail;
1363         }
1364 
1365         if (hugeshift) {
1366                 if (is_thp)
1367                         rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1368                                              trap, flags, ssize, psize);
1369 #ifdef CONFIG_HUGETLB_PAGE
1370                 else
1371                         rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1372                                               flags, ssize, hugeshift, psize);
1373 #else
1374                 else {
1375                         /*
1376                          * if we have hugeshift, and is not transhuge with
1377                          * hugetlb disabled, something is really wrong.
1378                          */
1379                         rc = 1;
1380                         WARN_ON(1);
1381                 }
1382 #endif
1383                 if (current->mm == mm)
1384                         check_paca_psize(ea, mm, psize, user_region);
1385 
1386                 goto bail;
1387         }
1388 
1389 #ifndef CONFIG_PPC_64K_PAGES
1390         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1391 #else
1392         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1393                 pte_val(*(ptep + PTRS_PER_PTE)));
1394 #endif
1395         /* Do actual hashing */
1396 #ifdef CONFIG_PPC_64K_PAGES
1397         /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1398         if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1399                 demote_segment_4k(mm, ea);
1400                 psize = MMU_PAGE_4K;
1401         }
1402 
1403         /*
1404          * If this PTE is non-cacheable and we have restrictions on
1405          * using non cacheable large pages, then we switch to 4k
1406          */
1407         if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1408                 if (user_region) {
1409                         demote_segment_4k(mm, ea);
1410                         psize = MMU_PAGE_4K;
1411                 } else if (ea < VMALLOC_END) {
1412                         /*
1413                          * some driver did a non-cacheable mapping
1414                          * in vmalloc space, so switch vmalloc
1415                          * to 4k pages
1416                          */
1417                         printk(KERN_ALERT "Reducing vmalloc segment "
1418                                "to 4kB pages because of "
1419                                "non-cacheable mapping\n");
1420                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1421                         copro_flush_all_slbs(mm);
1422                 }
1423         }
1424 
1425 #endif /* CONFIG_PPC_64K_PAGES */
1426 
1427         if (current->mm == mm)
1428                 check_paca_psize(ea, mm, psize, user_region);
1429 
1430 #ifdef CONFIG_PPC_64K_PAGES
1431         if (psize == MMU_PAGE_64K)
1432                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1433                                      flags, ssize);
1434         else
1435 #endif /* CONFIG_PPC_64K_PAGES */
1436         {
1437                 int spp = subpage_protection(mm, ea);
1438                 if (access & spp)
1439                         rc = -2;
1440                 else
1441                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1442                                             flags, ssize, spp);
1443         }
1444 
1445         /*
1446          * Dump some info in case of hash insertion failure, they should
1447          * never happen so it is really useful to know if/when they do
1448          */
1449         if (rc == -1)
1450                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1451                                    psize, pte_val(*ptep));
1452 #ifndef CONFIG_PPC_64K_PAGES
1453         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1454 #else
1455         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1456                 pte_val(*(ptep + PTRS_PER_PTE)));
1457 #endif
1458         DBG_LOW(" -> rc=%d\n", rc);
1459 
1460 bail:
1461         exception_exit(prev_state);
1462         return rc;
1463 }
1464 EXPORT_SYMBOL_GPL(hash_page_mm);
1465 
1466 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1467               unsigned long dsisr)
1468 {
1469         unsigned long flags = 0;
1470         struct mm_struct *mm = current->mm;
1471 
1472         if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1473             (get_region_id(ea) == IO_REGION_ID))
1474                 mm = &init_mm;
1475 
1476         if (dsisr & DSISR_NOHPTE)
1477                 flags |= HPTE_NOHPTE_UPDATE;
1478 
1479         return hash_page_mm(mm, ea, access, trap, flags);
1480 }
1481 EXPORT_SYMBOL_GPL(hash_page);
1482 
1483 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1484                 unsigned long msr)
1485 {
1486         unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1487         unsigned long flags = 0;
1488         struct mm_struct *mm = current->mm;
1489         unsigned int region_id = get_region_id(ea);
1490 
1491         if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1492                 mm = &init_mm;
1493 
1494         if (dsisr & DSISR_NOHPTE)
1495                 flags |= HPTE_NOHPTE_UPDATE;
1496 
1497         if (dsisr & DSISR_ISSTORE)
1498                 access |= _PAGE_WRITE;
1499         /*
1500          * We set _PAGE_PRIVILEGED only when
1501          * kernel mode access kernel space.
1502          *
1503          * _PAGE_PRIVILEGED is NOT set
1504          * 1) when kernel mode access user space
1505          * 2) user space access kernel space.
1506          */
1507         access |= _PAGE_PRIVILEGED;
1508         if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1509                 access &= ~_PAGE_PRIVILEGED;
1510 
1511         if (trap == 0x400)
1512                 access |= _PAGE_EXEC;
1513 
1514         return hash_page_mm(mm, ea, access, trap, flags);
1515 }
1516 
1517 #ifdef CONFIG_PPC_MM_SLICES
1518 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1519 {
1520         int psize = get_slice_psize(mm, ea);
1521 
1522         /* We only prefault standard pages for now */
1523         if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1524                 return false;
1525 
1526         /*
1527          * Don't prefault if subpage protection is enabled for the EA.
1528          */
1529         if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1530                 return false;
1531 
1532         return true;
1533 }
1534 #else
1535 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1536 {
1537         return true;
1538 }
1539 #endif
1540 
1541 static void hash_preload(struct mm_struct *mm, unsigned long ea,
1542                          bool is_exec, unsigned long trap)
1543 {
1544         int hugepage_shift;
1545         unsigned long vsid;
1546         pgd_t *pgdir;
1547         pte_t *ptep;
1548         unsigned long flags;
1549         int rc, ssize, update_flags = 0;
1550         unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1551 
1552         BUG_ON(get_region_id(ea) != USER_REGION_ID);
1553 
1554         if (!should_hash_preload(mm, ea))
1555                 return;
1556 
1557         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1558                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1559 
1560         /* Get Linux PTE if available */
1561         pgdir = mm->pgd;
1562         if (pgdir == NULL)
1563                 return;
1564 
1565         /* Get VSID */
1566         ssize = user_segment_size(ea);
1567         vsid = get_user_vsid(&mm->context, ea, ssize);
1568         if (!vsid)
1569                 return;
1570         /*
1571          * Hash doesn't like irqs. Walking linux page table with irq disabled
1572          * saves us from holding multiple locks.
1573          */
1574         local_irq_save(flags);
1575 
1576         /*
1577          * THP pages use update_mmu_cache_pmd. We don't do
1578          * hash preload there. Hence can ignore THP here
1579          */
1580         ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1581         if (!ptep)
1582                 goto out_exit;
1583 
1584         WARN_ON(hugepage_shift);
1585 #ifdef CONFIG_PPC_64K_PAGES
1586         /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1587          * a 64K kernel), then we don't preload, hash_page() will take
1588          * care of it once we actually try to access the page.
1589          * That way we don't have to duplicate all of the logic for segment
1590          * page size demotion here
1591          */
1592         if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1593                 goto out_exit;
1594 #endif /* CONFIG_PPC_64K_PAGES */
1595 
1596         /* Is that local to this CPU ? */
1597         if (mm_is_thread_local(mm))
1598                 update_flags |= HPTE_LOCAL_UPDATE;
1599 
1600         /* Hash it in */
1601 #ifdef CONFIG_PPC_64K_PAGES
1602         if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1603                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1604                                      update_flags, ssize);
1605         else
1606 #endif /* CONFIG_PPC_64K_PAGES */
1607                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1608                                     ssize, subpage_protection(mm, ea));
1609 
1610         /* Dump some info in case of hash insertion failure, they should
1611          * never happen so it is really useful to know if/when they do
1612          */
1613         if (rc == -1)
1614                 hash_failure_debug(ea, access, vsid, trap, ssize,
1615                                    mm_ctx_user_psize(&mm->context),
1616                                    mm_ctx_user_psize(&mm->context),
1617                                    pte_val(*ptep));
1618 out_exit:
1619         local_irq_restore(flags);
1620 }
1621 
1622 /*
1623  * This is called at the end of handling a user page fault, when the
1624  * fault has been handled by updating a PTE in the linux page tables.
1625  * We use it to preload an HPTE into the hash table corresponding to
1626  * the updated linux PTE.
1627  *
1628  * This must always be called with the pte lock held.
1629  */
1630 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1631                       pte_t *ptep)
1632 {
1633         /*
1634          * We don't need to worry about _PAGE_PRESENT here because we are
1635          * called with either mm->page_table_lock held or ptl lock held
1636          */
1637         unsigned long trap;
1638         bool is_exec;
1639 
1640         if (radix_enabled()) {
1641                 prefetch((void *)address);
1642                 return;
1643         }
1644 
1645         /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1646         if (!pte_young(*ptep) || address >= TASK_SIZE)
1647                 return;
1648 
1649         /*
1650          * We try to figure out if we are coming from an instruction
1651          * access fault and pass that down to __hash_page so we avoid
1652          * double-faulting on execution of fresh text. We have to test
1653          * for regs NULL since init will get here first thing at boot.
1654          *
1655          * We also avoid filling the hash if not coming from a fault.
1656          */
1657 
1658         trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1659         switch (trap) {
1660         case 0x300:
1661                 is_exec = false;
1662                 break;
1663         case 0x400:
1664                 is_exec = true;
1665                 break;
1666         default:
1667                 return;
1668         }
1669 
1670         hash_preload(vma->vm_mm, address, is_exec, trap);
1671 }
1672 
1673 #ifdef CONFIG_PPC_MEM_KEYS
1674 /*
1675  * Return the protection key associated with the given address and the
1676  * mm_struct.
1677  */
1678 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1679 {
1680         pte_t *ptep;
1681         u16 pkey = 0;
1682         unsigned long flags;
1683 
1684         if (!mm || !mm->pgd)
1685                 return 0;
1686 
1687         local_irq_save(flags);
1688         ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1689         if (ptep)
1690                 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1691         local_irq_restore(flags);
1692 
1693         return pkey;
1694 }
1695 #endif /* CONFIG_PPC_MEM_KEYS */
1696 
1697 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1698 static inline void tm_flush_hash_page(int local)
1699 {
1700         /*
1701          * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1702          * page back to a block device w/PIO could pick up transactional data
1703          * (bad!) so we force an abort here. Before the sync the page will be
1704          * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1705          * kernel uses a page from userspace without unmapping it first, it may
1706          * see the speculated version.
1707          */
1708         if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1709             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1710                 tm_enable();
1711                 tm_abort(TM_CAUSE_TLBI);
1712         }
1713 }
1714 #else
1715 static inline void tm_flush_hash_page(int local)
1716 {
1717 }
1718 #endif
1719 
1720 /*
1721  * Return the global hash slot, corresponding to the given PTE, which contains
1722  * the HPTE.
1723  */
1724 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1725                 int ssize, real_pte_t rpte, unsigned int subpg_index)
1726 {
1727         unsigned long hash, gslot, hidx;
1728 
1729         hash = hpt_hash(vpn, shift, ssize);
1730         hidx = __rpte_to_hidx(rpte, subpg_index);
1731         if (hidx & _PTEIDX_SECONDARY)
1732                 hash = ~hash;
1733         gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1734         gslot += hidx & _PTEIDX_GROUP_IX;
1735         return gslot;
1736 }
1737 
1738 /*
1739  * WARNING: This is called from hash_low_64.S, if you change this prototype,
1740  *          do not forget to update the assembly call site !
1741  */
1742 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1743                      unsigned long flags)
1744 {
1745         unsigned long index, shift, gslot;
1746         int local = flags & HPTE_LOCAL_UPDATE;
1747 
1748         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1749         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1750                 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1751                 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1752                 /*
1753                  * We use same base page size and actual psize, because we don't
1754                  * use these functions for hugepage
1755                  */
1756                 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1757                                              ssize, local);
1758         } pte_iterate_hashed_end();
1759 
1760         tm_flush_hash_page(local);
1761 }
1762 
1763 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1764 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1765                          pmd_t *pmdp, unsigned int psize, int ssize,
1766                          unsigned long flags)
1767 {
1768         int i, max_hpte_count, valid;
1769         unsigned long s_addr;
1770         unsigned char *hpte_slot_array;
1771         unsigned long hidx, shift, vpn, hash, slot;
1772         int local = flags & HPTE_LOCAL_UPDATE;
1773 
1774         s_addr = addr & HPAGE_PMD_MASK;
1775         hpte_slot_array = get_hpte_slot_array(pmdp);
1776         /*
1777          * IF we try to do a HUGE PTE update after a withdraw is done.
1778          * we will find the below NULL. This happens when we do
1779          * split_huge_pmd
1780          */
1781         if (!hpte_slot_array)
1782                 return;
1783 
1784         if (mmu_hash_ops.hugepage_invalidate) {
1785                 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1786                                                  psize, ssize, local);
1787                 goto tm_abort;
1788         }
1789         /*
1790          * No bluk hpte removal support, invalidate each entry
1791          */
1792         shift = mmu_psize_defs[psize].shift;
1793         max_hpte_count = HPAGE_PMD_SIZE >> shift;
1794         for (i = 0; i < max_hpte_count; i++) {
1795                 /*
1796                  * 8 bits per each hpte entries
1797                  * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1798                  */
1799                 valid = hpte_valid(hpte_slot_array, i);
1800                 if (!valid)
1801                         continue;
1802                 hidx =  hpte_hash_index(hpte_slot_array, i);
1803 
1804                 /* get the vpn */
1805                 addr = s_addr + (i * (1ul << shift));
1806                 vpn = hpt_vpn(addr, vsid, ssize);
1807                 hash = hpt_hash(vpn, shift, ssize);
1808                 if (hidx & _PTEIDX_SECONDARY)
1809                         hash = ~hash;
1810 
1811                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1812                 slot += hidx & _PTEIDX_GROUP_IX;
1813                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1814                                              MMU_PAGE_16M, ssize, local);
1815         }
1816 tm_abort:
1817         tm_flush_hash_page(local);
1818 }
1819 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1820 
1821 void flush_hash_range(unsigned long number, int local)
1822 {
1823         if (mmu_hash_ops.flush_hash_range)
1824                 mmu_hash_ops.flush_hash_range(number, local);
1825         else {
1826                 int i;
1827                 struct ppc64_tlb_batch *batch =
1828                         this_cpu_ptr(&ppc64_tlb_batch);
1829 
1830                 for (i = 0; i < number; i++)
1831                         flush_hash_page(batch->vpn[i], batch->pte[i],
1832                                         batch->psize, batch->ssize, local);
1833         }
1834 }
1835 
1836 /*
1837  * low_hash_fault is called when we the low level hash code failed
1838  * to instert a PTE due to an hypervisor error
1839  */
1840 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1841 {
1842         enum ctx_state prev_state = exception_enter();
1843 
1844         if (user_mode(regs)) {
1845 #ifdef CONFIG_PPC_SUBPAGE_PROT
1846                 if (rc == -2)
1847                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1848                 else
1849 #endif
1850                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1851         } else
1852                 bad_page_fault(regs, address, SIGBUS);
1853 
1854         exception_exit(prev_state);
1855 }
1856 
1857 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1858                            unsigned long pa, unsigned long rflags,
1859                            unsigned long vflags, int psize, int ssize)
1860 {
1861         unsigned long hpte_group;
1862         long slot;
1863 
1864 repeat:
1865         hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1866 
1867         /* Insert into the hash table, primary slot */
1868         slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1869                                         psize, psize, ssize);
1870 
1871         /* Primary is full, try the secondary */
1872         if (unlikely(slot == -1)) {
1873                 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1874                 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1875                                                 vflags | HPTE_V_SECONDARY,
1876                                                 psize, psize, ssize);
1877                 if (slot == -1) {
1878                         if (mftb() & 0x1)
1879                                 hpte_group = (hash & htab_hash_mask) *
1880                                                 HPTES_PER_GROUP;
1881 
1882                         mmu_hash_ops.hpte_remove(hpte_group);
1883                         goto repeat;
1884                 }
1885         }
1886 
1887         return slot;
1888 }
1889 
1890 #ifdef CONFIG_DEBUG_PAGEALLOC
1891 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1892 {
1893         unsigned long hash;
1894         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1895         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1896         unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1897         long ret;
1898 
1899         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1900 
1901         /* Don't create HPTE entries for bad address */
1902         if (!vsid)
1903                 return;
1904 
1905         ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1906                                     HPTE_V_BOLTED,
1907                                     mmu_linear_psize, mmu_kernel_ssize);
1908 
1909         BUG_ON (ret < 0);
1910         spin_lock(&linear_map_hash_lock);
1911         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1912         linear_map_hash_slots[lmi] = ret | 0x80;
1913         spin_unlock(&linear_map_hash_lock);
1914 }
1915 
1916 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1917 {
1918         unsigned long hash, hidx, slot;
1919         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1920         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1921 
1922         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1923         spin_lock(&linear_map_hash_lock);
1924         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1925         hidx = linear_map_hash_slots[lmi] & 0x7f;
1926         linear_map_hash_slots[lmi] = 0;
1927         spin_unlock(&linear_map_hash_lock);
1928         if (hidx & _PTEIDX_SECONDARY)
1929                 hash = ~hash;
1930         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1931         slot += hidx & _PTEIDX_GROUP_IX;
1932         mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1933                                      mmu_linear_psize,
1934                                      mmu_kernel_ssize, 0);
1935 }
1936 
1937 void __kernel_map_pages(struct page *page, int numpages, int enable)
1938 {
1939         unsigned long flags, vaddr, lmi;
1940         int i;
1941 
1942         local_irq_save(flags);
1943         for (i = 0; i < numpages; i++, page++) {
1944                 vaddr = (unsigned long)page_address(page);
1945                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1946                 if (lmi >= linear_map_hash_count)
1947                         continue;
1948                 if (enable)
1949                         kernel_map_linear_page(vaddr, lmi);
1950                 else
1951                         kernel_unmap_linear_page(vaddr, lmi);
1952         }
1953         local_irq_restore(flags);
1954 }
1955 #endif /* CONFIG_DEBUG_PAGEALLOC */
1956 
1957 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1958                                 phys_addr_t first_memblock_size)
1959 {
1960         /*
1961          * We don't currently support the first MEMBLOCK not mapping 0
1962          * physical on those processors
1963          */
1964         BUG_ON(first_memblock_base != 0);
1965 
1966         /*
1967          * On virtualized systems the first entry is our RMA region aka VRMA,
1968          * non-virtualized 64-bit hash MMU systems don't have a limitation
1969          * on real mode access.
1970          *
1971          * For guests on platforms before POWER9, we clamp the it limit to 1G
1972          * to avoid some funky things such as RTAS bugs etc...
1973          *
1974          * On POWER9 we limit to 1TB in case the host erroneously told us that
1975          * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1976          * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1977          * for virtual real mode addressing and so it doesn't make sense to
1978          * have an area larger than 1TB as it can't be addressed.
1979          */
1980         if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1981                 ppc64_rma_size = first_memblock_size;
1982                 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1983                         ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1984                 else
1985                         ppc64_rma_size = min_t(u64, ppc64_rma_size,
1986                                                1UL << SID_SHIFT_1T);
1987 
1988                 /* Finally limit subsequent allocations */
1989                 memblock_set_current_limit(ppc64_rma_size);
1990         } else {
1991                 ppc64_rma_size = ULONG_MAX;
1992         }
1993 }
1994 
1995 #ifdef CONFIG_DEBUG_FS
1996 
1997 static int hpt_order_get(void *data, u64 *val)
1998 {
1999         *val = ppc64_pft_size;
2000         return 0;
2001 }
2002 
2003 static int hpt_order_set(void *data, u64 val)
2004 {
2005         int ret;
2006 
2007         if (!mmu_hash_ops.resize_hpt)
2008                 return -ENODEV;
2009 
2010         cpus_read_lock();
2011         ret = mmu_hash_ops.resize_hpt(val);
2012         cpus_read_unlock();
2013 
2014         return ret;
2015 }
2016 
2017 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2018 
2019 static int __init hash64_debugfs(void)
2020 {
2021         if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
2022                                         NULL, &fops_hpt_order)) {
2023                 pr_err("lpar: unable to create hpt_order debugsfs file\n");
2024         }
2025 
2026         return 0;
2027 }
2028 machine_device_initcall(pseries, hash64_debugfs);
2029 #endif /* CONFIG_DEBUG_FS */
2030 
2031 void __init print_system_hash_info(void)
2032 {
2033         pr_info("ppc64_pft_size    = 0x%llx\n", ppc64_pft_size);
2034 
2035         if (htab_hash_mask)
2036                 pr_info("htab_hash_mask    = 0x%lx\n", htab_hash_mask);
2037 }
2038 

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