~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/powerpc/mm/hash_utils_64.c

Version: ~ [ linux-5.3-rc5 ] ~ [ linux-5.2.9 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.67 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.139 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.189 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.189 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.72 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
  3  *   {mikejc|engebret}@us.ibm.com
  4  *
  5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
  6  *
  7  * SMP scalability work:
  8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  9  * 
 10  *    Module name: htab.c
 11  *
 12  *    Description:
 13  *      PowerPC Hashed Page Table functions
 14  *
 15  * This program is free software; you can redistribute it and/or
 16  * modify it under the terms of the GNU General Public License
 17  * as published by the Free Software Foundation; either version
 18  * 2 of the License, or (at your option) any later version.
 19  */
 20 
 21 #undef DEBUG
 22 #undef DEBUG_LOW
 23 
 24 #include <linux/spinlock.h>
 25 #include <linux/errno.h>
 26 #include <linux/sched/mm.h>
 27 #include <linux/proc_fs.h>
 28 #include <linux/stat.h>
 29 #include <linux/sysctl.h>
 30 #include <linux/export.h>
 31 #include <linux/ctype.h>
 32 #include <linux/cache.h>
 33 #include <linux/init.h>
 34 #include <linux/signal.h>
 35 #include <linux/memblock.h>
 36 #include <linux/context_tracking.h>
 37 #include <linux/libfdt.h>
 38 #include <linux/debugfs.h>
 39 
 40 #include <asm/debug.h>
 41 #include <asm/processor.h>
 42 #include <asm/pgtable.h>
 43 #include <asm/mmu.h>
 44 #include <asm/mmu_context.h>
 45 #include <asm/page.h>
 46 #include <asm/types.h>
 47 #include <linux/uaccess.h>
 48 #include <asm/machdep.h>
 49 #include <asm/prom.h>
 50 #include <asm/tlbflush.h>
 51 #include <asm/io.h>
 52 #include <asm/eeh.h>
 53 #include <asm/tlb.h>
 54 #include <asm/cacheflush.h>
 55 #include <asm/cputable.h>
 56 #include <asm/sections.h>
 57 #include <asm/copro.h>
 58 #include <asm/udbg.h>
 59 #include <asm/code-patching.h>
 60 #include <asm/fadump.h>
 61 #include <asm/firmware.h>
 62 #include <asm/tm.h>
 63 #include <asm/trace.h>
 64 #include <asm/ps3.h>
 65 
 66 #ifdef DEBUG
 67 #define DBG(fmt...) udbg_printf(fmt)
 68 #else
 69 #define DBG(fmt...)
 70 #endif
 71 
 72 #ifdef DEBUG_LOW
 73 #define DBG_LOW(fmt...) udbg_printf(fmt)
 74 #else
 75 #define DBG_LOW(fmt...)
 76 #endif
 77 
 78 #define KB (1024)
 79 #define MB (1024*KB)
 80 #define GB (1024L*MB)
 81 
 82 /*
 83  * Note:  pte   --> Linux PTE
 84  *        HPTE  --> PowerPC Hashed Page Table Entry
 85  *
 86  * Execution context:
 87  *   htab_initialize is called with the MMU off (of course), but
 88  *   the kernel has been copied down to zero so it can directly
 89  *   reference global data.  At this point it is very difficult
 90  *   to print debug info.
 91  *
 92  */
 93 
 94 static unsigned long _SDR1;
 95 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 96 EXPORT_SYMBOL_GPL(mmu_psize_defs);
 97 
 98 u8 hpte_page_sizes[1 << LP_BITS];
 99 EXPORT_SYMBOL_GPL(hpte_page_sizes);
100 
101 struct hash_pte *htab_address;
102 unsigned long htab_size_bytes;
103 unsigned long htab_hash_mask;
104 EXPORT_SYMBOL_GPL(htab_hash_mask);
105 int mmu_linear_psize = MMU_PAGE_4K;
106 EXPORT_SYMBOL_GPL(mmu_linear_psize);
107 int mmu_virtual_psize = MMU_PAGE_4K;
108 int mmu_vmalloc_psize = MMU_PAGE_4K;
109 #ifdef CONFIG_SPARSEMEM_VMEMMAP
110 int mmu_vmemmap_psize = MMU_PAGE_4K;
111 #endif
112 int mmu_io_psize = MMU_PAGE_4K;
113 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
114 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
115 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
116 u16 mmu_slb_size = 64;
117 EXPORT_SYMBOL_GPL(mmu_slb_size);
118 #ifdef CONFIG_PPC_64K_PAGES
119 int mmu_ci_restrictions;
120 #endif
121 #ifdef CONFIG_DEBUG_PAGEALLOC
122 static u8 *linear_map_hash_slots;
123 static unsigned long linear_map_hash_count;
124 static DEFINE_SPINLOCK(linear_map_hash_lock);
125 #endif /* CONFIG_DEBUG_PAGEALLOC */
126 struct mmu_hash_ops mmu_hash_ops;
127 EXPORT_SYMBOL(mmu_hash_ops);
128 
129 /* There are definitions of page sizes arrays to be used when none
130  * is provided by the firmware.
131  */
132 
133 /* Pre-POWER4 CPUs (4k pages only)
134  */
135 static struct mmu_psize_def mmu_psize_defaults_old[] = {
136         [MMU_PAGE_4K] = {
137                 .shift  = 12,
138                 .sllp   = 0,
139                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
140                 .avpnm  = 0,
141                 .tlbiel = 0,
142         },
143 };
144 
145 /* POWER4, GPUL, POWER5
146  *
147  * Support for 16Mb large pages
148  */
149 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
150         [MMU_PAGE_4K] = {
151                 .shift  = 12,
152                 .sllp   = 0,
153                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
154                 .avpnm  = 0,
155                 .tlbiel = 1,
156         },
157         [MMU_PAGE_16M] = {
158                 .shift  = 24,
159                 .sllp   = SLB_VSID_L,
160                 .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
161                             [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
162                 .avpnm  = 0x1UL,
163                 .tlbiel = 0,
164         },
165 };
166 
167 /*
168  * 'R' and 'C' update notes:
169  *  - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
170  *     create writeable HPTEs without C set, because the hcall H_PROTECT
171  *     that we use in that case will not update C
172  *  - The above is however not a problem, because we also don't do that
173  *     fancy "no flush" variant of eviction and we use H_REMOVE which will
174  *     do the right thing and thus we don't have the race I described earlier
175  *
176  *    - Under bare metal,  we do have the race, so we need R and C set
177  *    - We make sure R is always set and never lost
178  *    - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
179  */
180 unsigned long htab_convert_pte_flags(unsigned long pteflags)
181 {
182         unsigned long rflags = 0;
183 
184         /* _PAGE_EXEC -> NOEXEC */
185         if ((pteflags & _PAGE_EXEC) == 0)
186                 rflags |= HPTE_R_N;
187         /*
188          * PPP bits:
189          * Linux uses slb key 0 for kernel and 1 for user.
190          * kernel RW areas are mapped with PPP=0b000
191          * User area is mapped with PPP=0b010 for read/write
192          * or PPP=0b011 for read-only (including writeable but clean pages).
193          */
194         if (pteflags & _PAGE_PRIVILEGED) {
195                 /*
196                  * Kernel read only mapped with ppp bits 0b110
197                  */
198                 if (!(pteflags & _PAGE_WRITE)) {
199                         if (mmu_has_feature(MMU_FTR_KERNEL_RO))
200                                 rflags |= (HPTE_R_PP0 | 0x2);
201                         else
202                                 rflags |= 0x3;
203                 }
204         } else {
205                 if (pteflags & _PAGE_RWX)
206                         rflags |= 0x2;
207                 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
208                         rflags |= 0x1;
209         }
210         /*
211          * We can't allow hardware to update hpte bits. Hence always
212          * set 'R' bit and set 'C' if it is a write fault
213          */
214         rflags |=  HPTE_R_R;
215 
216         if (pteflags & _PAGE_DIRTY)
217                 rflags |= HPTE_R_C;
218         /*
219          * Add in WIG bits
220          */
221 
222         if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
223                 rflags |= HPTE_R_I;
224         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
225                 rflags |= (HPTE_R_I | HPTE_R_G);
226         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
227                 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
228         else
229                 /*
230                  * Add memory coherence if cache inhibited is not set
231                  */
232                 rflags |= HPTE_R_M;
233 
234         return rflags;
235 }
236 
237 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
238                       unsigned long pstart, unsigned long prot,
239                       int psize, int ssize)
240 {
241         unsigned long vaddr, paddr;
242         unsigned int step, shift;
243         int ret = 0;
244 
245         shift = mmu_psize_defs[psize].shift;
246         step = 1 << shift;
247 
248         prot = htab_convert_pte_flags(prot);
249 
250         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
251             vstart, vend, pstart, prot, psize, ssize);
252 
253         for (vaddr = vstart, paddr = pstart; vaddr < vend;
254              vaddr += step, paddr += step) {
255                 unsigned long hash, hpteg;
256                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
257                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
258                 unsigned long tprot = prot;
259 
260                 /*
261                  * If we hit a bad address return error.
262                  */
263                 if (!vsid)
264                         return -1;
265                 /* Make kernel text executable */
266                 if (overlaps_kernel_text(vaddr, vaddr + step))
267                         tprot &= ~HPTE_R_N;
268 
269                 /* Make kvm guest trampolines executable */
270                 if (overlaps_kvm_tmp(vaddr, vaddr + step))
271                         tprot &= ~HPTE_R_N;
272 
273                 /*
274                  * If relocatable, check if it overlaps interrupt vectors that
275                  * are copied down to real 0. For relocatable kernel
276                  * (e.g. kdump case) we copy interrupt vectors down to real
277                  * address 0. Mark that region as executable. This is
278                  * because on p8 system with relocation on exception feature
279                  * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
280                  * in order to execute the interrupt handlers in virtual
281                  * mode the vector region need to be marked as executable.
282                  */
283                 if ((PHYSICAL_START > MEMORY_START) &&
284                         overlaps_interrupt_vector_text(vaddr, vaddr + step))
285                                 tprot &= ~HPTE_R_N;
286 
287                 hash = hpt_hash(vpn, shift, ssize);
288                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
289 
290                 BUG_ON(!mmu_hash_ops.hpte_insert);
291                 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
292                                                HPTE_V_BOLTED, psize, psize,
293                                                ssize);
294 
295                 if (ret < 0)
296                         break;
297 
298 #ifdef CONFIG_DEBUG_PAGEALLOC
299                 if (debug_pagealloc_enabled() &&
300                         (paddr >> PAGE_SHIFT) < linear_map_hash_count)
301                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
302 #endif /* CONFIG_DEBUG_PAGEALLOC */
303         }
304         return ret < 0 ? ret : 0;
305 }
306 
307 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
308                       int psize, int ssize)
309 {
310         unsigned long vaddr;
311         unsigned int step, shift;
312         int rc;
313         int ret = 0;
314 
315         shift = mmu_psize_defs[psize].shift;
316         step = 1 << shift;
317 
318         if (!mmu_hash_ops.hpte_removebolted)
319                 return -ENODEV;
320 
321         for (vaddr = vstart; vaddr < vend; vaddr += step) {
322                 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
323                 if (rc == -ENOENT) {
324                         ret = -ENOENT;
325                         continue;
326                 }
327                 if (rc < 0)
328                         return rc;
329         }
330 
331         return ret;
332 }
333 
334 static bool disable_1tb_segments = false;
335 
336 static int __init parse_disable_1tb_segments(char *p)
337 {
338         disable_1tb_segments = true;
339         return 0;
340 }
341 early_param("disable_1tb_segments", parse_disable_1tb_segments);
342 
343 static int __init htab_dt_scan_seg_sizes(unsigned long node,
344                                          const char *uname, int depth,
345                                          void *data)
346 {
347         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
348         const __be32 *prop;
349         int size = 0;
350 
351         /* We are scanning "cpu" nodes only */
352         if (type == NULL || strcmp(type, "cpu") != 0)
353                 return 0;
354 
355         prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
356         if (prop == NULL)
357                 return 0;
358         for (; size >= 4; size -= 4, ++prop) {
359                 if (be32_to_cpu(prop[0]) == 40) {
360                         DBG("1T segment support detected\n");
361 
362                         if (disable_1tb_segments) {
363                                 DBG("1T segments disabled by command line\n");
364                                 break;
365                         }
366 
367                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
368                         return 1;
369                 }
370         }
371         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
372         return 0;
373 }
374 
375 static int __init get_idx_from_shift(unsigned int shift)
376 {
377         int idx = -1;
378 
379         switch (shift) {
380         case 0xc:
381                 idx = MMU_PAGE_4K;
382                 break;
383         case 0x10:
384                 idx = MMU_PAGE_64K;
385                 break;
386         case 0x14:
387                 idx = MMU_PAGE_1M;
388                 break;
389         case 0x18:
390                 idx = MMU_PAGE_16M;
391                 break;
392         case 0x22:
393                 idx = MMU_PAGE_16G;
394                 break;
395         }
396         return idx;
397 }
398 
399 static int __init htab_dt_scan_page_sizes(unsigned long node,
400                                           const char *uname, int depth,
401                                           void *data)
402 {
403         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
404         const __be32 *prop;
405         int size = 0;
406 
407         /* We are scanning "cpu" nodes only */
408         if (type == NULL || strcmp(type, "cpu") != 0)
409                 return 0;
410 
411         prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
412         if (!prop)
413                 return 0;
414 
415         pr_info("Page sizes from device-tree:\n");
416         size /= 4;
417         cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
418         while(size > 0) {
419                 unsigned int base_shift = be32_to_cpu(prop[0]);
420                 unsigned int slbenc = be32_to_cpu(prop[1]);
421                 unsigned int lpnum = be32_to_cpu(prop[2]);
422                 struct mmu_psize_def *def;
423                 int idx, base_idx;
424 
425                 size -= 3; prop += 3;
426                 base_idx = get_idx_from_shift(base_shift);
427                 if (base_idx < 0) {
428                         /* skip the pte encoding also */
429                         prop += lpnum * 2; size -= lpnum * 2;
430                         continue;
431                 }
432                 def = &mmu_psize_defs[base_idx];
433                 if (base_idx == MMU_PAGE_16M)
434                         cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
435 
436                 def->shift = base_shift;
437                 if (base_shift <= 23)
438                         def->avpnm = 0;
439                 else
440                         def->avpnm = (1 << (base_shift - 23)) - 1;
441                 def->sllp = slbenc;
442                 /*
443                  * We don't know for sure what's up with tlbiel, so
444                  * for now we only set it for 4K and 64K pages
445                  */
446                 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
447                         def->tlbiel = 1;
448                 else
449                         def->tlbiel = 0;
450 
451                 while (size > 0 && lpnum) {
452                         unsigned int shift = be32_to_cpu(prop[0]);
453                         int penc  = be32_to_cpu(prop[1]);
454 
455                         prop += 2; size -= 2;
456                         lpnum--;
457 
458                         idx = get_idx_from_shift(shift);
459                         if (idx < 0)
460                                 continue;
461 
462                         if (penc == -1)
463                                 pr_err("Invalid penc for base_shift=%d "
464                                        "shift=%d\n", base_shift, shift);
465 
466                         def->penc[idx] = penc;
467                         pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
468                                 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
469                                 base_shift, shift, def->sllp,
470                                 def->avpnm, def->tlbiel, def->penc[idx]);
471                 }
472         }
473 
474         return 1;
475 }
476 
477 #ifdef CONFIG_HUGETLB_PAGE
478 /* Scan for 16G memory blocks that have been set aside for huge pages
479  * and reserve those blocks for 16G huge pages.
480  */
481 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
482                                         const char *uname, int depth,
483                                         void *data) {
484         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
485         const __be64 *addr_prop;
486         const __be32 *page_count_prop;
487         unsigned int expected_pages;
488         long unsigned int phys_addr;
489         long unsigned int block_size;
490 
491         /* We are scanning "memory" nodes only */
492         if (type == NULL || strcmp(type, "memory") != 0)
493                 return 0;
494 
495         /* This property is the log base 2 of the number of virtual pages that
496          * will represent this memory block. */
497         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
498         if (page_count_prop == NULL)
499                 return 0;
500         expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
501         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
502         if (addr_prop == NULL)
503                 return 0;
504         phys_addr = be64_to_cpu(addr_prop[0]);
505         block_size = be64_to_cpu(addr_prop[1]);
506         if (block_size != (16 * GB))
507                 return 0;
508         printk(KERN_INFO "Huge page(16GB) memory: "
509                         "addr = 0x%lX size = 0x%lX pages = %d\n",
510                         phys_addr, block_size, expected_pages);
511         if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
512                 memblock_reserve(phys_addr, block_size * expected_pages);
513                 add_gpage(phys_addr, block_size, expected_pages);
514         }
515         return 0;
516 }
517 #endif /* CONFIG_HUGETLB_PAGE */
518 
519 static void mmu_psize_set_default_penc(void)
520 {
521         int bpsize, apsize;
522         for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
523                 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
524                         mmu_psize_defs[bpsize].penc[apsize] = -1;
525 }
526 
527 #ifdef CONFIG_PPC_64K_PAGES
528 
529 static bool might_have_hea(void)
530 {
531         /*
532          * The HEA ethernet adapter requires awareness of the
533          * GX bus. Without that awareness we can easily assume
534          * we will never see an HEA ethernet device.
535          */
536 #ifdef CONFIG_IBMEBUS
537         return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
538                 firmware_has_feature(FW_FEATURE_SPLPAR);
539 #else
540         return false;
541 #endif
542 }
543 
544 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
545 
546 static void __init htab_scan_page_sizes(void)
547 {
548         int rc;
549 
550         /* se the invalid penc to -1 */
551         mmu_psize_set_default_penc();
552 
553         /* Default to 4K pages only */
554         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
555                sizeof(mmu_psize_defaults_old));
556 
557         /*
558          * Try to find the available page sizes in the device-tree
559          */
560         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
561         if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
562                 /*
563                  * Nothing in the device-tree, but the CPU supports 16M pages,
564                  * so let's fallback on a known size list for 16M capable CPUs.
565                  */
566                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
567                        sizeof(mmu_psize_defaults_gp));
568         }
569 
570 #ifdef CONFIG_HUGETLB_PAGE
571         /* Reserve 16G huge page memory sections for huge pages */
572         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
573 #endif /* CONFIG_HUGETLB_PAGE */
574 }
575 
576 /*
577  * Fill in the hpte_page_sizes[] array.
578  * We go through the mmu_psize_defs[] array looking for all the
579  * supported base/actual page size combinations.  Each combination
580  * has a unique pagesize encoding (penc) value in the low bits of
581  * the LP field of the HPTE.  For actual page sizes less than 1MB,
582  * some of the upper LP bits are used for RPN bits, meaning that
583  * we need to fill in several entries in hpte_page_sizes[].
584  *
585  * In diagrammatic form, with r = RPN bits and z = page size bits:
586  *        PTE LP     actual page size
587  *    rrrr rrrz         >=8KB
588  *    rrrr rrzz         >=16KB
589  *    rrrr rzzz         >=32KB
590  *    rrrr zzzz         >=64KB
591  *    ...
592  *
593  * The zzzz bits are implementation-specific but are chosen so that
594  * no encoding for a larger page size uses the same value in its
595  * low-order N bits as the encoding for the 2^(12+N) byte page size
596  * (if it exists).
597  */
598 static void init_hpte_page_sizes(void)
599 {
600         long int ap, bp;
601         long int shift, penc;
602 
603         for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
604                 if (!mmu_psize_defs[bp].shift)
605                         continue;       /* not a supported page size */
606                 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
607                         penc = mmu_psize_defs[bp].penc[ap];
608                         if (penc == -1)
609                                 continue;
610                         shift = mmu_psize_defs[ap].shift - LP_SHIFT;
611                         if (shift <= 0)
612                                 continue;       /* should never happen */
613                         /*
614                          * For page sizes less than 1MB, this loop
615                          * replicates the entry for all possible values
616                          * of the rrrr bits.
617                          */
618                         while (penc < (1 << LP_BITS)) {
619                                 hpte_page_sizes[penc] = (ap << 4) | bp;
620                                 penc += 1 << shift;
621                         }
622                 }
623         }
624 }
625 
626 static void __init htab_init_page_sizes(void)
627 {
628         init_hpte_page_sizes();
629 
630         if (!debug_pagealloc_enabled()) {
631                 /*
632                  * Pick a size for the linear mapping. Currently, we only
633                  * support 16M, 1M and 4K which is the default
634                  */
635                 if (mmu_psize_defs[MMU_PAGE_16M].shift)
636                         mmu_linear_psize = MMU_PAGE_16M;
637                 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
638                         mmu_linear_psize = MMU_PAGE_1M;
639         }
640 
641 #ifdef CONFIG_PPC_64K_PAGES
642         /*
643          * Pick a size for the ordinary pages. Default is 4K, we support
644          * 64K for user mappings and vmalloc if supported by the processor.
645          * We only use 64k for ioremap if the processor
646          * (and firmware) support cache-inhibited large pages.
647          * If not, we use 4k and set mmu_ci_restrictions so that
648          * hash_page knows to switch processes that use cache-inhibited
649          * mappings to 4k pages.
650          */
651         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
652                 mmu_virtual_psize = MMU_PAGE_64K;
653                 mmu_vmalloc_psize = MMU_PAGE_64K;
654                 if (mmu_linear_psize == MMU_PAGE_4K)
655                         mmu_linear_psize = MMU_PAGE_64K;
656                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
657                         /*
658                          * When running on pSeries using 64k pages for ioremap
659                          * would stop us accessing the HEA ethernet. So if we
660                          * have the chance of ever seeing one, stay at 4k.
661                          */
662                         if (!might_have_hea())
663                                 mmu_io_psize = MMU_PAGE_64K;
664                 } else
665                         mmu_ci_restrictions = 1;
666         }
667 #endif /* CONFIG_PPC_64K_PAGES */
668 
669 #ifdef CONFIG_SPARSEMEM_VMEMMAP
670         /* We try to use 16M pages for vmemmap if that is supported
671          * and we have at least 1G of RAM at boot
672          */
673         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
674             memblock_phys_mem_size() >= 0x40000000)
675                 mmu_vmemmap_psize = MMU_PAGE_16M;
676         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
677                 mmu_vmemmap_psize = MMU_PAGE_64K;
678         else
679                 mmu_vmemmap_psize = MMU_PAGE_4K;
680 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
681 
682         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
683                "virtual = %d, io = %d"
684 #ifdef CONFIG_SPARSEMEM_VMEMMAP
685                ", vmemmap = %d"
686 #endif
687                "\n",
688                mmu_psize_defs[mmu_linear_psize].shift,
689                mmu_psize_defs[mmu_virtual_psize].shift,
690                mmu_psize_defs[mmu_io_psize].shift
691 #ifdef CONFIG_SPARSEMEM_VMEMMAP
692                ,mmu_psize_defs[mmu_vmemmap_psize].shift
693 #endif
694                );
695 }
696 
697 static int __init htab_dt_scan_pftsize(unsigned long node,
698                                        const char *uname, int depth,
699                                        void *data)
700 {
701         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
702         const __be32 *prop;
703 
704         /* We are scanning "cpu" nodes only */
705         if (type == NULL || strcmp(type, "cpu") != 0)
706                 return 0;
707 
708         prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
709         if (prop != NULL) {
710                 /* pft_size[0] is the NUMA CEC cookie */
711                 ppc64_pft_size = be32_to_cpu(prop[1]);
712                 return 1;
713         }
714         return 0;
715 }
716 
717 unsigned htab_shift_for_mem_size(unsigned long mem_size)
718 {
719         unsigned memshift = __ilog2(mem_size);
720         unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
721         unsigned pteg_shift;
722 
723         /* round mem_size up to next power of 2 */
724         if ((1UL << memshift) < mem_size)
725                 memshift += 1;
726 
727         /* aim for 2 pages / pteg */
728         pteg_shift = memshift - (pshift + 1);
729 
730         /*
731          * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
732          * size permitted by the architecture.
733          */
734         return max(pteg_shift + 7, 18U);
735 }
736 
737 static unsigned long __init htab_get_table_size(void)
738 {
739         /* If hash size isn't already provided by the platform, we try to
740          * retrieve it from the device-tree. If it's not there neither, we
741          * calculate it now based on the total RAM size
742          */
743         if (ppc64_pft_size == 0)
744                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
745         if (ppc64_pft_size)
746                 return 1UL << ppc64_pft_size;
747 
748         return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
749 }
750 
751 #ifdef CONFIG_MEMORY_HOTPLUG
752 void resize_hpt_for_hotplug(unsigned long new_mem_size)
753 {
754         unsigned target_hpt_shift;
755 
756         if (!mmu_hash_ops.resize_hpt)
757                 return;
758 
759         target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
760 
761         /*
762          * To avoid lots of HPT resizes if memory size is fluctuating
763          * across a boundary, we deliberately have some hysterisis
764          * here: we immediately increase the HPT size if the target
765          * shift exceeds the current shift, but we won't attempt to
766          * reduce unless the target shift is at least 2 below the
767          * current shift
768          */
769         if ((target_hpt_shift > ppc64_pft_size)
770             || (target_hpt_shift < (ppc64_pft_size - 1))) {
771                 int rc;
772 
773                 rc = mmu_hash_ops.resize_hpt(target_hpt_shift);
774                 if (rc)
775                         printk(KERN_WARNING
776                                "Unable to resize hash page table to target order %d: %d\n",
777                                target_hpt_shift, rc);
778         }
779 }
780 
781 int hash__create_section_mapping(unsigned long start, unsigned long end)
782 {
783         int rc = htab_bolt_mapping(start, end, __pa(start),
784                                    pgprot_val(PAGE_KERNEL), mmu_linear_psize,
785                                    mmu_kernel_ssize);
786 
787         if (rc < 0) {
788                 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
789                                               mmu_kernel_ssize);
790                 BUG_ON(rc2 && (rc2 != -ENOENT));
791         }
792         return rc;
793 }
794 
795 int hash__remove_section_mapping(unsigned long start, unsigned long end)
796 {
797         int rc = htab_remove_mapping(start, end, mmu_linear_psize,
798                                      mmu_kernel_ssize);
799         WARN_ON(rc < 0);
800         return rc;
801 }
802 #endif /* CONFIG_MEMORY_HOTPLUG */
803 
804 static void update_hid_for_hash(void)
805 {
806         unsigned long hid0;
807         unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
808 
809         asm volatile("ptesync": : :"memory");
810         /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
811         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
812                      : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
813         asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
814         /*
815          * now switch the HID
816          */
817         hid0  = mfspr(SPRN_HID0);
818         hid0 &= ~HID0_POWER9_RADIX;
819         mtspr(SPRN_HID0, hid0);
820         asm volatile("isync": : :"memory");
821 
822         /* Wait for it to happen */
823         while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
824                 cpu_relax();
825 }
826 
827 static void __init hash_init_partition_table(phys_addr_t hash_table,
828                                              unsigned long htab_size)
829 {
830         mmu_partition_table_init();
831 
832         /*
833          * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
834          * For now, UPRT is 0 and we have no segment table.
835          */
836         htab_size =  __ilog2(htab_size) - 18;
837         mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
838         pr_info("Partition table %p\n", partition_tb);
839         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
840                 update_hid_for_hash();
841 }
842 
843 static void __init htab_initialize(void)
844 {
845         unsigned long table;
846         unsigned long pteg_count;
847         unsigned long prot;
848         unsigned long base = 0, size = 0;
849         struct memblock_region *reg;
850 
851         DBG(" -> htab_initialize()\n");
852 
853         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
854                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
855                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
856                 printk(KERN_INFO "Using 1TB segments\n");
857         }
858 
859         /*
860          * Calculate the required size of the htab.  We want the number of
861          * PTEGs to equal one half the number of real pages.
862          */ 
863         htab_size_bytes = htab_get_table_size();
864         pteg_count = htab_size_bytes >> 7;
865 
866         htab_hash_mask = pteg_count - 1;
867 
868         if (firmware_has_feature(FW_FEATURE_LPAR) ||
869             firmware_has_feature(FW_FEATURE_PS3_LV1)) {
870                 /* Using a hypervisor which owns the htab */
871                 htab_address = NULL;
872                 _SDR1 = 0; 
873 #ifdef CONFIG_FA_DUMP
874                 /*
875                  * If firmware assisted dump is active firmware preserves
876                  * the contents of htab along with entire partition memory.
877                  * Clear the htab if firmware assisted dump is active so
878                  * that we dont end up using old mappings.
879                  */
880                 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
881                         mmu_hash_ops.hpte_clear_all();
882 #endif
883         } else {
884                 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
885 
886 #ifdef CONFIG_PPC_CELL
887                 /*
888                  * Cell may require the hash table down low when using the
889                  * Axon IOMMU in order to fit the dynamic region over it, see
890                  * comments in cell/iommu.c
891                  */
892                 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
893                         limit = 0x80000000;
894                         pr_info("Hash table forced below 2G for Axon IOMMU\n");
895                 }
896 #endif /* CONFIG_PPC_CELL */
897 
898                 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
899                                             limit);
900 
901                 DBG("Hash table allocated at %lx, size: %lx\n", table,
902                     htab_size_bytes);
903 
904                 htab_address = __va(table);
905 
906                 /* htab absolute addr + encoded htabsize */
907                 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
908 
909                 /* Initialize the HPT with no entries */
910                 memset((void *)table, 0, htab_size_bytes);
911 
912                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
913                         /* Set SDR1 */
914                         mtspr(SPRN_SDR1, _SDR1);
915                 else
916                         hash_init_partition_table(table, htab_size_bytes);
917         }
918 
919         prot = pgprot_val(PAGE_KERNEL);
920 
921 #ifdef CONFIG_DEBUG_PAGEALLOC
922         if (debug_pagealloc_enabled()) {
923                 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
924                 linear_map_hash_slots = __va(memblock_alloc_base(
925                                 linear_map_hash_count, 1, ppc64_rma_size));
926                 memset(linear_map_hash_slots, 0, linear_map_hash_count);
927         }
928 #endif /* CONFIG_DEBUG_PAGEALLOC */
929 
930         /* On U3 based machines, we need to reserve the DART area and
931          * _NOT_ map it to avoid cache paradoxes as it's remapped non
932          * cacheable later on
933          */
934 
935         /* create bolted the linear mapping in the hash table */
936         for_each_memblock(memory, reg) {
937                 base = (unsigned long)__va(reg->base);
938                 size = reg->size;
939 
940                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
941                     base, size, prot);
942 
943                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
944                                 prot, mmu_linear_psize, mmu_kernel_ssize));
945         }
946         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
947 
948         /*
949          * If we have a memory_limit and we've allocated TCEs then we need to
950          * explicitly map the TCE area at the top of RAM. We also cope with the
951          * case that the TCEs start below memory_limit.
952          * tce_alloc_start/end are 16MB aligned so the mapping should work
953          * for either 4K or 16MB pages.
954          */
955         if (tce_alloc_start) {
956                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
957                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
958 
959                 if (base + size >= tce_alloc_start)
960                         tce_alloc_start = base + size + 1;
961 
962                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
963                                          __pa(tce_alloc_start), prot,
964                                          mmu_linear_psize, mmu_kernel_ssize));
965         }
966 
967 
968         DBG(" <- htab_initialize()\n");
969 }
970 #undef KB
971 #undef MB
972 
973 void __init hash__early_init_devtree(void)
974 {
975         /* Initialize segment sizes */
976         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
977 
978         /* Initialize page sizes */
979         htab_scan_page_sizes();
980 }
981 
982 void __init hash__early_init_mmu(void)
983 {
984         htab_init_page_sizes();
985 
986         /*
987          * initialize page table size
988          */
989         __pte_frag_nr = H_PTE_FRAG_NR;
990         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
991 
992         __pte_index_size = H_PTE_INDEX_SIZE;
993         __pmd_index_size = H_PMD_INDEX_SIZE;
994         __pud_index_size = H_PUD_INDEX_SIZE;
995         __pgd_index_size = H_PGD_INDEX_SIZE;
996         __pmd_cache_index = H_PMD_CACHE_INDEX;
997         __pte_table_size = H_PTE_TABLE_SIZE;
998         __pmd_table_size = H_PMD_TABLE_SIZE;
999         __pud_table_size = H_PUD_TABLE_SIZE;
1000         __pgd_table_size = H_PGD_TABLE_SIZE;
1001         /*
1002          * 4k use hugepd format, so for hash set then to
1003          * zero
1004          */
1005         __pmd_val_bits = 0;
1006         __pud_val_bits = 0;
1007         __pgd_val_bits = 0;
1008 
1009         __kernel_virt_start = H_KERN_VIRT_START;
1010         __kernel_virt_size = H_KERN_VIRT_SIZE;
1011         __vmalloc_start = H_VMALLOC_START;
1012         __vmalloc_end = H_VMALLOC_END;
1013         vmemmap = (struct page *)H_VMEMMAP_BASE;
1014         ioremap_bot = IOREMAP_BASE;
1015 
1016 #ifdef CONFIG_PCI
1017         pci_io_base = ISA_IO_BASE;
1018 #endif
1019 
1020         /* Select appropriate backend */
1021         if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1022                 ps3_early_mm_init();
1023         else if (firmware_has_feature(FW_FEATURE_LPAR))
1024                 hpte_init_pseries();
1025         else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1026                 hpte_init_native();
1027 
1028         if (!mmu_hash_ops.hpte_insert)
1029                 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1030 
1031         /* Initialize the MMU Hash table and create the linear mapping
1032          * of memory. Has to be done before SLB initialization as this is
1033          * currently where the page size encoding is obtained.
1034          */
1035         htab_initialize();
1036 
1037         pr_info("Initializing hash mmu with SLB\n");
1038         /* Initialize SLB management */
1039         slb_initialize();
1040 }
1041 
1042 #ifdef CONFIG_SMP
1043 void hash__early_init_mmu_secondary(void)
1044 {
1045         /* Initialize hash table for that CPU */
1046         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1047 
1048                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
1049                         update_hid_for_hash();
1050 
1051                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1052                         mtspr(SPRN_SDR1, _SDR1);
1053                 else
1054                         mtspr(SPRN_PTCR,
1055                               __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1056         }
1057         /* Initialize SLB */
1058         slb_initialize();
1059 }
1060 #endif /* CONFIG_SMP */
1061 
1062 /*
1063  * Called by asm hashtable.S for doing lazy icache flush
1064  */
1065 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1066 {
1067         struct page *page;
1068 
1069         if (!pfn_valid(pte_pfn(pte)))
1070                 return pp;
1071 
1072         page = pte_page(pte);
1073 
1074         /* page is dirty */
1075         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1076                 if (trap == 0x400) {
1077                         flush_dcache_icache_page(page);
1078                         set_bit(PG_arch_1, &page->flags);
1079                 } else
1080                         pp |= HPTE_R_N;
1081         }
1082         return pp;
1083 }
1084 
1085 #ifdef CONFIG_PPC_MM_SLICES
1086 static unsigned int get_paca_psize(unsigned long addr)
1087 {
1088         u64 lpsizes;
1089         unsigned char *hpsizes;
1090         unsigned long index, mask_index;
1091 
1092         if (addr < SLICE_LOW_TOP) {
1093                 lpsizes = get_paca()->mm_ctx_low_slices_psize;
1094                 index = GET_LOW_SLICE_INDEX(addr);
1095                 return (lpsizes >> (index * 4)) & 0xF;
1096         }
1097         hpsizes = get_paca()->mm_ctx_high_slices_psize;
1098         index = GET_HIGH_SLICE_INDEX(addr);
1099         mask_index = index & 0x1;
1100         return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1101 }
1102 
1103 #else
1104 unsigned int get_paca_psize(unsigned long addr)
1105 {
1106         return get_paca()->mm_ctx_user_psize;
1107 }
1108 #endif
1109 
1110 /*
1111  * Demote a segment to using 4k pages.
1112  * For now this makes the whole process use 4k pages.
1113  */
1114 #ifdef CONFIG_PPC_64K_PAGES
1115 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1116 {
1117         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1118                 return;
1119         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1120         copro_flush_all_slbs(mm);
1121         if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1122 
1123                 copy_mm_to_paca(&mm->context);
1124                 slb_flush_and_rebolt();
1125         }
1126 }
1127 #endif /* CONFIG_PPC_64K_PAGES */
1128 
1129 #ifdef CONFIG_PPC_SUBPAGE_PROT
1130 /*
1131  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1132  * Userspace sets the subpage permissions using the subpage_prot system call.
1133  *
1134  * Result is 0: full permissions, _PAGE_RW: read-only,
1135  * _PAGE_RWX: no access.
1136  */
1137 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1138 {
1139         struct subpage_prot_table *spt = &mm->context.spt;
1140         u32 spp = 0;
1141         u32 **sbpm, *sbpp;
1142 
1143         if (ea >= spt->maxaddr)
1144                 return 0;
1145         if (ea < 0x100000000UL) {
1146                 /* addresses below 4GB use spt->low_prot */
1147                 sbpm = spt->low_prot;
1148         } else {
1149                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1150                 if (!sbpm)
1151                         return 0;
1152         }
1153         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1154         if (!sbpp)
1155                 return 0;
1156         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1157 
1158         /* extract 2-bit bitfield for this 4k subpage */
1159         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1160 
1161         /*
1162          * 0 -> full premission
1163          * 1 -> Read only
1164          * 2 -> no access.
1165          * We return the flag that need to be cleared.
1166          */
1167         spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1168         return spp;
1169 }
1170 
1171 #else /* CONFIG_PPC_SUBPAGE_PROT */
1172 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1173 {
1174         return 0;
1175 }
1176 #endif
1177 
1178 void hash_failure_debug(unsigned long ea, unsigned long access,
1179                         unsigned long vsid, unsigned long trap,
1180                         int ssize, int psize, int lpsize, unsigned long pte)
1181 {
1182         if (!printk_ratelimit())
1183                 return;
1184         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1185                 ea, access, current->comm);
1186         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1187                 trap, vsid, ssize, psize, lpsize, pte);
1188 }
1189 
1190 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1191                              int psize, bool user_region)
1192 {
1193         if (user_region) {
1194                 if (psize != get_paca_psize(ea)) {
1195                         copy_mm_to_paca(&mm->context);
1196                         slb_flush_and_rebolt();
1197                 }
1198         } else if (get_paca()->vmalloc_sllp !=
1199                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1200                 get_paca()->vmalloc_sllp =
1201                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1202                 slb_vmalloc_update();
1203         }
1204 }
1205 
1206 /* Result code is:
1207  *  0 - handled
1208  *  1 - normal page fault
1209  * -1 - critical hash insertion error
1210  * -2 - access not permitted by subpage protection mechanism
1211  */
1212 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1213                  unsigned long access, unsigned long trap,
1214                  unsigned long flags)
1215 {
1216         bool is_thp;
1217         enum ctx_state prev_state = exception_enter();
1218         pgd_t *pgdir;
1219         unsigned long vsid;
1220         pte_t *ptep;
1221         unsigned hugeshift;
1222         const struct cpumask *tmp;
1223         int rc, user_region = 0;
1224         int psize, ssize;
1225 
1226         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1227                 ea, access, trap);
1228         trace_hash_fault(ea, access, trap);
1229 
1230         /* Get region & vsid */
1231         switch (REGION_ID(ea)) {
1232         case USER_REGION_ID:
1233                 user_region = 1;
1234                 if (! mm) {
1235                         DBG_LOW(" user region with no mm !\n");
1236                         rc = 1;
1237                         goto bail;
1238                 }
1239                 psize = get_slice_psize(mm, ea);
1240                 ssize = user_segment_size(ea);
1241                 vsid = get_vsid(mm->context.id, ea, ssize);
1242                 break;
1243         case VMALLOC_REGION_ID:
1244                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1245                 if (ea < VMALLOC_END)
1246                         psize = mmu_vmalloc_psize;
1247                 else
1248                         psize = mmu_io_psize;
1249                 ssize = mmu_kernel_ssize;
1250                 break;
1251         default:
1252                 /* Not a valid range
1253                  * Send the problem up to do_page_fault 
1254                  */
1255                 rc = 1;
1256                 goto bail;
1257         }
1258         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1259 
1260         /* Bad address. */
1261         if (!vsid) {
1262                 DBG_LOW("Bad address!\n");
1263                 rc = 1;
1264                 goto bail;
1265         }
1266         /* Get pgdir */
1267         pgdir = mm->pgd;
1268         if (pgdir == NULL) {
1269                 rc = 1;
1270                 goto bail;
1271         }
1272 
1273         /* Check CPU locality */
1274         tmp = cpumask_of(smp_processor_id());
1275         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1276                 flags |= HPTE_LOCAL_UPDATE;
1277 
1278 #ifndef CONFIG_PPC_64K_PAGES
1279         /* If we use 4K pages and our psize is not 4K, then we might
1280          * be hitting a special driver mapping, and need to align the
1281          * address before we fetch the PTE.
1282          *
1283          * It could also be a hugepage mapping, in which case this is
1284          * not necessary, but it's not harmful, either.
1285          */
1286         if (psize != MMU_PAGE_4K)
1287                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1288 #endif /* CONFIG_PPC_64K_PAGES */
1289 
1290         /* Get PTE and page size from page tables */
1291         ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1292         if (ptep == NULL || !pte_present(*ptep)) {
1293                 DBG_LOW(" no PTE !\n");
1294                 rc = 1;
1295                 goto bail;
1296         }
1297 
1298         /* Add _PAGE_PRESENT to the required access perm */
1299         access |= _PAGE_PRESENT;
1300 
1301         /* Pre-check access permissions (will be re-checked atomically
1302          * in __hash_page_XX but this pre-check is a fast path
1303          */
1304         if (!check_pte_access(access, pte_val(*ptep))) {
1305                 DBG_LOW(" no access !\n");
1306                 rc = 1;
1307                 goto bail;
1308         }
1309 
1310         if (hugeshift) {
1311                 if (is_thp)
1312                         rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1313                                              trap, flags, ssize, psize);
1314 #ifdef CONFIG_HUGETLB_PAGE
1315                 else
1316                         rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1317                                               flags, ssize, hugeshift, psize);
1318 #else
1319                 else {
1320                         /*
1321                          * if we have hugeshift, and is not transhuge with
1322                          * hugetlb disabled, something is really wrong.
1323                          */
1324                         rc = 1;
1325                         WARN_ON(1);
1326                 }
1327 #endif
1328                 if (current->mm == mm)
1329                         check_paca_psize(ea, mm, psize, user_region);
1330 
1331                 goto bail;
1332         }
1333 
1334 #ifndef CONFIG_PPC_64K_PAGES
1335         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1336 #else
1337         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1338                 pte_val(*(ptep + PTRS_PER_PTE)));
1339 #endif
1340         /* Do actual hashing */
1341 #ifdef CONFIG_PPC_64K_PAGES
1342         /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1343         if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1344                 demote_segment_4k(mm, ea);
1345                 psize = MMU_PAGE_4K;
1346         }
1347 
1348         /* If this PTE is non-cacheable and we have restrictions on
1349          * using non cacheable large pages, then we switch to 4k
1350          */
1351         if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1352                 if (user_region) {
1353                         demote_segment_4k(mm, ea);
1354                         psize = MMU_PAGE_4K;
1355                 } else if (ea < VMALLOC_END) {
1356                         /*
1357                          * some driver did a non-cacheable mapping
1358                          * in vmalloc space, so switch vmalloc
1359                          * to 4k pages
1360                          */
1361                         printk(KERN_ALERT "Reducing vmalloc segment "
1362                                "to 4kB pages because of "
1363                                "non-cacheable mapping\n");
1364                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1365                         copro_flush_all_slbs(mm);
1366                 }
1367         }
1368 
1369 #endif /* CONFIG_PPC_64K_PAGES */
1370 
1371         if (current->mm == mm)
1372                 check_paca_psize(ea, mm, psize, user_region);
1373 
1374 #ifdef CONFIG_PPC_64K_PAGES
1375         if (psize == MMU_PAGE_64K)
1376                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1377                                      flags, ssize);
1378         else
1379 #endif /* CONFIG_PPC_64K_PAGES */
1380         {
1381                 int spp = subpage_protection(mm, ea);
1382                 if (access & spp)
1383                         rc = -2;
1384                 else
1385                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1386                                             flags, ssize, spp);
1387         }
1388 
1389         /* Dump some info in case of hash insertion failure, they should
1390          * never happen so it is really useful to know if/when they do
1391          */
1392         if (rc == -1)
1393                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1394                                    psize, pte_val(*ptep));
1395 #ifndef CONFIG_PPC_64K_PAGES
1396         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1397 #else
1398         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1399                 pte_val(*(ptep + PTRS_PER_PTE)));
1400 #endif
1401         DBG_LOW(" -> rc=%d\n", rc);
1402 
1403 bail:
1404         exception_exit(prev_state);
1405         return rc;
1406 }
1407 EXPORT_SYMBOL_GPL(hash_page_mm);
1408 
1409 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1410               unsigned long dsisr)
1411 {
1412         unsigned long flags = 0;
1413         struct mm_struct *mm = current->mm;
1414 
1415         if (REGION_ID(ea) == VMALLOC_REGION_ID)
1416                 mm = &init_mm;
1417 
1418         if (dsisr & DSISR_NOHPTE)
1419                 flags |= HPTE_NOHPTE_UPDATE;
1420 
1421         return hash_page_mm(mm, ea, access, trap, flags);
1422 }
1423 EXPORT_SYMBOL_GPL(hash_page);
1424 
1425 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1426                 unsigned long dsisr)
1427 {
1428         unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1429         unsigned long flags = 0;
1430         struct mm_struct *mm = current->mm;
1431 
1432         if (REGION_ID(ea) == VMALLOC_REGION_ID)
1433                 mm = &init_mm;
1434 
1435         if (dsisr & DSISR_NOHPTE)
1436                 flags |= HPTE_NOHPTE_UPDATE;
1437 
1438         if (dsisr & DSISR_ISSTORE)
1439                 access |= _PAGE_WRITE;
1440         /*
1441          * We set _PAGE_PRIVILEGED only when
1442          * kernel mode access kernel space.
1443          *
1444          * _PAGE_PRIVILEGED is NOT set
1445          * 1) when kernel mode access user space
1446          * 2) user space access kernel space.
1447          */
1448         access |= _PAGE_PRIVILEGED;
1449         if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1450                 access &= ~_PAGE_PRIVILEGED;
1451 
1452         if (trap == 0x400)
1453                 access |= _PAGE_EXEC;
1454 
1455         return hash_page_mm(mm, ea, access, trap, flags);
1456 }
1457 
1458 #ifdef CONFIG_PPC_MM_SLICES
1459 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1460 {
1461         int psize = get_slice_psize(mm, ea);
1462 
1463         /* We only prefault standard pages for now */
1464         if (unlikely(psize != mm->context.user_psize))
1465                 return false;
1466 
1467         /*
1468          * Don't prefault if subpage protection is enabled for the EA.
1469          */
1470         if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1471                 return false;
1472 
1473         return true;
1474 }
1475 #else
1476 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1477 {
1478         return true;
1479 }
1480 #endif
1481 
1482 void hash_preload(struct mm_struct *mm, unsigned long ea,
1483                   unsigned long access, unsigned long trap)
1484 {
1485         int hugepage_shift;
1486         unsigned long vsid;
1487         pgd_t *pgdir;
1488         pte_t *ptep;
1489         unsigned long flags;
1490         int rc, ssize, update_flags = 0;
1491 
1492         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1493 
1494         if (!should_hash_preload(mm, ea))
1495                 return;
1496 
1497         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1498                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1499 
1500         /* Get Linux PTE if available */
1501         pgdir = mm->pgd;
1502         if (pgdir == NULL)
1503                 return;
1504 
1505         /* Get VSID */
1506         ssize = user_segment_size(ea);
1507         vsid = get_vsid(mm->context.id, ea, ssize);
1508         if (!vsid)
1509                 return;
1510         /*
1511          * Hash doesn't like irqs. Walking linux page table with irq disabled
1512          * saves us from holding multiple locks.
1513          */
1514         local_irq_save(flags);
1515 
1516         /*
1517          * THP pages use update_mmu_cache_pmd. We don't do
1518          * hash preload there. Hence can ignore THP here
1519          */
1520         ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1521         if (!ptep)
1522                 goto out_exit;
1523 
1524         WARN_ON(hugepage_shift);
1525 #ifdef CONFIG_PPC_64K_PAGES
1526         /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1527          * a 64K kernel), then we don't preload, hash_page() will take
1528          * care of it once we actually try to access the page.
1529          * That way we don't have to duplicate all of the logic for segment
1530          * page size demotion here
1531          */
1532         if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1533                 goto out_exit;
1534 #endif /* CONFIG_PPC_64K_PAGES */
1535 
1536         /* Is that local to this CPU ? */
1537         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1538                 update_flags |= HPTE_LOCAL_UPDATE;
1539 
1540         /* Hash it in */
1541 #ifdef CONFIG_PPC_64K_PAGES
1542         if (mm->context.user_psize == MMU_PAGE_64K)
1543                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1544                                      update_flags, ssize);
1545         else
1546 #endif /* CONFIG_PPC_64K_PAGES */
1547                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1548                                     ssize, subpage_protection(mm, ea));
1549 
1550         /* Dump some info in case of hash insertion failure, they should
1551          * never happen so it is really useful to know if/when they do
1552          */
1553         if (rc == -1)
1554                 hash_failure_debug(ea, access, vsid, trap, ssize,
1555                                    mm->context.user_psize,
1556                                    mm->context.user_psize,
1557                                    pte_val(*ptep));
1558 out_exit:
1559         local_irq_restore(flags);
1560 }
1561 
1562 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1563 static inline void tm_flush_hash_page(int local)
1564 {
1565         /*
1566          * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1567          * page back to a block device w/PIO could pick up transactional data
1568          * (bad!) so we force an abort here. Before the sync the page will be
1569          * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1570          * kernel uses a page from userspace without unmapping it first, it may
1571          * see the speculated version.
1572          */
1573         if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1574             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1575                 tm_enable();
1576                 tm_abort(TM_CAUSE_TLBI);
1577         }
1578 }
1579 #else
1580 static inline void tm_flush_hash_page(int local)
1581 {
1582 }
1583 #endif
1584 
1585 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1586  *          do not forget to update the assembly call site !
1587  */
1588 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1589                      unsigned long flags)
1590 {
1591         unsigned long hash, index, shift, hidx, slot;
1592         int local = flags & HPTE_LOCAL_UPDATE;
1593 
1594         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1595         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1596                 hash = hpt_hash(vpn, shift, ssize);
1597                 hidx = __rpte_to_hidx(pte, index);
1598                 if (hidx & _PTEIDX_SECONDARY)
1599                         hash = ~hash;
1600                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1601                 slot += hidx & _PTEIDX_GROUP_IX;
1602                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1603                 /*
1604                  * We use same base page size and actual psize, because we don't
1605                  * use these functions for hugepage
1606                  */
1607                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1608                                              ssize, local);
1609         } pte_iterate_hashed_end();
1610 
1611         tm_flush_hash_page(local);
1612 }
1613 
1614 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1615 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1616                          pmd_t *pmdp, unsigned int psize, int ssize,
1617                          unsigned long flags)
1618 {
1619         int i, max_hpte_count, valid;
1620         unsigned long s_addr;
1621         unsigned char *hpte_slot_array;
1622         unsigned long hidx, shift, vpn, hash, slot;
1623         int local = flags & HPTE_LOCAL_UPDATE;
1624 
1625         s_addr = addr & HPAGE_PMD_MASK;
1626         hpte_slot_array = get_hpte_slot_array(pmdp);
1627         /*
1628          * IF we try to do a HUGE PTE update after a withdraw is done.
1629          * we will find the below NULL. This happens when we do
1630          * split_huge_page_pmd
1631          */
1632         if (!hpte_slot_array)
1633                 return;
1634 
1635         if (mmu_hash_ops.hugepage_invalidate) {
1636                 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1637                                                  psize, ssize, local);
1638                 goto tm_abort;
1639         }
1640         /*
1641          * No bluk hpte removal support, invalidate each entry
1642          */
1643         shift = mmu_psize_defs[psize].shift;
1644         max_hpte_count = HPAGE_PMD_SIZE >> shift;
1645         for (i = 0; i < max_hpte_count; i++) {
1646                 /*
1647                  * 8 bits per each hpte entries
1648                  * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1649                  */
1650                 valid = hpte_valid(hpte_slot_array, i);
1651                 if (!valid)
1652                         continue;
1653                 hidx =  hpte_hash_index(hpte_slot_array, i);
1654 
1655                 /* get the vpn */
1656                 addr = s_addr + (i * (1ul << shift));
1657                 vpn = hpt_vpn(addr, vsid, ssize);
1658                 hash = hpt_hash(vpn, shift, ssize);
1659                 if (hidx & _PTEIDX_SECONDARY)
1660                         hash = ~hash;
1661 
1662                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1663                 slot += hidx & _PTEIDX_GROUP_IX;
1664                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1665                                              MMU_PAGE_16M, ssize, local);
1666         }
1667 tm_abort:
1668         tm_flush_hash_page(local);
1669 }
1670 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1671 
1672 void flush_hash_range(unsigned long number, int local)
1673 {
1674         if (mmu_hash_ops.flush_hash_range)
1675                 mmu_hash_ops.flush_hash_range(number, local);
1676         else {
1677                 int i;
1678                 struct ppc64_tlb_batch *batch =
1679                         this_cpu_ptr(&ppc64_tlb_batch);
1680 
1681                 for (i = 0; i < number; i++)
1682                         flush_hash_page(batch->vpn[i], batch->pte[i],
1683                                         batch->psize, batch->ssize, local);
1684         }
1685 }
1686 
1687 /*
1688  * low_hash_fault is called when we the low level hash code failed
1689  * to instert a PTE due to an hypervisor error
1690  */
1691 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1692 {
1693         enum ctx_state prev_state = exception_enter();
1694 
1695         if (user_mode(regs)) {
1696 #ifdef CONFIG_PPC_SUBPAGE_PROT
1697                 if (rc == -2)
1698                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1699                 else
1700 #endif
1701                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1702         } else
1703                 bad_page_fault(regs, address, SIGBUS);
1704 
1705         exception_exit(prev_state);
1706 }
1707 
1708 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1709                            unsigned long pa, unsigned long rflags,
1710                            unsigned long vflags, int psize, int ssize)
1711 {
1712         unsigned long hpte_group;
1713         long slot;
1714 
1715 repeat:
1716         hpte_group = ((hash & htab_hash_mask) *
1717                        HPTES_PER_GROUP) & ~0x7UL;
1718 
1719         /* Insert into the hash table, primary slot */
1720         slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1721                                         psize, psize, ssize);
1722 
1723         /* Primary is full, try the secondary */
1724         if (unlikely(slot == -1)) {
1725                 hpte_group = ((~hash & htab_hash_mask) *
1726                               HPTES_PER_GROUP) & ~0x7UL;
1727                 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1728                                                 vflags | HPTE_V_SECONDARY,
1729                                                 psize, psize, ssize);
1730                 if (slot == -1) {
1731                         if (mftb() & 0x1)
1732                                 hpte_group = ((hash & htab_hash_mask) *
1733                                               HPTES_PER_GROUP)&~0x7UL;
1734 
1735                         mmu_hash_ops.hpte_remove(hpte_group);
1736                         goto repeat;
1737                 }
1738         }
1739 
1740         return slot;
1741 }
1742 
1743 #ifdef CONFIG_DEBUG_PAGEALLOC
1744 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1745 {
1746         unsigned long hash;
1747         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1748         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1749         unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1750         long ret;
1751 
1752         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1753 
1754         /* Don't create HPTE entries for bad address */
1755         if (!vsid)
1756                 return;
1757 
1758         ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1759                                     HPTE_V_BOLTED,
1760                                     mmu_linear_psize, mmu_kernel_ssize);
1761 
1762         BUG_ON (ret < 0);
1763         spin_lock(&linear_map_hash_lock);
1764         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1765         linear_map_hash_slots[lmi] = ret | 0x80;
1766         spin_unlock(&linear_map_hash_lock);
1767 }
1768 
1769 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1770 {
1771         unsigned long hash, hidx, slot;
1772         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1773         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1774 
1775         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1776         spin_lock(&linear_map_hash_lock);
1777         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1778         hidx = linear_map_hash_slots[lmi] & 0x7f;
1779         linear_map_hash_slots[lmi] = 0;
1780         spin_unlock(&linear_map_hash_lock);
1781         if (hidx & _PTEIDX_SECONDARY)
1782                 hash = ~hash;
1783         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1784         slot += hidx & _PTEIDX_GROUP_IX;
1785         mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1786                                      mmu_linear_psize,
1787                                      mmu_kernel_ssize, 0);
1788 }
1789 
1790 void __kernel_map_pages(struct page *page, int numpages, int enable)
1791 {
1792         unsigned long flags, vaddr, lmi;
1793         int i;
1794 
1795         local_irq_save(flags);
1796         for (i = 0; i < numpages; i++, page++) {
1797                 vaddr = (unsigned long)page_address(page);
1798                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1799                 if (lmi >= linear_map_hash_count)
1800                         continue;
1801                 if (enable)
1802                         kernel_map_linear_page(vaddr, lmi);
1803                 else
1804                         kernel_unmap_linear_page(vaddr, lmi);
1805         }
1806         local_irq_restore(flags);
1807 }
1808 #endif /* CONFIG_DEBUG_PAGEALLOC */
1809 
1810 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1811                                 phys_addr_t first_memblock_size)
1812 {
1813         /* We don't currently support the first MEMBLOCK not mapping 0
1814          * physical on those processors
1815          */
1816         BUG_ON(first_memblock_base != 0);
1817 
1818         /* On LPAR systems, the first entry is our RMA region,
1819          * non-LPAR 64-bit hash MMU systems don't have a limitation
1820          * on real mode access, but using the first entry works well
1821          * enough. We also clamp it to 1G to avoid some funky things
1822          * such as RTAS bugs etc...
1823          */
1824         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1825 
1826         /* Finally limit subsequent allocations */
1827         memblock_set_current_limit(ppc64_rma_size);
1828 }
1829 
1830 #ifdef CONFIG_DEBUG_FS
1831 
1832 static int hpt_order_get(void *data, u64 *val)
1833 {
1834         *val = ppc64_pft_size;
1835         return 0;
1836 }
1837 
1838 static int hpt_order_set(void *data, u64 val)
1839 {
1840         if (!mmu_hash_ops.resize_hpt)
1841                 return -ENODEV;
1842 
1843         return mmu_hash_ops.resize_hpt(val);
1844 }
1845 
1846 DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1847 
1848 static int __init hash64_debugfs(void)
1849 {
1850         if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root,
1851                                  NULL, &fops_hpt_order)) {
1852                 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1853         }
1854 
1855         return 0;
1856 }
1857 machine_device_initcall(pseries, hash64_debugfs);
1858 
1859 #endif /* CONFIG_DEBUG_FS */
1860 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp