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TOMOYO Linux Cross Reference
Linux/arch/powerpc/mm/hash_utils_64.c

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  1 /*
  2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
  3  *   {mikejc|engebret}@us.ibm.com
  4  *
  5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
  6  *
  7  * SMP scalability work:
  8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  9  * 
 10  *    Module name: htab.c
 11  *
 12  *    Description:
 13  *      PowerPC Hashed Page Table functions
 14  *
 15  * This program is free software; you can redistribute it and/or
 16  * modify it under the terms of the GNU General Public License
 17  * as published by the Free Software Foundation; either version
 18  * 2 of the License, or (at your option) any later version.
 19  */
 20 
 21 #undef DEBUG
 22 #undef DEBUG_LOW
 23 
 24 #define pr_fmt(fmt) "hash-mmu: " fmt
 25 #include <linux/spinlock.h>
 26 #include <linux/errno.h>
 27 #include <linux/sched/mm.h>
 28 #include <linux/proc_fs.h>
 29 #include <linux/stat.h>
 30 #include <linux/sysctl.h>
 31 #include <linux/export.h>
 32 #include <linux/ctype.h>
 33 #include <linux/cache.h>
 34 #include <linux/init.h>
 35 #include <linux/signal.h>
 36 #include <linux/memblock.h>
 37 #include <linux/context_tracking.h>
 38 #include <linux/libfdt.h>
 39 
 40 #include <asm/debugfs.h>
 41 #include <asm/processor.h>
 42 #include <asm/pgtable.h>
 43 #include <asm/mmu.h>
 44 #include <asm/mmu_context.h>
 45 #include <asm/page.h>
 46 #include <asm/types.h>
 47 #include <linux/uaccess.h>
 48 #include <asm/machdep.h>
 49 #include <asm/prom.h>
 50 #include <asm/tlbflush.h>
 51 #include <asm/io.h>
 52 #include <asm/eeh.h>
 53 #include <asm/tlb.h>
 54 #include <asm/cacheflush.h>
 55 #include <asm/cputable.h>
 56 #include <asm/sections.h>
 57 #include <asm/copro.h>
 58 #include <asm/udbg.h>
 59 #include <asm/code-patching.h>
 60 #include <asm/fadump.h>
 61 #include <asm/firmware.h>
 62 #include <asm/tm.h>
 63 #include <asm/trace.h>
 64 #include <asm/ps3.h>
 65 #include <asm/pte-walk.h>
 66 
 67 #ifdef DEBUG
 68 #define DBG(fmt...) udbg_printf(fmt)
 69 #else
 70 #define DBG(fmt...)
 71 #endif
 72 
 73 #ifdef DEBUG_LOW
 74 #define DBG_LOW(fmt...) udbg_printf(fmt)
 75 #else
 76 #define DBG_LOW(fmt...)
 77 #endif
 78 
 79 #define KB (1024)
 80 #define MB (1024*KB)
 81 #define GB (1024L*MB)
 82 
 83 /*
 84  * Note:  pte   --> Linux PTE
 85  *        HPTE  --> PowerPC Hashed Page Table Entry
 86  *
 87  * Execution context:
 88  *   htab_initialize is called with the MMU off (of course), but
 89  *   the kernel has been copied down to zero so it can directly
 90  *   reference global data.  At this point it is very difficult
 91  *   to print debug info.
 92  *
 93  */
 94 
 95 static unsigned long _SDR1;
 96 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 97 EXPORT_SYMBOL_GPL(mmu_psize_defs);
 98 
 99 u8 hpte_page_sizes[1 << LP_BITS];
100 EXPORT_SYMBOL_GPL(hpte_page_sizes);
101 
102 struct hash_pte *htab_address;
103 unsigned long htab_size_bytes;
104 unsigned long htab_hash_mask;
105 EXPORT_SYMBOL_GPL(htab_hash_mask);
106 int mmu_linear_psize = MMU_PAGE_4K;
107 EXPORT_SYMBOL_GPL(mmu_linear_psize);
108 int mmu_virtual_psize = MMU_PAGE_4K;
109 int mmu_vmalloc_psize = MMU_PAGE_4K;
110 #ifdef CONFIG_SPARSEMEM_VMEMMAP
111 int mmu_vmemmap_psize = MMU_PAGE_4K;
112 #endif
113 int mmu_io_psize = MMU_PAGE_4K;
114 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
115 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
116 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
117 u16 mmu_slb_size = 64;
118 EXPORT_SYMBOL_GPL(mmu_slb_size);
119 #ifdef CONFIG_PPC_64K_PAGES
120 int mmu_ci_restrictions;
121 #endif
122 #ifdef CONFIG_DEBUG_PAGEALLOC
123 static u8 *linear_map_hash_slots;
124 static unsigned long linear_map_hash_count;
125 static DEFINE_SPINLOCK(linear_map_hash_lock);
126 #endif /* CONFIG_DEBUG_PAGEALLOC */
127 struct mmu_hash_ops mmu_hash_ops;
128 EXPORT_SYMBOL(mmu_hash_ops);
129 
130 /* There are definitions of page sizes arrays to be used when none
131  * is provided by the firmware.
132  */
133 
134 /* Pre-POWER4 CPUs (4k pages only)
135  */
136 static struct mmu_psize_def mmu_psize_defaults_old[] = {
137         [MMU_PAGE_4K] = {
138                 .shift  = 12,
139                 .sllp   = 0,
140                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
141                 .avpnm  = 0,
142                 .tlbiel = 0,
143         },
144 };
145 
146 /* POWER4, GPUL, POWER5
147  *
148  * Support for 16Mb large pages
149  */
150 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
151         [MMU_PAGE_4K] = {
152                 .shift  = 12,
153                 .sllp   = 0,
154                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
155                 .avpnm  = 0,
156                 .tlbiel = 1,
157         },
158         [MMU_PAGE_16M] = {
159                 .shift  = 24,
160                 .sllp   = SLB_VSID_L,
161                 .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
162                             [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
163                 .avpnm  = 0x1UL,
164                 .tlbiel = 0,
165         },
166 };
167 
168 /*
169  * 'R' and 'C' update notes:
170  *  - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
171  *     create writeable HPTEs without C set, because the hcall H_PROTECT
172  *     that we use in that case will not update C
173  *  - The above is however not a problem, because we also don't do that
174  *     fancy "no flush" variant of eviction and we use H_REMOVE which will
175  *     do the right thing and thus we don't have the race I described earlier
176  *
177  *    - Under bare metal,  we do have the race, so we need R and C set
178  *    - We make sure R is always set and never lost
179  *    - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
180  */
181 unsigned long htab_convert_pte_flags(unsigned long pteflags)
182 {
183         unsigned long rflags = 0;
184 
185         /* _PAGE_EXEC -> NOEXEC */
186         if ((pteflags & _PAGE_EXEC) == 0)
187                 rflags |= HPTE_R_N;
188         /*
189          * PPP bits:
190          * Linux uses slb key 0 for kernel and 1 for user.
191          * kernel RW areas are mapped with PPP=0b000
192          * User area is mapped with PPP=0b010 for read/write
193          * or PPP=0b011 for read-only (including writeable but clean pages).
194          */
195         if (pteflags & _PAGE_PRIVILEGED) {
196                 /*
197                  * Kernel read only mapped with ppp bits 0b110
198                  */
199                 if (!(pteflags & _PAGE_WRITE)) {
200                         if (mmu_has_feature(MMU_FTR_KERNEL_RO))
201                                 rflags |= (HPTE_R_PP0 | 0x2);
202                         else
203                                 rflags |= 0x3;
204                 }
205         } else {
206                 if (pteflags & _PAGE_RWX)
207                         rflags |= 0x2;
208                 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
209                         rflags |= 0x1;
210         }
211         /*
212          * We can't allow hardware to update hpte bits. Hence always
213          * set 'R' bit and set 'C' if it is a write fault
214          */
215         rflags |=  HPTE_R_R;
216 
217         if (pteflags & _PAGE_DIRTY)
218                 rflags |= HPTE_R_C;
219         /*
220          * Add in WIG bits
221          */
222 
223         if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
224                 rflags |= HPTE_R_I;
225         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
226                 rflags |= (HPTE_R_I | HPTE_R_G);
227         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
228                 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
229         else
230                 /*
231                  * Add memory coherence if cache inhibited is not set
232                  */
233                 rflags |= HPTE_R_M;
234 
235         return rflags;
236 }
237 
238 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
239                       unsigned long pstart, unsigned long prot,
240                       int psize, int ssize)
241 {
242         unsigned long vaddr, paddr;
243         unsigned int step, shift;
244         int ret = 0;
245 
246         shift = mmu_psize_defs[psize].shift;
247         step = 1 << shift;
248 
249         prot = htab_convert_pte_flags(prot);
250 
251         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
252             vstart, vend, pstart, prot, psize, ssize);
253 
254         for (vaddr = vstart, paddr = pstart; vaddr < vend;
255              vaddr += step, paddr += step) {
256                 unsigned long hash, hpteg;
257                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
258                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
259                 unsigned long tprot = prot;
260 
261                 /*
262                  * If we hit a bad address return error.
263                  */
264                 if (!vsid)
265                         return -1;
266                 /* Make kernel text executable */
267                 if (overlaps_kernel_text(vaddr, vaddr + step))
268                         tprot &= ~HPTE_R_N;
269 
270                 /* Make kvm guest trampolines executable */
271                 if (overlaps_kvm_tmp(vaddr, vaddr + step))
272                         tprot &= ~HPTE_R_N;
273 
274                 /*
275                  * If relocatable, check if it overlaps interrupt vectors that
276                  * are copied down to real 0. For relocatable kernel
277                  * (e.g. kdump case) we copy interrupt vectors down to real
278                  * address 0. Mark that region as executable. This is
279                  * because on p8 system with relocation on exception feature
280                  * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
281                  * in order to execute the interrupt handlers in virtual
282                  * mode the vector region need to be marked as executable.
283                  */
284                 if ((PHYSICAL_START > MEMORY_START) &&
285                         overlaps_interrupt_vector_text(vaddr, vaddr + step))
286                                 tprot &= ~HPTE_R_N;
287 
288                 hash = hpt_hash(vpn, shift, ssize);
289                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
290 
291                 BUG_ON(!mmu_hash_ops.hpte_insert);
292                 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
293                                                HPTE_V_BOLTED, psize, psize,
294                                                ssize);
295 
296                 if (ret < 0)
297                         break;
298 
299 #ifdef CONFIG_DEBUG_PAGEALLOC
300                 if (debug_pagealloc_enabled() &&
301                         (paddr >> PAGE_SHIFT) < linear_map_hash_count)
302                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
303 #endif /* CONFIG_DEBUG_PAGEALLOC */
304         }
305         return ret < 0 ? ret : 0;
306 }
307 
308 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
309                       int psize, int ssize)
310 {
311         unsigned long vaddr;
312         unsigned int step, shift;
313         int rc;
314         int ret = 0;
315 
316         shift = mmu_psize_defs[psize].shift;
317         step = 1 << shift;
318 
319         if (!mmu_hash_ops.hpte_removebolted)
320                 return -ENODEV;
321 
322         for (vaddr = vstart; vaddr < vend; vaddr += step) {
323                 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
324                 if (rc == -ENOENT) {
325                         ret = -ENOENT;
326                         continue;
327                 }
328                 if (rc < 0)
329                         return rc;
330         }
331 
332         return ret;
333 }
334 
335 static bool disable_1tb_segments = false;
336 
337 static int __init parse_disable_1tb_segments(char *p)
338 {
339         disable_1tb_segments = true;
340         return 0;
341 }
342 early_param("disable_1tb_segments", parse_disable_1tb_segments);
343 
344 static int __init htab_dt_scan_seg_sizes(unsigned long node,
345                                          const char *uname, int depth,
346                                          void *data)
347 {
348         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
349         const __be32 *prop;
350         int size = 0;
351 
352         /* We are scanning "cpu" nodes only */
353         if (type == NULL || strcmp(type, "cpu") != 0)
354                 return 0;
355 
356         prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
357         if (prop == NULL)
358                 return 0;
359         for (; size >= 4; size -= 4, ++prop) {
360                 if (be32_to_cpu(prop[0]) == 40) {
361                         DBG("1T segment support detected\n");
362 
363                         if (disable_1tb_segments) {
364                                 DBG("1T segments disabled by command line\n");
365                                 break;
366                         }
367 
368                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
369                         return 1;
370                 }
371         }
372         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
373         return 0;
374 }
375 
376 static int __init get_idx_from_shift(unsigned int shift)
377 {
378         int idx = -1;
379 
380         switch (shift) {
381         case 0xc:
382                 idx = MMU_PAGE_4K;
383                 break;
384         case 0x10:
385                 idx = MMU_PAGE_64K;
386                 break;
387         case 0x14:
388                 idx = MMU_PAGE_1M;
389                 break;
390         case 0x18:
391                 idx = MMU_PAGE_16M;
392                 break;
393         case 0x22:
394                 idx = MMU_PAGE_16G;
395                 break;
396         }
397         return idx;
398 }
399 
400 static int __init htab_dt_scan_page_sizes(unsigned long node,
401                                           const char *uname, int depth,
402                                           void *data)
403 {
404         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
405         const __be32 *prop;
406         int size = 0;
407 
408         /* We are scanning "cpu" nodes only */
409         if (type == NULL || strcmp(type, "cpu") != 0)
410                 return 0;
411 
412         prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
413         if (!prop)
414                 return 0;
415 
416         pr_info("Page sizes from device-tree:\n");
417         size /= 4;
418         cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
419         while(size > 0) {
420                 unsigned int base_shift = be32_to_cpu(prop[0]);
421                 unsigned int slbenc = be32_to_cpu(prop[1]);
422                 unsigned int lpnum = be32_to_cpu(prop[2]);
423                 struct mmu_psize_def *def;
424                 int idx, base_idx;
425 
426                 size -= 3; prop += 3;
427                 base_idx = get_idx_from_shift(base_shift);
428                 if (base_idx < 0) {
429                         /* skip the pte encoding also */
430                         prop += lpnum * 2; size -= lpnum * 2;
431                         continue;
432                 }
433                 def = &mmu_psize_defs[base_idx];
434                 if (base_idx == MMU_PAGE_16M)
435                         cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
436 
437                 def->shift = base_shift;
438                 if (base_shift <= 23)
439                         def->avpnm = 0;
440                 else
441                         def->avpnm = (1 << (base_shift - 23)) - 1;
442                 def->sllp = slbenc;
443                 /*
444                  * We don't know for sure what's up with tlbiel, so
445                  * for now we only set it for 4K and 64K pages
446                  */
447                 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
448                         def->tlbiel = 1;
449                 else
450                         def->tlbiel = 0;
451 
452                 while (size > 0 && lpnum) {
453                         unsigned int shift = be32_to_cpu(prop[0]);
454                         int penc  = be32_to_cpu(prop[1]);
455 
456                         prop += 2; size -= 2;
457                         lpnum--;
458 
459                         idx = get_idx_from_shift(shift);
460                         if (idx < 0)
461                                 continue;
462 
463                         if (penc == -1)
464                                 pr_err("Invalid penc for base_shift=%d "
465                                        "shift=%d\n", base_shift, shift);
466 
467                         def->penc[idx] = penc;
468                         pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
469                                 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
470                                 base_shift, shift, def->sllp,
471                                 def->avpnm, def->tlbiel, def->penc[idx]);
472                 }
473         }
474 
475         return 1;
476 }
477 
478 #ifdef CONFIG_HUGETLB_PAGE
479 /* Scan for 16G memory blocks that have been set aside for huge pages
480  * and reserve those blocks for 16G huge pages.
481  */
482 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
483                                         const char *uname, int depth,
484                                         void *data) {
485         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
486         const __be64 *addr_prop;
487         const __be32 *page_count_prop;
488         unsigned int expected_pages;
489         long unsigned int phys_addr;
490         long unsigned int block_size;
491 
492         /* We are scanning "memory" nodes only */
493         if (type == NULL || strcmp(type, "memory") != 0)
494                 return 0;
495 
496         /* This property is the log base 2 of the number of virtual pages that
497          * will represent this memory block. */
498         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
499         if (page_count_prop == NULL)
500                 return 0;
501         expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
502         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
503         if (addr_prop == NULL)
504                 return 0;
505         phys_addr = be64_to_cpu(addr_prop[0]);
506         block_size = be64_to_cpu(addr_prop[1]);
507         if (block_size != (16 * GB))
508                 return 0;
509         printk(KERN_INFO "Huge page(16GB) memory: "
510                         "addr = 0x%lX size = 0x%lX pages = %d\n",
511                         phys_addr, block_size, expected_pages);
512         if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
513                 memblock_reserve(phys_addr, block_size * expected_pages);
514                 pseries_add_gpage(phys_addr, block_size, expected_pages);
515         }
516         return 0;
517 }
518 #endif /* CONFIG_HUGETLB_PAGE */
519 
520 static void mmu_psize_set_default_penc(void)
521 {
522         int bpsize, apsize;
523         for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
524                 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
525                         mmu_psize_defs[bpsize].penc[apsize] = -1;
526 }
527 
528 #ifdef CONFIG_PPC_64K_PAGES
529 
530 static bool might_have_hea(void)
531 {
532         /*
533          * The HEA ethernet adapter requires awareness of the
534          * GX bus. Without that awareness we can easily assume
535          * we will never see an HEA ethernet device.
536          */
537 #ifdef CONFIG_IBMEBUS
538         return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
539                 firmware_has_feature(FW_FEATURE_SPLPAR);
540 #else
541         return false;
542 #endif
543 }
544 
545 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
546 
547 static void __init htab_scan_page_sizes(void)
548 {
549         int rc;
550 
551         /* se the invalid penc to -1 */
552         mmu_psize_set_default_penc();
553 
554         /* Default to 4K pages only */
555         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
556                sizeof(mmu_psize_defaults_old));
557 
558         /*
559          * Try to find the available page sizes in the device-tree
560          */
561         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
562         if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
563                 /*
564                  * Nothing in the device-tree, but the CPU supports 16M pages,
565                  * so let's fallback on a known size list for 16M capable CPUs.
566                  */
567                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
568                        sizeof(mmu_psize_defaults_gp));
569         }
570 
571 #ifdef CONFIG_HUGETLB_PAGE
572         /* Reserve 16G huge page memory sections for huge pages */
573         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
574 #endif /* CONFIG_HUGETLB_PAGE */
575 }
576 
577 /*
578  * Fill in the hpte_page_sizes[] array.
579  * We go through the mmu_psize_defs[] array looking for all the
580  * supported base/actual page size combinations.  Each combination
581  * has a unique pagesize encoding (penc) value in the low bits of
582  * the LP field of the HPTE.  For actual page sizes less than 1MB,
583  * some of the upper LP bits are used for RPN bits, meaning that
584  * we need to fill in several entries in hpte_page_sizes[].
585  *
586  * In diagrammatic form, with r = RPN bits and z = page size bits:
587  *        PTE LP     actual page size
588  *    rrrr rrrz         >=8KB
589  *    rrrr rrzz         >=16KB
590  *    rrrr rzzz         >=32KB
591  *    rrrr zzzz         >=64KB
592  *    ...
593  *
594  * The zzzz bits are implementation-specific but are chosen so that
595  * no encoding for a larger page size uses the same value in its
596  * low-order N bits as the encoding for the 2^(12+N) byte page size
597  * (if it exists).
598  */
599 static void init_hpte_page_sizes(void)
600 {
601         long int ap, bp;
602         long int shift, penc;
603 
604         for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
605                 if (!mmu_psize_defs[bp].shift)
606                         continue;       /* not a supported page size */
607                 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
608                         penc = mmu_psize_defs[bp].penc[ap];
609                         if (penc == -1)
610                                 continue;
611                         shift = mmu_psize_defs[ap].shift - LP_SHIFT;
612                         if (shift <= 0)
613                                 continue;       /* should never happen */
614                         /*
615                          * For page sizes less than 1MB, this loop
616                          * replicates the entry for all possible values
617                          * of the rrrr bits.
618                          */
619                         while (penc < (1 << LP_BITS)) {
620                                 hpte_page_sizes[penc] = (ap << 4) | bp;
621                                 penc += 1 << shift;
622                         }
623                 }
624         }
625 }
626 
627 static void __init htab_init_page_sizes(void)
628 {
629         init_hpte_page_sizes();
630 
631         if (!debug_pagealloc_enabled()) {
632                 /*
633                  * Pick a size for the linear mapping. Currently, we only
634                  * support 16M, 1M and 4K which is the default
635                  */
636                 if (mmu_psize_defs[MMU_PAGE_16M].shift)
637                         mmu_linear_psize = MMU_PAGE_16M;
638                 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
639                         mmu_linear_psize = MMU_PAGE_1M;
640         }
641 
642 #ifdef CONFIG_PPC_64K_PAGES
643         /*
644          * Pick a size for the ordinary pages. Default is 4K, we support
645          * 64K for user mappings and vmalloc if supported by the processor.
646          * We only use 64k for ioremap if the processor
647          * (and firmware) support cache-inhibited large pages.
648          * If not, we use 4k and set mmu_ci_restrictions so that
649          * hash_page knows to switch processes that use cache-inhibited
650          * mappings to 4k pages.
651          */
652         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
653                 mmu_virtual_psize = MMU_PAGE_64K;
654                 mmu_vmalloc_psize = MMU_PAGE_64K;
655                 if (mmu_linear_psize == MMU_PAGE_4K)
656                         mmu_linear_psize = MMU_PAGE_64K;
657                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
658                         /*
659                          * When running on pSeries using 64k pages for ioremap
660                          * would stop us accessing the HEA ethernet. So if we
661                          * have the chance of ever seeing one, stay at 4k.
662                          */
663                         if (!might_have_hea())
664                                 mmu_io_psize = MMU_PAGE_64K;
665                 } else
666                         mmu_ci_restrictions = 1;
667         }
668 #endif /* CONFIG_PPC_64K_PAGES */
669 
670 #ifdef CONFIG_SPARSEMEM_VMEMMAP
671         /* We try to use 16M pages for vmemmap if that is supported
672          * and we have at least 1G of RAM at boot
673          */
674         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
675             memblock_phys_mem_size() >= 0x40000000)
676                 mmu_vmemmap_psize = MMU_PAGE_16M;
677         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
678                 mmu_vmemmap_psize = MMU_PAGE_64K;
679         else
680                 mmu_vmemmap_psize = MMU_PAGE_4K;
681 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
682 
683         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
684                "virtual = %d, io = %d"
685 #ifdef CONFIG_SPARSEMEM_VMEMMAP
686                ", vmemmap = %d"
687 #endif
688                "\n",
689                mmu_psize_defs[mmu_linear_psize].shift,
690                mmu_psize_defs[mmu_virtual_psize].shift,
691                mmu_psize_defs[mmu_io_psize].shift
692 #ifdef CONFIG_SPARSEMEM_VMEMMAP
693                ,mmu_psize_defs[mmu_vmemmap_psize].shift
694 #endif
695                );
696 }
697 
698 static int __init htab_dt_scan_pftsize(unsigned long node,
699                                        const char *uname, int depth,
700                                        void *data)
701 {
702         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
703         const __be32 *prop;
704 
705         /* We are scanning "cpu" nodes only */
706         if (type == NULL || strcmp(type, "cpu") != 0)
707                 return 0;
708 
709         prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
710         if (prop != NULL) {
711                 /* pft_size[0] is the NUMA CEC cookie */
712                 ppc64_pft_size = be32_to_cpu(prop[1]);
713                 return 1;
714         }
715         return 0;
716 }
717 
718 unsigned htab_shift_for_mem_size(unsigned long mem_size)
719 {
720         unsigned memshift = __ilog2(mem_size);
721         unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
722         unsigned pteg_shift;
723 
724         /* round mem_size up to next power of 2 */
725         if ((1UL << memshift) < mem_size)
726                 memshift += 1;
727 
728         /* aim for 2 pages / pteg */
729         pteg_shift = memshift - (pshift + 1);
730 
731         /*
732          * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
733          * size permitted by the architecture.
734          */
735         return max(pteg_shift + 7, 18U);
736 }
737 
738 static unsigned long __init htab_get_table_size(void)
739 {
740         /* If hash size isn't already provided by the platform, we try to
741          * retrieve it from the device-tree. If it's not there neither, we
742          * calculate it now based on the total RAM size
743          */
744         if (ppc64_pft_size == 0)
745                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
746         if (ppc64_pft_size)
747                 return 1UL << ppc64_pft_size;
748 
749         return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
750 }
751 
752 #ifdef CONFIG_MEMORY_HOTPLUG
753 void resize_hpt_for_hotplug(unsigned long new_mem_size)
754 {
755         unsigned target_hpt_shift;
756 
757         if (!mmu_hash_ops.resize_hpt)
758                 return;
759 
760         target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
761 
762         /*
763          * To avoid lots of HPT resizes if memory size is fluctuating
764          * across a boundary, we deliberately have some hysterisis
765          * here: we immediately increase the HPT size if the target
766          * shift exceeds the current shift, but we won't attempt to
767          * reduce unless the target shift is at least 2 below the
768          * current shift
769          */
770         if ((target_hpt_shift > ppc64_pft_size)
771             || (target_hpt_shift < (ppc64_pft_size - 1))) {
772                 int rc;
773 
774                 rc = mmu_hash_ops.resize_hpt(target_hpt_shift);
775                 if (rc)
776                         printk(KERN_WARNING
777                                "Unable to resize hash page table to target order %d: %d\n",
778                                target_hpt_shift, rc);
779         }
780 }
781 
782 int hash__create_section_mapping(unsigned long start, unsigned long end)
783 {
784         int rc = htab_bolt_mapping(start, end, __pa(start),
785                                    pgprot_val(PAGE_KERNEL), mmu_linear_psize,
786                                    mmu_kernel_ssize);
787 
788         if (rc < 0) {
789                 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
790                                               mmu_kernel_ssize);
791                 BUG_ON(rc2 && (rc2 != -ENOENT));
792         }
793         return rc;
794 }
795 
796 int hash__remove_section_mapping(unsigned long start, unsigned long end)
797 {
798         int rc = htab_remove_mapping(start, end, mmu_linear_psize,
799                                      mmu_kernel_ssize);
800         WARN_ON(rc < 0);
801         return rc;
802 }
803 #endif /* CONFIG_MEMORY_HOTPLUG */
804 
805 static void update_hid_for_hash(void)
806 {
807         unsigned long hid0;
808         unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
809 
810         asm volatile("ptesync": : :"memory");
811         /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
812         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
813                      : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
814         asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
815         trace_tlbie(0, 0, rb, 0, 2, 0, 0);
816 
817         /*
818          * now switch the HID
819          */
820         hid0  = mfspr(SPRN_HID0);
821         hid0 &= ~HID0_POWER9_RADIX;
822         mtspr(SPRN_HID0, hid0);
823         asm volatile("isync": : :"memory");
824 
825         /* Wait for it to happen */
826         while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
827                 cpu_relax();
828 }
829 
830 static void __init hash_init_partition_table(phys_addr_t hash_table,
831                                              unsigned long htab_size)
832 {
833         mmu_partition_table_init();
834 
835         /*
836          * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
837          * For now, UPRT is 0 and we have no segment table.
838          */
839         htab_size =  __ilog2(htab_size) - 18;
840         mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
841         pr_info("Partition table %p\n", partition_tb);
842         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
843                 update_hid_for_hash();
844 }
845 
846 static void __init htab_initialize(void)
847 {
848         unsigned long table;
849         unsigned long pteg_count;
850         unsigned long prot;
851         unsigned long base = 0, size = 0;
852         struct memblock_region *reg;
853 
854         DBG(" -> htab_initialize()\n");
855 
856         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
857                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
858                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
859                 printk(KERN_INFO "Using 1TB segments\n");
860         }
861 
862         /*
863          * Calculate the required size of the htab.  We want the number of
864          * PTEGs to equal one half the number of real pages.
865          */ 
866         htab_size_bytes = htab_get_table_size();
867         pteg_count = htab_size_bytes >> 7;
868 
869         htab_hash_mask = pteg_count - 1;
870 
871         if (firmware_has_feature(FW_FEATURE_LPAR) ||
872             firmware_has_feature(FW_FEATURE_PS3_LV1)) {
873                 /* Using a hypervisor which owns the htab */
874                 htab_address = NULL;
875                 _SDR1 = 0; 
876 #ifdef CONFIG_FA_DUMP
877                 /*
878                  * If firmware assisted dump is active firmware preserves
879                  * the contents of htab along with entire partition memory.
880                  * Clear the htab if firmware assisted dump is active so
881                  * that we dont end up using old mappings.
882                  */
883                 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
884                         mmu_hash_ops.hpte_clear_all();
885 #endif
886         } else {
887                 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
888 
889 #ifdef CONFIG_PPC_CELL
890                 /*
891                  * Cell may require the hash table down low when using the
892                  * Axon IOMMU in order to fit the dynamic region over it, see
893                  * comments in cell/iommu.c
894                  */
895                 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
896                         limit = 0x80000000;
897                         pr_info("Hash table forced below 2G for Axon IOMMU\n");
898                 }
899 #endif /* CONFIG_PPC_CELL */
900 
901                 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
902                                             limit);
903 
904                 DBG("Hash table allocated at %lx, size: %lx\n", table,
905                     htab_size_bytes);
906 
907                 htab_address = __va(table);
908 
909                 /* htab absolute addr + encoded htabsize */
910                 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
911 
912                 /* Initialize the HPT with no entries */
913                 memset((void *)table, 0, htab_size_bytes);
914 
915                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
916                         /* Set SDR1 */
917                         mtspr(SPRN_SDR1, _SDR1);
918                 else
919                         hash_init_partition_table(table, htab_size_bytes);
920         }
921 
922         prot = pgprot_val(PAGE_KERNEL);
923 
924 #ifdef CONFIG_DEBUG_PAGEALLOC
925         if (debug_pagealloc_enabled()) {
926                 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
927                 linear_map_hash_slots = __va(memblock_alloc_base(
928                                 linear_map_hash_count, 1, ppc64_rma_size));
929                 memset(linear_map_hash_slots, 0, linear_map_hash_count);
930         }
931 #endif /* CONFIG_DEBUG_PAGEALLOC */
932 
933         /* create bolted the linear mapping in the hash table */
934         for_each_memblock(memory, reg) {
935                 base = (unsigned long)__va(reg->base);
936                 size = reg->size;
937 
938                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
939                     base, size, prot);
940 
941                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
942                                 prot, mmu_linear_psize, mmu_kernel_ssize));
943         }
944         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
945 
946         /*
947          * If we have a memory_limit and we've allocated TCEs then we need to
948          * explicitly map the TCE area at the top of RAM. We also cope with the
949          * case that the TCEs start below memory_limit.
950          * tce_alloc_start/end are 16MB aligned so the mapping should work
951          * for either 4K or 16MB pages.
952          */
953         if (tce_alloc_start) {
954                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
955                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
956 
957                 if (base + size >= tce_alloc_start)
958                         tce_alloc_start = base + size + 1;
959 
960                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
961                                          __pa(tce_alloc_start), prot,
962                                          mmu_linear_psize, mmu_kernel_ssize));
963         }
964 
965 
966         DBG(" <- htab_initialize()\n");
967 }
968 #undef KB
969 #undef MB
970 
971 void __init hash__early_init_devtree(void)
972 {
973         /* Initialize segment sizes */
974         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
975 
976         /* Initialize page sizes */
977         htab_scan_page_sizes();
978 }
979 
980 void __init hash__early_init_mmu(void)
981 {
982         /*
983          * We have code in __hash_page_64K() and elsewhere, which assumes it can
984          * do the following:
985          *   new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
986          *
987          * Where the slot number is between 0-15, and values of 8-15 indicate
988          * the secondary bucket. For that code to work H_PAGE_F_SECOND and
989          * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
990          * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
991          * with a BUILD_BUG_ON().
992          */
993         BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul  << (H_PAGE_F_GIX_SHIFT + 3)));
994 
995         htab_init_page_sizes();
996 
997         /*
998          * initialize page table size
999          */
1000         __pte_frag_nr = H_PTE_FRAG_NR;
1001         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1002 
1003         __pte_index_size = H_PTE_INDEX_SIZE;
1004         __pmd_index_size = H_PMD_INDEX_SIZE;
1005         __pud_index_size = H_PUD_INDEX_SIZE;
1006         __pgd_index_size = H_PGD_INDEX_SIZE;
1007         __pmd_cache_index = H_PMD_CACHE_INDEX;
1008         __pte_table_size = H_PTE_TABLE_SIZE;
1009         __pmd_table_size = H_PMD_TABLE_SIZE;
1010         __pud_table_size = H_PUD_TABLE_SIZE;
1011         __pgd_table_size = H_PGD_TABLE_SIZE;
1012         /*
1013          * 4k use hugepd format, so for hash set then to
1014          * zero
1015          */
1016         __pmd_val_bits = 0;
1017         __pud_val_bits = 0;
1018         __pgd_val_bits = 0;
1019 
1020         __kernel_virt_start = H_KERN_VIRT_START;
1021         __kernel_virt_size = H_KERN_VIRT_SIZE;
1022         __vmalloc_start = H_VMALLOC_START;
1023         __vmalloc_end = H_VMALLOC_END;
1024         __kernel_io_start = H_KERN_IO_START;
1025         vmemmap = (struct page *)H_VMEMMAP_BASE;
1026         ioremap_bot = IOREMAP_BASE;
1027 
1028 #ifdef CONFIG_PCI
1029         pci_io_base = ISA_IO_BASE;
1030 #endif
1031 
1032         /* Select appropriate backend */
1033         if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1034                 ps3_early_mm_init();
1035         else if (firmware_has_feature(FW_FEATURE_LPAR))
1036                 hpte_init_pseries();
1037         else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1038                 hpte_init_native();
1039 
1040         if (!mmu_hash_ops.hpte_insert)
1041                 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1042 
1043         /* Initialize the MMU Hash table and create the linear mapping
1044          * of memory. Has to be done before SLB initialization as this is
1045          * currently where the page size encoding is obtained.
1046          */
1047         htab_initialize();
1048 
1049         pr_info("Initializing hash mmu with SLB\n");
1050         /* Initialize SLB management */
1051         slb_initialize();
1052 }
1053 
1054 #ifdef CONFIG_SMP
1055 void hash__early_init_mmu_secondary(void)
1056 {
1057         /* Initialize hash table for that CPU */
1058         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1059 
1060                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
1061                         update_hid_for_hash();
1062 
1063                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1064                         mtspr(SPRN_SDR1, _SDR1);
1065                 else
1066                         mtspr(SPRN_PTCR,
1067                               __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1068         }
1069         /* Initialize SLB */
1070         slb_initialize();
1071 }
1072 #endif /* CONFIG_SMP */
1073 
1074 /*
1075  * Called by asm hashtable.S for doing lazy icache flush
1076  */
1077 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1078 {
1079         struct page *page;
1080 
1081         if (!pfn_valid(pte_pfn(pte)))
1082                 return pp;
1083 
1084         page = pte_page(pte);
1085 
1086         /* page is dirty */
1087         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1088                 if (trap == 0x400) {
1089                         flush_dcache_icache_page(page);
1090                         set_bit(PG_arch_1, &page->flags);
1091                 } else
1092                         pp |= HPTE_R_N;
1093         }
1094         return pp;
1095 }
1096 
1097 #ifdef CONFIG_PPC_MM_SLICES
1098 static unsigned int get_paca_psize(unsigned long addr)
1099 {
1100         u64 lpsizes;
1101         unsigned char *hpsizes;
1102         unsigned long index, mask_index;
1103 
1104         if (addr < SLICE_LOW_TOP) {
1105                 lpsizes = get_paca()->mm_ctx_low_slices_psize;
1106                 index = GET_LOW_SLICE_INDEX(addr);
1107                 return (lpsizes >> (index * 4)) & 0xF;
1108         }
1109         hpsizes = get_paca()->mm_ctx_high_slices_psize;
1110         index = GET_HIGH_SLICE_INDEX(addr);
1111         mask_index = index & 0x1;
1112         return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1113 }
1114 
1115 #else
1116 unsigned int get_paca_psize(unsigned long addr)
1117 {
1118         return get_paca()->mm_ctx_user_psize;
1119 }
1120 #endif
1121 
1122 /*
1123  * Demote a segment to using 4k pages.
1124  * For now this makes the whole process use 4k pages.
1125  */
1126 #ifdef CONFIG_PPC_64K_PAGES
1127 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1128 {
1129         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1130                 return;
1131         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1132         copro_flush_all_slbs(mm);
1133         if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1134 
1135                 copy_mm_to_paca(mm);
1136                 slb_flush_and_rebolt();
1137         }
1138 }
1139 #endif /* CONFIG_PPC_64K_PAGES */
1140 
1141 #ifdef CONFIG_PPC_SUBPAGE_PROT
1142 /*
1143  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1144  * Userspace sets the subpage permissions using the subpage_prot system call.
1145  *
1146  * Result is 0: full permissions, _PAGE_RW: read-only,
1147  * _PAGE_RWX: no access.
1148  */
1149 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1150 {
1151         struct subpage_prot_table *spt = &mm->context.spt;
1152         u32 spp = 0;
1153         u32 **sbpm, *sbpp;
1154 
1155         if (ea >= spt->maxaddr)
1156                 return 0;
1157         if (ea < 0x100000000UL) {
1158                 /* addresses below 4GB use spt->low_prot */
1159                 sbpm = spt->low_prot;
1160         } else {
1161                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1162                 if (!sbpm)
1163                         return 0;
1164         }
1165         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1166         if (!sbpp)
1167                 return 0;
1168         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1169 
1170         /* extract 2-bit bitfield for this 4k subpage */
1171         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1172 
1173         /*
1174          * 0 -> full premission
1175          * 1 -> Read only
1176          * 2 -> no access.
1177          * We return the flag that need to be cleared.
1178          */
1179         spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1180         return spp;
1181 }
1182 
1183 #else /* CONFIG_PPC_SUBPAGE_PROT */
1184 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1185 {
1186         return 0;
1187 }
1188 #endif
1189 
1190 void hash_failure_debug(unsigned long ea, unsigned long access,
1191                         unsigned long vsid, unsigned long trap,
1192                         int ssize, int psize, int lpsize, unsigned long pte)
1193 {
1194         if (!printk_ratelimit())
1195                 return;
1196         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1197                 ea, access, current->comm);
1198         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1199                 trap, vsid, ssize, psize, lpsize, pte);
1200 }
1201 
1202 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1203                              int psize, bool user_region)
1204 {
1205         if (user_region) {
1206                 if (psize != get_paca_psize(ea)) {
1207                         copy_mm_to_paca(mm);
1208                         slb_flush_and_rebolt();
1209                 }
1210         } else if (get_paca()->vmalloc_sllp !=
1211                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1212                 get_paca()->vmalloc_sllp =
1213                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1214                 slb_vmalloc_update();
1215         }
1216 }
1217 
1218 /* Result code is:
1219  *  0 - handled
1220  *  1 - normal page fault
1221  * -1 - critical hash insertion error
1222  * -2 - access not permitted by subpage protection mechanism
1223  */
1224 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1225                  unsigned long access, unsigned long trap,
1226                  unsigned long flags)
1227 {
1228         bool is_thp;
1229         enum ctx_state prev_state = exception_enter();
1230         pgd_t *pgdir;
1231         unsigned long vsid;
1232         pte_t *ptep;
1233         unsigned hugeshift;
1234         int rc, user_region = 0;
1235         int psize, ssize;
1236 
1237         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1238                 ea, access, trap);
1239         trace_hash_fault(ea, access, trap);
1240 
1241         /* Get region & vsid */
1242         switch (REGION_ID(ea)) {
1243         case USER_REGION_ID:
1244                 user_region = 1;
1245                 if (! mm) {
1246                         DBG_LOW(" user region with no mm !\n");
1247                         rc = 1;
1248                         goto bail;
1249                 }
1250                 psize = get_slice_psize(mm, ea);
1251                 ssize = user_segment_size(ea);
1252                 vsid = get_vsid(mm->context.id, ea, ssize);
1253                 break;
1254         case VMALLOC_REGION_ID:
1255                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1256                 if (ea < VMALLOC_END)
1257                         psize = mmu_vmalloc_psize;
1258                 else
1259                         psize = mmu_io_psize;
1260                 ssize = mmu_kernel_ssize;
1261                 break;
1262         default:
1263                 /* Not a valid range
1264                  * Send the problem up to do_page_fault 
1265                  */
1266                 rc = 1;
1267                 goto bail;
1268         }
1269         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1270 
1271         /* Bad address. */
1272         if (!vsid) {
1273                 DBG_LOW("Bad address!\n");
1274                 rc = 1;
1275                 goto bail;
1276         }
1277         /* Get pgdir */
1278         pgdir = mm->pgd;
1279         if (pgdir == NULL) {
1280                 rc = 1;
1281                 goto bail;
1282         }
1283 
1284         /* Check CPU locality */
1285         if (user_region && mm_is_thread_local(mm))
1286                 flags |= HPTE_LOCAL_UPDATE;
1287 
1288 #ifndef CONFIG_PPC_64K_PAGES
1289         /* If we use 4K pages and our psize is not 4K, then we might
1290          * be hitting a special driver mapping, and need to align the
1291          * address before we fetch the PTE.
1292          *
1293          * It could also be a hugepage mapping, in which case this is
1294          * not necessary, but it's not harmful, either.
1295          */
1296         if (psize != MMU_PAGE_4K)
1297                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1298 #endif /* CONFIG_PPC_64K_PAGES */
1299 
1300         /* Get PTE and page size from page tables */
1301         ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1302         if (ptep == NULL || !pte_present(*ptep)) {
1303                 DBG_LOW(" no PTE !\n");
1304                 rc = 1;
1305                 goto bail;
1306         }
1307 
1308         /* Add _PAGE_PRESENT to the required access perm */
1309         access |= _PAGE_PRESENT;
1310 
1311         /* Pre-check access permissions (will be re-checked atomically
1312          * in __hash_page_XX but this pre-check is a fast path
1313          */
1314         if (!check_pte_access(access, pte_val(*ptep))) {
1315                 DBG_LOW(" no access !\n");
1316                 rc = 1;
1317                 goto bail;
1318         }
1319 
1320         if (hugeshift) {
1321                 if (is_thp)
1322                         rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1323                                              trap, flags, ssize, psize);
1324 #ifdef CONFIG_HUGETLB_PAGE
1325                 else
1326                         rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1327                                               flags, ssize, hugeshift, psize);
1328 #else
1329                 else {
1330                         /*
1331                          * if we have hugeshift, and is not transhuge with
1332                          * hugetlb disabled, something is really wrong.
1333                          */
1334                         rc = 1;
1335                         WARN_ON(1);
1336                 }
1337 #endif
1338                 if (current->mm == mm)
1339                         check_paca_psize(ea, mm, psize, user_region);
1340 
1341                 goto bail;
1342         }
1343 
1344 #ifndef CONFIG_PPC_64K_PAGES
1345         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1346 #else
1347         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1348                 pte_val(*(ptep + PTRS_PER_PTE)));
1349 #endif
1350         /* Do actual hashing */
1351 #ifdef CONFIG_PPC_64K_PAGES
1352         /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1353         if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1354                 demote_segment_4k(mm, ea);
1355                 psize = MMU_PAGE_4K;
1356         }
1357 
1358         /* If this PTE is non-cacheable and we have restrictions on
1359          * using non cacheable large pages, then we switch to 4k
1360          */
1361         if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1362                 if (user_region) {
1363                         demote_segment_4k(mm, ea);
1364                         psize = MMU_PAGE_4K;
1365                 } else if (ea < VMALLOC_END) {
1366                         /*
1367                          * some driver did a non-cacheable mapping
1368                          * in vmalloc space, so switch vmalloc
1369                          * to 4k pages
1370                          */
1371                         printk(KERN_ALERT "Reducing vmalloc segment "
1372                                "to 4kB pages because of "
1373                                "non-cacheable mapping\n");
1374                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1375                         copro_flush_all_slbs(mm);
1376                 }
1377         }
1378 
1379 #endif /* CONFIG_PPC_64K_PAGES */
1380 
1381         if (current->mm == mm)
1382                 check_paca_psize(ea, mm, psize, user_region);
1383 
1384 #ifdef CONFIG_PPC_64K_PAGES
1385         if (psize == MMU_PAGE_64K)
1386                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1387                                      flags, ssize);
1388         else
1389 #endif /* CONFIG_PPC_64K_PAGES */
1390         {
1391                 int spp = subpage_protection(mm, ea);
1392                 if (access & spp)
1393                         rc = -2;
1394                 else
1395                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1396                                             flags, ssize, spp);
1397         }
1398 
1399         /* Dump some info in case of hash insertion failure, they should
1400          * never happen so it is really useful to know if/when they do
1401          */
1402         if (rc == -1)
1403                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1404                                    psize, pte_val(*ptep));
1405 #ifndef CONFIG_PPC_64K_PAGES
1406         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1407 #else
1408         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1409                 pte_val(*(ptep + PTRS_PER_PTE)));
1410 #endif
1411         DBG_LOW(" -> rc=%d\n", rc);
1412 
1413 bail:
1414         exception_exit(prev_state);
1415         return rc;
1416 }
1417 EXPORT_SYMBOL_GPL(hash_page_mm);
1418 
1419 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1420               unsigned long dsisr)
1421 {
1422         unsigned long flags = 0;
1423         struct mm_struct *mm = current->mm;
1424 
1425         if (REGION_ID(ea) == VMALLOC_REGION_ID)
1426                 mm = &init_mm;
1427 
1428         if (dsisr & DSISR_NOHPTE)
1429                 flags |= HPTE_NOHPTE_UPDATE;
1430 
1431         return hash_page_mm(mm, ea, access, trap, flags);
1432 }
1433 EXPORT_SYMBOL_GPL(hash_page);
1434 
1435 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1436                 unsigned long dsisr)
1437 {
1438         unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1439         unsigned long flags = 0;
1440         struct mm_struct *mm = current->mm;
1441 
1442         if (REGION_ID(ea) == VMALLOC_REGION_ID)
1443                 mm = &init_mm;
1444 
1445         if (dsisr & DSISR_NOHPTE)
1446                 flags |= HPTE_NOHPTE_UPDATE;
1447 
1448         if (dsisr & DSISR_ISSTORE)
1449                 access |= _PAGE_WRITE;
1450         /*
1451          * We set _PAGE_PRIVILEGED only when
1452          * kernel mode access kernel space.
1453          *
1454          * _PAGE_PRIVILEGED is NOT set
1455          * 1) when kernel mode access user space
1456          * 2) user space access kernel space.
1457          */
1458         access |= _PAGE_PRIVILEGED;
1459         if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1460                 access &= ~_PAGE_PRIVILEGED;
1461 
1462         if (trap == 0x400)
1463                 access |= _PAGE_EXEC;
1464 
1465         return hash_page_mm(mm, ea, access, trap, flags);
1466 }
1467 
1468 #ifdef CONFIG_PPC_MM_SLICES
1469 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1470 {
1471         int psize = get_slice_psize(mm, ea);
1472 
1473         /* We only prefault standard pages for now */
1474         if (unlikely(psize != mm->context.user_psize))
1475                 return false;
1476 
1477         /*
1478          * Don't prefault if subpage protection is enabled for the EA.
1479          */
1480         if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1481                 return false;
1482 
1483         return true;
1484 }
1485 #else
1486 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1487 {
1488         return true;
1489 }
1490 #endif
1491 
1492 void hash_preload(struct mm_struct *mm, unsigned long ea,
1493                   unsigned long access, unsigned long trap)
1494 {
1495         int hugepage_shift;
1496         unsigned long vsid;
1497         pgd_t *pgdir;
1498         pte_t *ptep;
1499         unsigned long flags;
1500         int rc, ssize, update_flags = 0;
1501 
1502         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1503 
1504         if (!should_hash_preload(mm, ea))
1505                 return;
1506 
1507         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1508                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1509 
1510         /* Get Linux PTE if available */
1511         pgdir = mm->pgd;
1512         if (pgdir == NULL)
1513                 return;
1514 
1515         /* Get VSID */
1516         ssize = user_segment_size(ea);
1517         vsid = get_vsid(mm->context.id, ea, ssize);
1518         if (!vsid)
1519                 return;
1520         /*
1521          * Hash doesn't like irqs. Walking linux page table with irq disabled
1522          * saves us from holding multiple locks.
1523          */
1524         local_irq_save(flags);
1525 
1526         /*
1527          * THP pages use update_mmu_cache_pmd. We don't do
1528          * hash preload there. Hence can ignore THP here
1529          */
1530         ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1531         if (!ptep)
1532                 goto out_exit;
1533 
1534         WARN_ON(hugepage_shift);
1535 #ifdef CONFIG_PPC_64K_PAGES
1536         /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1537          * a 64K kernel), then we don't preload, hash_page() will take
1538          * care of it once we actually try to access the page.
1539          * That way we don't have to duplicate all of the logic for segment
1540          * page size demotion here
1541          */
1542         if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1543                 goto out_exit;
1544 #endif /* CONFIG_PPC_64K_PAGES */
1545 
1546         /* Is that local to this CPU ? */
1547         if (mm_is_thread_local(mm))
1548                 update_flags |= HPTE_LOCAL_UPDATE;
1549 
1550         /* Hash it in */
1551 #ifdef CONFIG_PPC_64K_PAGES
1552         if (mm->context.user_psize == MMU_PAGE_64K)
1553                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1554                                      update_flags, ssize);
1555         else
1556 #endif /* CONFIG_PPC_64K_PAGES */
1557                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1558                                     ssize, subpage_protection(mm, ea));
1559 
1560         /* Dump some info in case of hash insertion failure, they should
1561          * never happen so it is really useful to know if/when they do
1562          */
1563         if (rc == -1)
1564                 hash_failure_debug(ea, access, vsid, trap, ssize,
1565                                    mm->context.user_psize,
1566                                    mm->context.user_psize,
1567                                    pte_val(*ptep));
1568 out_exit:
1569         local_irq_restore(flags);
1570 }
1571 
1572 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1573 static inline void tm_flush_hash_page(int local)
1574 {
1575         /*
1576          * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1577          * page back to a block device w/PIO could pick up transactional data
1578          * (bad!) so we force an abort here. Before the sync the page will be
1579          * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1580          * kernel uses a page from userspace without unmapping it first, it may
1581          * see the speculated version.
1582          */
1583         if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1584             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1585                 tm_enable();
1586                 tm_abort(TM_CAUSE_TLBI);
1587         }
1588 }
1589 #else
1590 static inline void tm_flush_hash_page(int local)
1591 {
1592 }
1593 #endif
1594 
1595 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1596  *          do not forget to update the assembly call site !
1597  */
1598 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1599                      unsigned long flags)
1600 {
1601         unsigned long hash, index, shift, hidx, slot;
1602         int local = flags & HPTE_LOCAL_UPDATE;
1603 
1604         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1605         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1606                 hash = hpt_hash(vpn, shift, ssize);
1607                 hidx = __rpte_to_hidx(pte, index);
1608                 if (hidx & _PTEIDX_SECONDARY)
1609                         hash = ~hash;
1610                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1611                 slot += hidx & _PTEIDX_GROUP_IX;
1612                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1613                 /*
1614                  * We use same base page size and actual psize, because we don't
1615                  * use these functions for hugepage
1616                  */
1617                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1618                                              ssize, local);
1619         } pte_iterate_hashed_end();
1620 
1621         tm_flush_hash_page(local);
1622 }
1623 
1624 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1625 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1626                          pmd_t *pmdp, unsigned int psize, int ssize,
1627                          unsigned long flags)
1628 {
1629         int i, max_hpte_count, valid;
1630         unsigned long s_addr;
1631         unsigned char *hpte_slot_array;
1632         unsigned long hidx, shift, vpn, hash, slot;
1633         int local = flags & HPTE_LOCAL_UPDATE;
1634 
1635         s_addr = addr & HPAGE_PMD_MASK;
1636         hpte_slot_array = get_hpte_slot_array(pmdp);
1637         /*
1638          * IF we try to do a HUGE PTE update after a withdraw is done.
1639          * we will find the below NULL. This happens when we do
1640          * split_huge_page_pmd
1641          */
1642         if (!hpte_slot_array)
1643                 return;
1644 
1645         if (mmu_hash_ops.hugepage_invalidate) {
1646                 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1647                                                  psize, ssize, local);
1648                 goto tm_abort;
1649         }
1650         /*
1651          * No bluk hpte removal support, invalidate each entry
1652          */
1653         shift = mmu_psize_defs[psize].shift;
1654         max_hpte_count = HPAGE_PMD_SIZE >> shift;
1655         for (i = 0; i < max_hpte_count; i++) {
1656                 /*
1657                  * 8 bits per each hpte entries
1658                  * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1659                  */
1660                 valid = hpte_valid(hpte_slot_array, i);
1661                 if (!valid)
1662                         continue;
1663                 hidx =  hpte_hash_index(hpte_slot_array, i);
1664 
1665                 /* get the vpn */
1666                 addr = s_addr + (i * (1ul << shift));
1667                 vpn = hpt_vpn(addr, vsid, ssize);
1668                 hash = hpt_hash(vpn, shift, ssize);
1669                 if (hidx & _PTEIDX_SECONDARY)
1670                         hash = ~hash;
1671 
1672                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1673                 slot += hidx & _PTEIDX_GROUP_IX;
1674                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1675                                              MMU_PAGE_16M, ssize, local);
1676         }
1677 tm_abort:
1678         tm_flush_hash_page(local);
1679 }
1680 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1681 
1682 void flush_hash_range(unsigned long number, int local)
1683 {
1684         if (mmu_hash_ops.flush_hash_range)
1685                 mmu_hash_ops.flush_hash_range(number, local);
1686         else {
1687                 int i;
1688                 struct ppc64_tlb_batch *batch =
1689                         this_cpu_ptr(&ppc64_tlb_batch);
1690 
1691                 for (i = 0; i < number; i++)
1692                         flush_hash_page(batch->vpn[i], batch->pte[i],
1693                                         batch->psize, batch->ssize, local);
1694         }
1695 }
1696 
1697 /*
1698  * low_hash_fault is called when we the low level hash code failed
1699  * to instert a PTE due to an hypervisor error
1700  */
1701 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1702 {
1703         enum ctx_state prev_state = exception_enter();
1704 
1705         if (user_mode(regs)) {
1706 #ifdef CONFIG_PPC_SUBPAGE_PROT
1707                 if (rc == -2)
1708                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1709                 else
1710 #endif
1711                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1712         } else
1713                 bad_page_fault(regs, address, SIGBUS);
1714 
1715         exception_exit(prev_state);
1716 }
1717 
1718 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1719                            unsigned long pa, unsigned long rflags,
1720                            unsigned long vflags, int psize, int ssize)
1721 {
1722         unsigned long hpte_group;
1723         long slot;
1724 
1725 repeat:
1726         hpte_group = ((hash & htab_hash_mask) *
1727                        HPTES_PER_GROUP) & ~0x7UL;
1728 
1729         /* Insert into the hash table, primary slot */
1730         slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1731                                         psize, psize, ssize);
1732 
1733         /* Primary is full, try the secondary */
1734         if (unlikely(slot == -1)) {
1735                 hpte_group = ((~hash & htab_hash_mask) *
1736                               HPTES_PER_GROUP) & ~0x7UL;
1737                 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1738                                                 vflags | HPTE_V_SECONDARY,
1739                                                 psize, psize, ssize);
1740                 if (slot == -1) {
1741                         if (mftb() & 0x1)
1742                                 hpte_group = ((hash & htab_hash_mask) *
1743                                               HPTES_PER_GROUP)&~0x7UL;
1744 
1745                         mmu_hash_ops.hpte_remove(hpte_group);
1746                         goto repeat;
1747                 }
1748         }
1749 
1750         return slot;
1751 }
1752 
1753 #ifdef CONFIG_DEBUG_PAGEALLOC
1754 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1755 {
1756         unsigned long hash;
1757         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1758         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1759         unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1760         long ret;
1761 
1762         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1763 
1764         /* Don't create HPTE entries for bad address */
1765         if (!vsid)
1766                 return;
1767 
1768         ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1769                                     HPTE_V_BOLTED,
1770                                     mmu_linear_psize, mmu_kernel_ssize);
1771 
1772         BUG_ON (ret < 0);
1773         spin_lock(&linear_map_hash_lock);
1774         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1775         linear_map_hash_slots[lmi] = ret | 0x80;
1776         spin_unlock(&linear_map_hash_lock);
1777 }
1778 
1779 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1780 {
1781         unsigned long hash, hidx, slot;
1782         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1783         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1784 
1785         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1786         spin_lock(&linear_map_hash_lock);
1787         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1788         hidx = linear_map_hash_slots[lmi] & 0x7f;
1789         linear_map_hash_slots[lmi] = 0;
1790         spin_unlock(&linear_map_hash_lock);
1791         if (hidx & _PTEIDX_SECONDARY)
1792                 hash = ~hash;
1793         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1794         slot += hidx & _PTEIDX_GROUP_IX;
1795         mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1796                                      mmu_linear_psize,
1797                                      mmu_kernel_ssize, 0);
1798 }
1799 
1800 void __kernel_map_pages(struct page *page, int numpages, int enable)
1801 {
1802         unsigned long flags, vaddr, lmi;
1803         int i;
1804 
1805         local_irq_save(flags);
1806         for (i = 0; i < numpages; i++, page++) {
1807                 vaddr = (unsigned long)page_address(page);
1808                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1809                 if (lmi >= linear_map_hash_count)
1810                         continue;
1811                 if (enable)
1812                         kernel_map_linear_page(vaddr, lmi);
1813                 else
1814                         kernel_unmap_linear_page(vaddr, lmi);
1815         }
1816         local_irq_restore(flags);
1817 }
1818 #endif /* CONFIG_DEBUG_PAGEALLOC */
1819 
1820 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1821                                 phys_addr_t first_memblock_size)
1822 {
1823         /* We don't currently support the first MEMBLOCK not mapping 0
1824          * physical on those processors
1825          */
1826         BUG_ON(first_memblock_base != 0);
1827 
1828         /* On LPAR systems, the first entry is our RMA region,
1829          * non-LPAR 64-bit hash MMU systems don't have a limitation
1830          * on real mode access, but using the first entry works well
1831          * enough. We also clamp it to 1G to avoid some funky things
1832          * such as RTAS bugs etc...
1833          */
1834         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1835 
1836         /* Finally limit subsequent allocations */
1837         memblock_set_current_limit(ppc64_rma_size);
1838 }
1839 
1840 #ifdef CONFIG_DEBUG_FS
1841 
1842 static int hpt_order_get(void *data, u64 *val)
1843 {
1844         *val = ppc64_pft_size;
1845         return 0;
1846 }
1847 
1848 static int hpt_order_set(void *data, u64 val)
1849 {
1850         if (!mmu_hash_ops.resize_hpt)
1851                 return -ENODEV;
1852 
1853         return mmu_hash_ops.resize_hpt(val);
1854 }
1855 
1856 DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1857 
1858 static int __init hash64_debugfs(void)
1859 {
1860         if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root,
1861                                  NULL, &fops_hpt_order)) {
1862                 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1863         }
1864 
1865         return 0;
1866 }
1867 machine_device_initcall(pseries, hash64_debugfs);
1868 #endif /* CONFIG_DEBUG_FS */
1869 

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