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Linux/arch/powerpc/mm/hash_utils_64.c

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  1 /*
  2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
  3  *   {mikejc|engebret}@us.ibm.com
  4  *
  5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
  6  *
  7  * SMP scalability work:
  8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  9  * 
 10  *    Module name: htab.c
 11  *
 12  *    Description:
 13  *      PowerPC Hashed Page Table functions
 14  *
 15  * This program is free software; you can redistribute it and/or
 16  * modify it under the terms of the GNU General Public License
 17  * as published by the Free Software Foundation; either version
 18  * 2 of the License, or (at your option) any later version.
 19  */
 20 
 21 #undef DEBUG
 22 #undef DEBUG_LOW
 23 
 24 #include <linux/spinlock.h>
 25 #include <linux/errno.h>
 26 #include <linux/sched.h>
 27 #include <linux/proc_fs.h>
 28 #include <linux/stat.h>
 29 #include <linux/sysctl.h>
 30 #include <linux/export.h>
 31 #include <linux/ctype.h>
 32 #include <linux/cache.h>
 33 #include <linux/init.h>
 34 #include <linux/signal.h>
 35 #include <linux/memblock.h>
 36 #include <linux/context_tracking.h>
 37 #include <linux/libfdt.h>
 38 
 39 #include <asm/processor.h>
 40 #include <asm/pgtable.h>
 41 #include <asm/mmu.h>
 42 #include <asm/mmu_context.h>
 43 #include <asm/page.h>
 44 #include <asm/types.h>
 45 #include <asm/uaccess.h>
 46 #include <asm/machdep.h>
 47 #include <asm/prom.h>
 48 #include <asm/tlbflush.h>
 49 #include <asm/io.h>
 50 #include <asm/eeh.h>
 51 #include <asm/tlb.h>
 52 #include <asm/cacheflush.h>
 53 #include <asm/cputable.h>
 54 #include <asm/sections.h>
 55 #include <asm/copro.h>
 56 #include <asm/udbg.h>
 57 #include <asm/code-patching.h>
 58 #include <asm/fadump.h>
 59 #include <asm/firmware.h>
 60 #include <asm/tm.h>
 61 #include <asm/trace.h>
 62 #include <asm/ps3.h>
 63 
 64 #ifdef DEBUG
 65 #define DBG(fmt...) udbg_printf(fmt)
 66 #else
 67 #define DBG(fmt...)
 68 #endif
 69 
 70 #ifdef DEBUG_LOW
 71 #define DBG_LOW(fmt...) udbg_printf(fmt)
 72 #else
 73 #define DBG_LOW(fmt...)
 74 #endif
 75 
 76 #define KB (1024)
 77 #define MB (1024*KB)
 78 #define GB (1024L*MB)
 79 
 80 /*
 81  * Note:  pte   --> Linux PTE
 82  *        HPTE  --> PowerPC Hashed Page Table Entry
 83  *
 84  * Execution context:
 85  *   htab_initialize is called with the MMU off (of course), but
 86  *   the kernel has been copied down to zero so it can directly
 87  *   reference global data.  At this point it is very difficult
 88  *   to print debug info.
 89  *
 90  */
 91 
 92 static unsigned long _SDR1;
 93 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 94 EXPORT_SYMBOL_GPL(mmu_psize_defs);
 95 
 96 struct hash_pte *htab_address;
 97 unsigned long htab_size_bytes;
 98 unsigned long htab_hash_mask;
 99 EXPORT_SYMBOL_GPL(htab_hash_mask);
100 int mmu_linear_psize = MMU_PAGE_4K;
101 EXPORT_SYMBOL_GPL(mmu_linear_psize);
102 int mmu_virtual_psize = MMU_PAGE_4K;
103 int mmu_vmalloc_psize = MMU_PAGE_4K;
104 #ifdef CONFIG_SPARSEMEM_VMEMMAP
105 int mmu_vmemmap_psize = MMU_PAGE_4K;
106 #endif
107 int mmu_io_psize = MMU_PAGE_4K;
108 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
109 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
110 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
111 u16 mmu_slb_size = 64;
112 EXPORT_SYMBOL_GPL(mmu_slb_size);
113 #ifdef CONFIG_PPC_64K_PAGES
114 int mmu_ci_restrictions;
115 #endif
116 #ifdef CONFIG_DEBUG_PAGEALLOC
117 static u8 *linear_map_hash_slots;
118 static unsigned long linear_map_hash_count;
119 static DEFINE_SPINLOCK(linear_map_hash_lock);
120 #endif /* CONFIG_DEBUG_PAGEALLOC */
121 struct mmu_hash_ops mmu_hash_ops;
122 EXPORT_SYMBOL(mmu_hash_ops);
123 
124 /* There are definitions of page sizes arrays to be used when none
125  * is provided by the firmware.
126  */
127 
128 /* Pre-POWER4 CPUs (4k pages only)
129  */
130 static struct mmu_psize_def mmu_psize_defaults_old[] = {
131         [MMU_PAGE_4K] = {
132                 .shift  = 12,
133                 .sllp   = 0,
134                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
135                 .avpnm  = 0,
136                 .tlbiel = 0,
137         },
138 };
139 
140 /* POWER4, GPUL, POWER5
141  *
142  * Support for 16Mb large pages
143  */
144 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
145         [MMU_PAGE_4K] = {
146                 .shift  = 12,
147                 .sllp   = 0,
148                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
149                 .avpnm  = 0,
150                 .tlbiel = 1,
151         },
152         [MMU_PAGE_16M] = {
153                 .shift  = 24,
154                 .sllp   = SLB_VSID_L,
155                 .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
156                             [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
157                 .avpnm  = 0x1UL,
158                 .tlbiel = 0,
159         },
160 };
161 
162 /*
163  * 'R' and 'C' update notes:
164  *  - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
165  *     create writeable HPTEs without C set, because the hcall H_PROTECT
166  *     that we use in that case will not update C
167  *  - The above is however not a problem, because we also don't do that
168  *     fancy "no flush" variant of eviction and we use H_REMOVE which will
169  *     do the right thing and thus we don't have the race I described earlier
170  *
171  *    - Under bare metal,  we do have the race, so we need R and C set
172  *    - We make sure R is always set and never lost
173  *    - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
174  */
175 unsigned long htab_convert_pte_flags(unsigned long pteflags)
176 {
177         unsigned long rflags = 0;
178 
179         /* _PAGE_EXEC -> NOEXEC */
180         if ((pteflags & _PAGE_EXEC) == 0)
181                 rflags |= HPTE_R_N;
182         /*
183          * PPP bits:
184          * Linux uses slb key 0 for kernel and 1 for user.
185          * kernel RW areas are mapped with PPP=0b000
186          * User area is mapped with PPP=0b010 for read/write
187          * or PPP=0b011 for read-only (including writeable but clean pages).
188          */
189         if (pteflags & _PAGE_PRIVILEGED) {
190                 /*
191                  * Kernel read only mapped with ppp bits 0b110
192                  */
193                 if (!(pteflags & _PAGE_WRITE)) {
194                         if (mmu_has_feature(MMU_FTR_KERNEL_RO))
195                                 rflags |= (HPTE_R_PP0 | 0x2);
196                         else
197                                 rflags |= 0x3;
198                 }
199         } else {
200                 if (pteflags & _PAGE_RWX)
201                         rflags |= 0x2;
202                 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
203                         rflags |= 0x1;
204         }
205         /*
206          * We can't allow hardware to update hpte bits. Hence always
207          * set 'R' bit and set 'C' if it is a write fault
208          */
209         rflags |=  HPTE_R_R;
210 
211         if (pteflags & _PAGE_DIRTY)
212                 rflags |= HPTE_R_C;
213         /*
214          * Add in WIG bits
215          */
216 
217         if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
218                 rflags |= HPTE_R_I;
219         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
220                 rflags |= (HPTE_R_I | HPTE_R_G);
221         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
222                 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
223         else
224                 /*
225                  * Add memory coherence if cache inhibited is not set
226                  */
227                 rflags |= HPTE_R_M;
228 
229         return rflags;
230 }
231 
232 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
233                       unsigned long pstart, unsigned long prot,
234                       int psize, int ssize)
235 {
236         unsigned long vaddr, paddr;
237         unsigned int step, shift;
238         int ret = 0;
239 
240         shift = mmu_psize_defs[psize].shift;
241         step = 1 << shift;
242 
243         prot = htab_convert_pte_flags(prot);
244 
245         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
246             vstart, vend, pstart, prot, psize, ssize);
247 
248         for (vaddr = vstart, paddr = pstart; vaddr < vend;
249              vaddr += step, paddr += step) {
250                 unsigned long hash, hpteg;
251                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
252                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
253                 unsigned long tprot = prot;
254 
255                 /*
256                  * If we hit a bad address return error.
257                  */
258                 if (!vsid)
259                         return -1;
260                 /* Make kernel text executable */
261                 if (overlaps_kernel_text(vaddr, vaddr + step))
262                         tprot &= ~HPTE_R_N;
263 
264                 /* Make kvm guest trampolines executable */
265                 if (overlaps_kvm_tmp(vaddr, vaddr + step))
266                         tprot &= ~HPTE_R_N;
267 
268                 /*
269                  * If relocatable, check if it overlaps interrupt vectors that
270                  * are copied down to real 0. For relocatable kernel
271                  * (e.g. kdump case) we copy interrupt vectors down to real
272                  * address 0. Mark that region as executable. This is
273                  * because on p8 system with relocation on exception feature
274                  * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
275                  * in order to execute the interrupt handlers in virtual
276                  * mode the vector region need to be marked as executable.
277                  */
278                 if ((PHYSICAL_START > MEMORY_START) &&
279                         overlaps_interrupt_vector_text(vaddr, vaddr + step))
280                                 tprot &= ~HPTE_R_N;
281 
282                 hash = hpt_hash(vpn, shift, ssize);
283                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
284 
285                 BUG_ON(!mmu_hash_ops.hpte_insert);
286                 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
287                                                HPTE_V_BOLTED, psize, psize,
288                                                ssize);
289 
290                 if (ret < 0)
291                         break;
292 
293 #ifdef CONFIG_DEBUG_PAGEALLOC
294                 if (debug_pagealloc_enabled() &&
295                         (paddr >> PAGE_SHIFT) < linear_map_hash_count)
296                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
297 #endif /* CONFIG_DEBUG_PAGEALLOC */
298         }
299         return ret < 0 ? ret : 0;
300 }
301 
302 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
303                       int psize, int ssize)
304 {
305         unsigned long vaddr;
306         unsigned int step, shift;
307         int rc;
308         int ret = 0;
309 
310         shift = mmu_psize_defs[psize].shift;
311         step = 1 << shift;
312 
313         if (!mmu_hash_ops.hpte_removebolted)
314                 return -ENODEV;
315 
316         for (vaddr = vstart; vaddr < vend; vaddr += step) {
317                 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
318                 if (rc == -ENOENT) {
319                         ret = -ENOENT;
320                         continue;
321                 }
322                 if (rc < 0)
323                         return rc;
324         }
325 
326         return ret;
327 }
328 
329 static bool disable_1tb_segments = false;
330 
331 static int __init parse_disable_1tb_segments(char *p)
332 {
333         disable_1tb_segments = true;
334         return 0;
335 }
336 early_param("disable_1tb_segments", parse_disable_1tb_segments);
337 
338 static int __init htab_dt_scan_seg_sizes(unsigned long node,
339                                          const char *uname, int depth,
340                                          void *data)
341 {
342         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
343         const __be32 *prop;
344         int size = 0;
345 
346         /* We are scanning "cpu" nodes only */
347         if (type == NULL || strcmp(type, "cpu") != 0)
348                 return 0;
349 
350         prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
351         if (prop == NULL)
352                 return 0;
353         for (; size >= 4; size -= 4, ++prop) {
354                 if (be32_to_cpu(prop[0]) == 40) {
355                         DBG("1T segment support detected\n");
356 
357                         if (disable_1tb_segments) {
358                                 DBG("1T segments disabled by command line\n");
359                                 break;
360                         }
361 
362                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
363                         return 1;
364                 }
365         }
366         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
367         return 0;
368 }
369 
370 static int __init get_idx_from_shift(unsigned int shift)
371 {
372         int idx = -1;
373 
374         switch (shift) {
375         case 0xc:
376                 idx = MMU_PAGE_4K;
377                 break;
378         case 0x10:
379                 idx = MMU_PAGE_64K;
380                 break;
381         case 0x14:
382                 idx = MMU_PAGE_1M;
383                 break;
384         case 0x18:
385                 idx = MMU_PAGE_16M;
386                 break;
387         case 0x22:
388                 idx = MMU_PAGE_16G;
389                 break;
390         }
391         return idx;
392 }
393 
394 static int __init htab_dt_scan_page_sizes(unsigned long node,
395                                           const char *uname, int depth,
396                                           void *data)
397 {
398         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
399         const __be32 *prop;
400         int size = 0;
401 
402         /* We are scanning "cpu" nodes only */
403         if (type == NULL || strcmp(type, "cpu") != 0)
404                 return 0;
405 
406         prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
407         if (!prop)
408                 return 0;
409 
410         pr_info("Page sizes from device-tree:\n");
411         size /= 4;
412         cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
413         while(size > 0) {
414                 unsigned int base_shift = be32_to_cpu(prop[0]);
415                 unsigned int slbenc = be32_to_cpu(prop[1]);
416                 unsigned int lpnum = be32_to_cpu(prop[2]);
417                 struct mmu_psize_def *def;
418                 int idx, base_idx;
419 
420                 size -= 3; prop += 3;
421                 base_idx = get_idx_from_shift(base_shift);
422                 if (base_idx < 0) {
423                         /* skip the pte encoding also */
424                         prop += lpnum * 2; size -= lpnum * 2;
425                         continue;
426                 }
427                 def = &mmu_psize_defs[base_idx];
428                 if (base_idx == MMU_PAGE_16M)
429                         cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
430 
431                 def->shift = base_shift;
432                 if (base_shift <= 23)
433                         def->avpnm = 0;
434                 else
435                         def->avpnm = (1 << (base_shift - 23)) - 1;
436                 def->sllp = slbenc;
437                 /*
438                  * We don't know for sure what's up with tlbiel, so
439                  * for now we only set it for 4K and 64K pages
440                  */
441                 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
442                         def->tlbiel = 1;
443                 else
444                         def->tlbiel = 0;
445 
446                 while (size > 0 && lpnum) {
447                         unsigned int shift = be32_to_cpu(prop[0]);
448                         int penc  = be32_to_cpu(prop[1]);
449 
450                         prop += 2; size -= 2;
451                         lpnum--;
452 
453                         idx = get_idx_from_shift(shift);
454                         if (idx < 0)
455                                 continue;
456 
457                         if (penc == -1)
458                                 pr_err("Invalid penc for base_shift=%d "
459                                        "shift=%d\n", base_shift, shift);
460 
461                         def->penc[idx] = penc;
462                         pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
463                                 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
464                                 base_shift, shift, def->sllp,
465                                 def->avpnm, def->tlbiel, def->penc[idx]);
466                 }
467         }
468 
469         return 1;
470 }
471 
472 #ifdef CONFIG_HUGETLB_PAGE
473 /* Scan for 16G memory blocks that have been set aside for huge pages
474  * and reserve those blocks for 16G huge pages.
475  */
476 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
477                                         const char *uname, int depth,
478                                         void *data) {
479         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
480         const __be64 *addr_prop;
481         const __be32 *page_count_prop;
482         unsigned int expected_pages;
483         long unsigned int phys_addr;
484         long unsigned int block_size;
485 
486         /* We are scanning "memory" nodes only */
487         if (type == NULL || strcmp(type, "memory") != 0)
488                 return 0;
489 
490         /* This property is the log base 2 of the number of virtual pages that
491          * will represent this memory block. */
492         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
493         if (page_count_prop == NULL)
494                 return 0;
495         expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
496         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
497         if (addr_prop == NULL)
498                 return 0;
499         phys_addr = be64_to_cpu(addr_prop[0]);
500         block_size = be64_to_cpu(addr_prop[1]);
501         if (block_size != (16 * GB))
502                 return 0;
503         printk(KERN_INFO "Huge page(16GB) memory: "
504                         "addr = 0x%lX size = 0x%lX pages = %d\n",
505                         phys_addr, block_size, expected_pages);
506         if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
507                 memblock_reserve(phys_addr, block_size * expected_pages);
508                 add_gpage(phys_addr, block_size, expected_pages);
509         }
510         return 0;
511 }
512 #endif /* CONFIG_HUGETLB_PAGE */
513 
514 static void mmu_psize_set_default_penc(void)
515 {
516         int bpsize, apsize;
517         for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
518                 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
519                         mmu_psize_defs[bpsize].penc[apsize] = -1;
520 }
521 
522 #ifdef CONFIG_PPC_64K_PAGES
523 
524 static bool might_have_hea(void)
525 {
526         /*
527          * The HEA ethernet adapter requires awareness of the
528          * GX bus. Without that awareness we can easily assume
529          * we will never see an HEA ethernet device.
530          */
531 #ifdef CONFIG_IBMEBUS
532         return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
533                 firmware_has_feature(FW_FEATURE_SPLPAR);
534 #else
535         return false;
536 #endif
537 }
538 
539 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
540 
541 static void __init htab_scan_page_sizes(void)
542 {
543         int rc;
544 
545         /* se the invalid penc to -1 */
546         mmu_psize_set_default_penc();
547 
548         /* Default to 4K pages only */
549         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
550                sizeof(mmu_psize_defaults_old));
551 
552         /*
553          * Try to find the available page sizes in the device-tree
554          */
555         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
556         if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
557                 /*
558                  * Nothing in the device-tree, but the CPU supports 16M pages,
559                  * so let's fallback on a known size list for 16M capable CPUs.
560                  */
561                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
562                        sizeof(mmu_psize_defaults_gp));
563         }
564 
565 #ifdef CONFIG_HUGETLB_PAGE
566         /* Reserve 16G huge page memory sections for huge pages */
567         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
568 #endif /* CONFIG_HUGETLB_PAGE */
569 }
570 
571 static void __init htab_init_page_sizes(void)
572 {
573         if (!debug_pagealloc_enabled()) {
574                 /*
575                  * Pick a size for the linear mapping. Currently, we only
576                  * support 16M, 1M and 4K which is the default
577                  */
578                 if (mmu_psize_defs[MMU_PAGE_16M].shift)
579                         mmu_linear_psize = MMU_PAGE_16M;
580                 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
581                         mmu_linear_psize = MMU_PAGE_1M;
582         }
583 
584 #ifdef CONFIG_PPC_64K_PAGES
585         /*
586          * Pick a size for the ordinary pages. Default is 4K, we support
587          * 64K for user mappings and vmalloc if supported by the processor.
588          * We only use 64k for ioremap if the processor
589          * (and firmware) support cache-inhibited large pages.
590          * If not, we use 4k and set mmu_ci_restrictions so that
591          * hash_page knows to switch processes that use cache-inhibited
592          * mappings to 4k pages.
593          */
594         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
595                 mmu_virtual_psize = MMU_PAGE_64K;
596                 mmu_vmalloc_psize = MMU_PAGE_64K;
597                 if (mmu_linear_psize == MMU_PAGE_4K)
598                         mmu_linear_psize = MMU_PAGE_64K;
599                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
600                         /*
601                          * When running on pSeries using 64k pages for ioremap
602                          * would stop us accessing the HEA ethernet. So if we
603                          * have the chance of ever seeing one, stay at 4k.
604                          */
605                         if (!might_have_hea())
606                                 mmu_io_psize = MMU_PAGE_64K;
607                 } else
608                         mmu_ci_restrictions = 1;
609         }
610 #endif /* CONFIG_PPC_64K_PAGES */
611 
612 #ifdef CONFIG_SPARSEMEM_VMEMMAP
613         /* We try to use 16M pages for vmemmap if that is supported
614          * and we have at least 1G of RAM at boot
615          */
616         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
617             memblock_phys_mem_size() >= 0x40000000)
618                 mmu_vmemmap_psize = MMU_PAGE_16M;
619         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
620                 mmu_vmemmap_psize = MMU_PAGE_64K;
621         else
622                 mmu_vmemmap_psize = MMU_PAGE_4K;
623 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
624 
625         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
626                "virtual = %d, io = %d"
627 #ifdef CONFIG_SPARSEMEM_VMEMMAP
628                ", vmemmap = %d"
629 #endif
630                "\n",
631                mmu_psize_defs[mmu_linear_psize].shift,
632                mmu_psize_defs[mmu_virtual_psize].shift,
633                mmu_psize_defs[mmu_io_psize].shift
634 #ifdef CONFIG_SPARSEMEM_VMEMMAP
635                ,mmu_psize_defs[mmu_vmemmap_psize].shift
636 #endif
637                );
638 }
639 
640 static int __init htab_dt_scan_pftsize(unsigned long node,
641                                        const char *uname, int depth,
642                                        void *data)
643 {
644         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
645         const __be32 *prop;
646 
647         /* We are scanning "cpu" nodes only */
648         if (type == NULL || strcmp(type, "cpu") != 0)
649                 return 0;
650 
651         prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
652         if (prop != NULL) {
653                 /* pft_size[0] is the NUMA CEC cookie */
654                 ppc64_pft_size = be32_to_cpu(prop[1]);
655                 return 1;
656         }
657         return 0;
658 }
659 
660 unsigned htab_shift_for_mem_size(unsigned long mem_size)
661 {
662         unsigned memshift = __ilog2(mem_size);
663         unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
664         unsigned pteg_shift;
665 
666         /* round mem_size up to next power of 2 */
667         if ((1UL << memshift) < mem_size)
668                 memshift += 1;
669 
670         /* aim for 2 pages / pteg */
671         pteg_shift = memshift - (pshift + 1);
672 
673         /*
674          * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
675          * size permitted by the architecture.
676          */
677         return max(pteg_shift + 7, 18U);
678 }
679 
680 static unsigned long __init htab_get_table_size(void)
681 {
682         /* If hash size isn't already provided by the platform, we try to
683          * retrieve it from the device-tree. If it's not there neither, we
684          * calculate it now based on the total RAM size
685          */
686         if (ppc64_pft_size == 0)
687                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
688         if (ppc64_pft_size)
689                 return 1UL << ppc64_pft_size;
690 
691         return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
692 }
693 
694 #ifdef CONFIG_MEMORY_HOTPLUG
695 int create_section_mapping(unsigned long start, unsigned long end)
696 {
697         int rc = htab_bolt_mapping(start, end, __pa(start),
698                                    pgprot_val(PAGE_KERNEL), mmu_linear_psize,
699                                    mmu_kernel_ssize);
700 
701         if (rc < 0) {
702                 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
703                                               mmu_kernel_ssize);
704                 BUG_ON(rc2 && (rc2 != -ENOENT));
705         }
706         return rc;
707 }
708 
709 int remove_section_mapping(unsigned long start, unsigned long end)
710 {
711         int rc = htab_remove_mapping(start, end, mmu_linear_psize,
712                                      mmu_kernel_ssize);
713         WARN_ON(rc < 0);
714         return rc;
715 }
716 #endif /* CONFIG_MEMORY_HOTPLUG */
717 
718 static void __init hash_init_partition_table(phys_addr_t hash_table,
719                                              unsigned long htab_size)
720 {
721         unsigned long ps_field;
722         unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
723 
724         /*
725          * slb llp encoding for the page size used in VPM real mode.
726          * We can ignore that for lpid 0
727          */
728         ps_field = 0;
729         htab_size =  __ilog2(htab_size) - 18;
730 
731         BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
732         partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
733                                                 MEMBLOCK_ALLOC_ANYWHERE));
734 
735         /* Initialize the Partition Table with no entries */
736         memset((void *)partition_tb, 0, patb_size);
737         partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size);
738         /*
739          * FIXME!! This should be done via update_partition table
740          * For now UPRT is 0 for us.
741          */
742         partition_tb->patb1 = 0;
743         pr_info("Partition table %p\n", partition_tb);
744         /*
745          * update partition table control register,
746          * 64 K size.
747          */
748         mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
749 
750 }
751 
752 static void __init htab_initialize(void)
753 {
754         unsigned long table;
755         unsigned long pteg_count;
756         unsigned long prot;
757         unsigned long base = 0, size = 0;
758         struct memblock_region *reg;
759 
760         DBG(" -> htab_initialize()\n");
761 
762         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
763                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
764                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
765                 printk(KERN_INFO "Using 1TB segments\n");
766         }
767 
768         /*
769          * Calculate the required size of the htab.  We want the number of
770          * PTEGs to equal one half the number of real pages.
771          */ 
772         htab_size_bytes = htab_get_table_size();
773         pteg_count = htab_size_bytes >> 7;
774 
775         htab_hash_mask = pteg_count - 1;
776 
777         if (firmware_has_feature(FW_FEATURE_LPAR) ||
778             firmware_has_feature(FW_FEATURE_PS3_LV1)) {
779                 /* Using a hypervisor which owns the htab */
780                 htab_address = NULL;
781                 _SDR1 = 0; 
782 #ifdef CONFIG_FA_DUMP
783                 /*
784                  * If firmware assisted dump is active firmware preserves
785                  * the contents of htab along with entire partition memory.
786                  * Clear the htab if firmware assisted dump is active so
787                  * that we dont end up using old mappings.
788                  */
789                 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
790                         mmu_hash_ops.hpte_clear_all();
791 #endif
792         } else {
793                 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
794 
795 #ifdef CONFIG_PPC_CELL
796                 /*
797                  * Cell may require the hash table down low when using the
798                  * Axon IOMMU in order to fit the dynamic region over it, see
799                  * comments in cell/iommu.c
800                  */
801                 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
802                         limit = 0x80000000;
803                         pr_info("Hash table forced below 2G for Axon IOMMU\n");
804                 }
805 #endif /* CONFIG_PPC_CELL */
806 
807                 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
808                                             limit);
809 
810                 DBG("Hash table allocated at %lx, size: %lx\n", table,
811                     htab_size_bytes);
812 
813                 htab_address = __va(table);
814 
815                 /* htab absolute addr + encoded htabsize */
816                 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
817 
818                 /* Initialize the HPT with no entries */
819                 memset((void *)table, 0, htab_size_bytes);
820 
821                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
822                         /* Set SDR1 */
823                         mtspr(SPRN_SDR1, _SDR1);
824                 else
825                         hash_init_partition_table(table, htab_size_bytes);
826         }
827 
828         prot = pgprot_val(PAGE_KERNEL);
829 
830 #ifdef CONFIG_DEBUG_PAGEALLOC
831         if (debug_pagealloc_enabled()) {
832                 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
833                 linear_map_hash_slots = __va(memblock_alloc_base(
834                                 linear_map_hash_count, 1, ppc64_rma_size));
835                 memset(linear_map_hash_slots, 0, linear_map_hash_count);
836         }
837 #endif /* CONFIG_DEBUG_PAGEALLOC */
838 
839         /* On U3 based machines, we need to reserve the DART area and
840          * _NOT_ map it to avoid cache paradoxes as it's remapped non
841          * cacheable later on
842          */
843 
844         /* create bolted the linear mapping in the hash table */
845         for_each_memblock(memory, reg) {
846                 base = (unsigned long)__va(reg->base);
847                 size = reg->size;
848 
849                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
850                     base, size, prot);
851 
852                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
853                                 prot, mmu_linear_psize, mmu_kernel_ssize));
854         }
855         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
856 
857         /*
858          * If we have a memory_limit and we've allocated TCEs then we need to
859          * explicitly map the TCE area at the top of RAM. We also cope with the
860          * case that the TCEs start below memory_limit.
861          * tce_alloc_start/end are 16MB aligned so the mapping should work
862          * for either 4K or 16MB pages.
863          */
864         if (tce_alloc_start) {
865                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
866                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
867 
868                 if (base + size >= tce_alloc_start)
869                         tce_alloc_start = base + size + 1;
870 
871                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
872                                          __pa(tce_alloc_start), prot,
873                                          mmu_linear_psize, mmu_kernel_ssize));
874         }
875 
876 
877         DBG(" <- htab_initialize()\n");
878 }
879 #undef KB
880 #undef MB
881 
882 void __init hash__early_init_devtree(void)
883 {
884         /* Initialize segment sizes */
885         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
886 
887         /* Initialize page sizes */
888         htab_scan_page_sizes();
889 }
890 
891 void __init hash__early_init_mmu(void)
892 {
893         htab_init_page_sizes();
894 
895         /*
896          * initialize page table size
897          */
898         __pte_frag_nr = H_PTE_FRAG_NR;
899         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
900 
901         __pte_index_size = H_PTE_INDEX_SIZE;
902         __pmd_index_size = H_PMD_INDEX_SIZE;
903         __pud_index_size = H_PUD_INDEX_SIZE;
904         __pgd_index_size = H_PGD_INDEX_SIZE;
905         __pmd_cache_index = H_PMD_CACHE_INDEX;
906         __pte_table_size = H_PTE_TABLE_SIZE;
907         __pmd_table_size = H_PMD_TABLE_SIZE;
908         __pud_table_size = H_PUD_TABLE_SIZE;
909         __pgd_table_size = H_PGD_TABLE_SIZE;
910         /*
911          * 4k use hugepd format, so for hash set then to
912          * zero
913          */
914         __pmd_val_bits = 0;
915         __pud_val_bits = 0;
916         __pgd_val_bits = 0;
917 
918         __kernel_virt_start = H_KERN_VIRT_START;
919         __kernel_virt_size = H_KERN_VIRT_SIZE;
920         __vmalloc_start = H_VMALLOC_START;
921         __vmalloc_end = H_VMALLOC_END;
922         vmemmap = (struct page *)H_VMEMMAP_BASE;
923         ioremap_bot = IOREMAP_BASE;
924 
925 #ifdef CONFIG_PCI
926         pci_io_base = ISA_IO_BASE;
927 #endif
928 
929         /* Select appropriate backend */
930         if (firmware_has_feature(FW_FEATURE_PS3_LV1))
931                 ps3_early_mm_init();
932         else if (firmware_has_feature(FW_FEATURE_LPAR))
933                 hpte_init_pseries();
934         else if (IS_ENABLED(CONFIG_PPC_NATIVE))
935                 hpte_init_native();
936 
937         if (!mmu_hash_ops.hpte_insert)
938                 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
939 
940         /* Initialize the MMU Hash table and create the linear mapping
941          * of memory. Has to be done before SLB initialization as this is
942          * currently where the page size encoding is obtained.
943          */
944         htab_initialize();
945 
946         pr_info("Initializing hash mmu with SLB\n");
947         /* Initialize SLB management */
948         slb_initialize();
949 }
950 
951 #ifdef CONFIG_SMP
952 void hash__early_init_mmu_secondary(void)
953 {
954         /* Initialize hash table for that CPU */
955         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
956                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
957                         mtspr(SPRN_SDR1, _SDR1);
958                 else
959                         mtspr(SPRN_PTCR,
960                               __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
961         }
962         /* Initialize SLB */
963         slb_initialize();
964 }
965 #endif /* CONFIG_SMP */
966 
967 /*
968  * Called by asm hashtable.S for doing lazy icache flush
969  */
970 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
971 {
972         struct page *page;
973 
974         if (!pfn_valid(pte_pfn(pte)))
975                 return pp;
976 
977         page = pte_page(pte);
978 
979         /* page is dirty */
980         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
981                 if (trap == 0x400) {
982                         flush_dcache_icache_page(page);
983                         set_bit(PG_arch_1, &page->flags);
984                 } else
985                         pp |= HPTE_R_N;
986         }
987         return pp;
988 }
989 
990 #ifdef CONFIG_PPC_MM_SLICES
991 static unsigned int get_paca_psize(unsigned long addr)
992 {
993         u64 lpsizes;
994         unsigned char *hpsizes;
995         unsigned long index, mask_index;
996 
997         if (addr < SLICE_LOW_TOP) {
998                 lpsizes = get_paca()->mm_ctx_low_slices_psize;
999                 index = GET_LOW_SLICE_INDEX(addr);
1000                 return (lpsizes >> (index * 4)) & 0xF;
1001         }
1002         hpsizes = get_paca()->mm_ctx_high_slices_psize;
1003         index = GET_HIGH_SLICE_INDEX(addr);
1004         mask_index = index & 0x1;
1005         return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1006 }
1007 
1008 #else
1009 unsigned int get_paca_psize(unsigned long addr)
1010 {
1011         return get_paca()->mm_ctx_user_psize;
1012 }
1013 #endif
1014 
1015 /*
1016  * Demote a segment to using 4k pages.
1017  * For now this makes the whole process use 4k pages.
1018  */
1019 #ifdef CONFIG_PPC_64K_PAGES
1020 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1021 {
1022         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1023                 return;
1024         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1025         copro_flush_all_slbs(mm);
1026         if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1027 
1028                 copy_mm_to_paca(&mm->context);
1029                 slb_flush_and_rebolt();
1030         }
1031 }
1032 #endif /* CONFIG_PPC_64K_PAGES */
1033 
1034 #ifdef CONFIG_PPC_SUBPAGE_PROT
1035 /*
1036  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1037  * Userspace sets the subpage permissions using the subpage_prot system call.
1038  *
1039  * Result is 0: full permissions, _PAGE_RW: read-only,
1040  * _PAGE_RWX: no access.
1041  */
1042 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1043 {
1044         struct subpage_prot_table *spt = &mm->context.spt;
1045         u32 spp = 0;
1046         u32 **sbpm, *sbpp;
1047 
1048         if (ea >= spt->maxaddr)
1049                 return 0;
1050         if (ea < 0x100000000UL) {
1051                 /* addresses below 4GB use spt->low_prot */
1052                 sbpm = spt->low_prot;
1053         } else {
1054                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1055                 if (!sbpm)
1056                         return 0;
1057         }
1058         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1059         if (!sbpp)
1060                 return 0;
1061         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1062 
1063         /* extract 2-bit bitfield for this 4k subpage */
1064         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1065 
1066         /*
1067          * 0 -> full premission
1068          * 1 -> Read only
1069          * 2 -> no access.
1070          * We return the flag that need to be cleared.
1071          */
1072         spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1073         return spp;
1074 }
1075 
1076 #else /* CONFIG_PPC_SUBPAGE_PROT */
1077 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1078 {
1079         return 0;
1080 }
1081 #endif
1082 
1083 void hash_failure_debug(unsigned long ea, unsigned long access,
1084                         unsigned long vsid, unsigned long trap,
1085                         int ssize, int psize, int lpsize, unsigned long pte)
1086 {
1087         if (!printk_ratelimit())
1088                 return;
1089         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1090                 ea, access, current->comm);
1091         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1092                 trap, vsid, ssize, psize, lpsize, pte);
1093 }
1094 
1095 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1096                              int psize, bool user_region)
1097 {
1098         if (user_region) {
1099                 if (psize != get_paca_psize(ea)) {
1100                         copy_mm_to_paca(&mm->context);
1101                         slb_flush_and_rebolt();
1102                 }
1103         } else if (get_paca()->vmalloc_sllp !=
1104                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1105                 get_paca()->vmalloc_sllp =
1106                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1107                 slb_vmalloc_update();
1108         }
1109 }
1110 
1111 /* Result code is:
1112  *  0 - handled
1113  *  1 - normal page fault
1114  * -1 - critical hash insertion error
1115  * -2 - access not permitted by subpage protection mechanism
1116  */
1117 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1118                  unsigned long access, unsigned long trap,
1119                  unsigned long flags)
1120 {
1121         bool is_thp;
1122         enum ctx_state prev_state = exception_enter();
1123         pgd_t *pgdir;
1124         unsigned long vsid;
1125         pte_t *ptep;
1126         unsigned hugeshift;
1127         const struct cpumask *tmp;
1128         int rc, user_region = 0;
1129         int psize, ssize;
1130 
1131         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1132                 ea, access, trap);
1133         trace_hash_fault(ea, access, trap);
1134 
1135         /* Get region & vsid */
1136         switch (REGION_ID(ea)) {
1137         case USER_REGION_ID:
1138                 user_region = 1;
1139                 if (! mm) {
1140                         DBG_LOW(" user region with no mm !\n");
1141                         rc = 1;
1142                         goto bail;
1143                 }
1144                 psize = get_slice_psize(mm, ea);
1145                 ssize = user_segment_size(ea);
1146                 vsid = get_vsid(mm->context.id, ea, ssize);
1147                 break;
1148         case VMALLOC_REGION_ID:
1149                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1150                 if (ea < VMALLOC_END)
1151                         psize = mmu_vmalloc_psize;
1152                 else
1153                         psize = mmu_io_psize;
1154                 ssize = mmu_kernel_ssize;
1155                 break;
1156         default:
1157                 /* Not a valid range
1158                  * Send the problem up to do_page_fault 
1159                  */
1160                 rc = 1;
1161                 goto bail;
1162         }
1163         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1164 
1165         /* Bad address. */
1166         if (!vsid) {
1167                 DBG_LOW("Bad address!\n");
1168                 rc = 1;
1169                 goto bail;
1170         }
1171         /* Get pgdir */
1172         pgdir = mm->pgd;
1173         if (pgdir == NULL) {
1174                 rc = 1;
1175                 goto bail;
1176         }
1177 
1178         /* Check CPU locality */
1179         tmp = cpumask_of(smp_processor_id());
1180         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1181                 flags |= HPTE_LOCAL_UPDATE;
1182 
1183 #ifndef CONFIG_PPC_64K_PAGES
1184         /* If we use 4K pages and our psize is not 4K, then we might
1185          * be hitting a special driver mapping, and need to align the
1186          * address before we fetch the PTE.
1187          *
1188          * It could also be a hugepage mapping, in which case this is
1189          * not necessary, but it's not harmful, either.
1190          */
1191         if (psize != MMU_PAGE_4K)
1192                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1193 #endif /* CONFIG_PPC_64K_PAGES */
1194 
1195         /* Get PTE and page size from page tables */
1196         ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1197         if (ptep == NULL || !pte_present(*ptep)) {
1198                 DBG_LOW(" no PTE !\n");
1199                 rc = 1;
1200                 goto bail;
1201         }
1202 
1203         /* Add _PAGE_PRESENT to the required access perm */
1204         access |= _PAGE_PRESENT;
1205 
1206         /* Pre-check access permissions (will be re-checked atomically
1207          * in __hash_page_XX but this pre-check is a fast path
1208          */
1209         if (!check_pte_access(access, pte_val(*ptep))) {
1210                 DBG_LOW(" no access !\n");
1211                 rc = 1;
1212                 goto bail;
1213         }
1214 
1215         if (hugeshift) {
1216                 if (is_thp)
1217                         rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1218                                              trap, flags, ssize, psize);
1219 #ifdef CONFIG_HUGETLB_PAGE
1220                 else
1221                         rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1222                                               flags, ssize, hugeshift, psize);
1223 #else
1224                 else {
1225                         /*
1226                          * if we have hugeshift, and is not transhuge with
1227                          * hugetlb disabled, something is really wrong.
1228                          */
1229                         rc = 1;
1230                         WARN_ON(1);
1231                 }
1232 #endif
1233                 if (current->mm == mm)
1234                         check_paca_psize(ea, mm, psize, user_region);
1235 
1236                 goto bail;
1237         }
1238 
1239 #ifndef CONFIG_PPC_64K_PAGES
1240         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1241 #else
1242         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1243                 pte_val(*(ptep + PTRS_PER_PTE)));
1244 #endif
1245         /* Do actual hashing */
1246 #ifdef CONFIG_PPC_64K_PAGES
1247         /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1248         if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1249                 demote_segment_4k(mm, ea);
1250                 psize = MMU_PAGE_4K;
1251         }
1252 
1253         /* If this PTE is non-cacheable and we have restrictions on
1254          * using non cacheable large pages, then we switch to 4k
1255          */
1256         if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1257                 if (user_region) {
1258                         demote_segment_4k(mm, ea);
1259                         psize = MMU_PAGE_4K;
1260                 } else if (ea < VMALLOC_END) {
1261                         /*
1262                          * some driver did a non-cacheable mapping
1263                          * in vmalloc space, so switch vmalloc
1264                          * to 4k pages
1265                          */
1266                         printk(KERN_ALERT "Reducing vmalloc segment "
1267                                "to 4kB pages because of "
1268                                "non-cacheable mapping\n");
1269                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1270                         copro_flush_all_slbs(mm);
1271                 }
1272         }
1273 
1274 #endif /* CONFIG_PPC_64K_PAGES */
1275 
1276         if (current->mm == mm)
1277                 check_paca_psize(ea, mm, psize, user_region);
1278 
1279 #ifdef CONFIG_PPC_64K_PAGES
1280         if (psize == MMU_PAGE_64K)
1281                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1282                                      flags, ssize);
1283         else
1284 #endif /* CONFIG_PPC_64K_PAGES */
1285         {
1286                 int spp = subpage_protection(mm, ea);
1287                 if (access & spp)
1288                         rc = -2;
1289                 else
1290                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1291                                             flags, ssize, spp);
1292         }
1293 
1294         /* Dump some info in case of hash insertion failure, they should
1295          * never happen so it is really useful to know if/when they do
1296          */
1297         if (rc == -1)
1298                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1299                                    psize, pte_val(*ptep));
1300 #ifndef CONFIG_PPC_64K_PAGES
1301         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1302 #else
1303         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1304                 pte_val(*(ptep + PTRS_PER_PTE)));
1305 #endif
1306         DBG_LOW(" -> rc=%d\n", rc);
1307 
1308 bail:
1309         exception_exit(prev_state);
1310         return rc;
1311 }
1312 EXPORT_SYMBOL_GPL(hash_page_mm);
1313 
1314 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1315               unsigned long dsisr)
1316 {
1317         unsigned long flags = 0;
1318         struct mm_struct *mm = current->mm;
1319 
1320         if (REGION_ID(ea) == VMALLOC_REGION_ID)
1321                 mm = &init_mm;
1322 
1323         if (dsisr & DSISR_NOHPTE)
1324                 flags |= HPTE_NOHPTE_UPDATE;
1325 
1326         return hash_page_mm(mm, ea, access, trap, flags);
1327 }
1328 EXPORT_SYMBOL_GPL(hash_page);
1329 
1330 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1331                 unsigned long dsisr)
1332 {
1333         unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1334         unsigned long flags = 0;
1335         struct mm_struct *mm = current->mm;
1336 
1337         if (REGION_ID(ea) == VMALLOC_REGION_ID)
1338                 mm = &init_mm;
1339 
1340         if (dsisr & DSISR_NOHPTE)
1341                 flags |= HPTE_NOHPTE_UPDATE;
1342 
1343         if (dsisr & DSISR_ISSTORE)
1344                 access |= _PAGE_WRITE;
1345         /*
1346          * We set _PAGE_PRIVILEGED only when
1347          * kernel mode access kernel space.
1348          *
1349          * _PAGE_PRIVILEGED is NOT set
1350          * 1) when kernel mode access user space
1351          * 2) user space access kernel space.
1352          */
1353         access |= _PAGE_PRIVILEGED;
1354         if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1355                 access &= ~_PAGE_PRIVILEGED;
1356 
1357         if (trap == 0x400)
1358                 access |= _PAGE_EXEC;
1359 
1360         return hash_page_mm(mm, ea, access, trap, flags);
1361 }
1362 
1363 #ifdef CONFIG_PPC_MM_SLICES
1364 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1365 {
1366         int psize = get_slice_psize(mm, ea);
1367 
1368         /* We only prefault standard pages for now */
1369         if (unlikely(psize != mm->context.user_psize))
1370                 return false;
1371 
1372         /*
1373          * Don't prefault if subpage protection is enabled for the EA.
1374          */
1375         if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1376                 return false;
1377 
1378         return true;
1379 }
1380 #else
1381 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1382 {
1383         return true;
1384 }
1385 #endif
1386 
1387 void hash_preload(struct mm_struct *mm, unsigned long ea,
1388                   unsigned long access, unsigned long trap)
1389 {
1390         int hugepage_shift;
1391         unsigned long vsid;
1392         pgd_t *pgdir;
1393         pte_t *ptep;
1394         unsigned long flags;
1395         int rc, ssize, update_flags = 0;
1396 
1397         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1398 
1399         if (!should_hash_preload(mm, ea))
1400                 return;
1401 
1402         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1403                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1404 
1405         /* Get Linux PTE if available */
1406         pgdir = mm->pgd;
1407         if (pgdir == NULL)
1408                 return;
1409 
1410         /* Get VSID */
1411         ssize = user_segment_size(ea);
1412         vsid = get_vsid(mm->context.id, ea, ssize);
1413         if (!vsid)
1414                 return;
1415         /*
1416          * Hash doesn't like irqs. Walking linux page table with irq disabled
1417          * saves us from holding multiple locks.
1418          */
1419         local_irq_save(flags);
1420 
1421         /*
1422          * THP pages use update_mmu_cache_pmd. We don't do
1423          * hash preload there. Hence can ignore THP here
1424          */
1425         ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1426         if (!ptep)
1427                 goto out_exit;
1428 
1429         WARN_ON(hugepage_shift);
1430 #ifdef CONFIG_PPC_64K_PAGES
1431         /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1432          * a 64K kernel), then we don't preload, hash_page() will take
1433          * care of it once we actually try to access the page.
1434          * That way we don't have to duplicate all of the logic for segment
1435          * page size demotion here
1436          */
1437         if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1438                 goto out_exit;
1439 #endif /* CONFIG_PPC_64K_PAGES */
1440 
1441         /* Is that local to this CPU ? */
1442         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1443                 update_flags |= HPTE_LOCAL_UPDATE;
1444 
1445         /* Hash it in */
1446 #ifdef CONFIG_PPC_64K_PAGES
1447         if (mm->context.user_psize == MMU_PAGE_64K)
1448                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1449                                      update_flags, ssize);
1450         else
1451 #endif /* CONFIG_PPC_64K_PAGES */
1452                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1453                                     ssize, subpage_protection(mm, ea));
1454 
1455         /* Dump some info in case of hash insertion failure, they should
1456          * never happen so it is really useful to know if/when they do
1457          */
1458         if (rc == -1)
1459                 hash_failure_debug(ea, access, vsid, trap, ssize,
1460                                    mm->context.user_psize,
1461                                    mm->context.user_psize,
1462                                    pte_val(*ptep));
1463 out_exit:
1464         local_irq_restore(flags);
1465 }
1466 
1467 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1468  *          do not forget to update the assembly call site !
1469  */
1470 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1471                      unsigned long flags)
1472 {
1473         unsigned long hash, index, shift, hidx, slot;
1474         int local = flags & HPTE_LOCAL_UPDATE;
1475 
1476         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1477         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1478                 hash = hpt_hash(vpn, shift, ssize);
1479                 hidx = __rpte_to_hidx(pte, index);
1480                 if (hidx & _PTEIDX_SECONDARY)
1481                         hash = ~hash;
1482                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1483                 slot += hidx & _PTEIDX_GROUP_IX;
1484                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1485                 /*
1486                  * We use same base page size and actual psize, because we don't
1487                  * use these functions for hugepage
1488                  */
1489                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1490                                              ssize, local);
1491         } pte_iterate_hashed_end();
1492 
1493 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1494         /* Transactions are not aborted by tlbiel, only tlbie.
1495          * Without, syncing a page back to a block device w/ PIO could pick up
1496          * transactional data (bad!) so we force an abort here.  Before the
1497          * sync the page will be made read-only, which will flush_hash_page.
1498          * BIG ISSUE here: if the kernel uses a page from userspace without
1499          * unmapping it first, it may see the speculated version.
1500          */
1501         if (local && cpu_has_feature(CPU_FTR_TM) &&
1502             current->thread.regs &&
1503             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1504                 tm_enable();
1505                 tm_abort(TM_CAUSE_TLBI);
1506         }
1507 #endif
1508 }
1509 
1510 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1511 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1512                          pmd_t *pmdp, unsigned int psize, int ssize,
1513                          unsigned long flags)
1514 {
1515         int i, max_hpte_count, valid;
1516         unsigned long s_addr;
1517         unsigned char *hpte_slot_array;
1518         unsigned long hidx, shift, vpn, hash, slot;
1519         int local = flags & HPTE_LOCAL_UPDATE;
1520 
1521         s_addr = addr & HPAGE_PMD_MASK;
1522         hpte_slot_array = get_hpte_slot_array(pmdp);
1523         /*
1524          * IF we try to do a HUGE PTE update after a withdraw is done.
1525          * we will find the below NULL. This happens when we do
1526          * split_huge_page_pmd
1527          */
1528         if (!hpte_slot_array)
1529                 return;
1530 
1531         if (mmu_hash_ops.hugepage_invalidate) {
1532                 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1533                                                  psize, ssize, local);
1534                 goto tm_abort;
1535         }
1536         /*
1537          * No bluk hpte removal support, invalidate each entry
1538          */
1539         shift = mmu_psize_defs[psize].shift;
1540         max_hpte_count = HPAGE_PMD_SIZE >> shift;
1541         for (i = 0; i < max_hpte_count; i++) {
1542                 /*
1543                  * 8 bits per each hpte entries
1544                  * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1545                  */
1546                 valid = hpte_valid(hpte_slot_array, i);
1547                 if (!valid)
1548                         continue;
1549                 hidx =  hpte_hash_index(hpte_slot_array, i);
1550 
1551                 /* get the vpn */
1552                 addr = s_addr + (i * (1ul << shift));
1553                 vpn = hpt_vpn(addr, vsid, ssize);
1554                 hash = hpt_hash(vpn, shift, ssize);
1555                 if (hidx & _PTEIDX_SECONDARY)
1556                         hash = ~hash;
1557 
1558                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1559                 slot += hidx & _PTEIDX_GROUP_IX;
1560                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1561                                              MMU_PAGE_16M, ssize, local);
1562         }
1563 tm_abort:
1564 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1565         /* Transactions are not aborted by tlbiel, only tlbie.
1566          * Without, syncing a page back to a block device w/ PIO could pick up
1567          * transactional data (bad!) so we force an abort here.  Before the
1568          * sync the page will be made read-only, which will flush_hash_page.
1569          * BIG ISSUE here: if the kernel uses a page from userspace without
1570          * unmapping it first, it may see the speculated version.
1571          */
1572         if (local && cpu_has_feature(CPU_FTR_TM) &&
1573             current->thread.regs &&
1574             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1575                 tm_enable();
1576                 tm_abort(TM_CAUSE_TLBI);
1577         }
1578 #endif
1579         return;
1580 }
1581 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1582 
1583 void flush_hash_range(unsigned long number, int local)
1584 {
1585         if (mmu_hash_ops.flush_hash_range)
1586                 mmu_hash_ops.flush_hash_range(number, local);
1587         else {
1588                 int i;
1589                 struct ppc64_tlb_batch *batch =
1590                         this_cpu_ptr(&ppc64_tlb_batch);
1591 
1592                 for (i = 0; i < number; i++)
1593                         flush_hash_page(batch->vpn[i], batch->pte[i],
1594                                         batch->psize, batch->ssize, local);
1595         }
1596 }
1597 
1598 /*
1599  * low_hash_fault is called when we the low level hash code failed
1600  * to instert a PTE due to an hypervisor error
1601  */
1602 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1603 {
1604         enum ctx_state prev_state = exception_enter();
1605 
1606         if (user_mode(regs)) {
1607 #ifdef CONFIG_PPC_SUBPAGE_PROT
1608                 if (rc == -2)
1609                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1610                 else
1611 #endif
1612                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1613         } else
1614                 bad_page_fault(regs, address, SIGBUS);
1615 
1616         exception_exit(prev_state);
1617 }
1618 
1619 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1620                            unsigned long pa, unsigned long rflags,
1621                            unsigned long vflags, int psize, int ssize)
1622 {
1623         unsigned long hpte_group;
1624         long slot;
1625 
1626 repeat:
1627         hpte_group = ((hash & htab_hash_mask) *
1628                        HPTES_PER_GROUP) & ~0x7UL;
1629 
1630         /* Insert into the hash table, primary slot */
1631         slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1632                                         psize, psize, ssize);
1633 
1634         /* Primary is full, try the secondary */
1635         if (unlikely(slot == -1)) {
1636                 hpte_group = ((~hash & htab_hash_mask) *
1637                               HPTES_PER_GROUP) & ~0x7UL;
1638                 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1639                                                 vflags | HPTE_V_SECONDARY,
1640                                                 psize, psize, ssize);
1641                 if (slot == -1) {
1642                         if (mftb() & 0x1)
1643                                 hpte_group = ((hash & htab_hash_mask) *
1644                                               HPTES_PER_GROUP)&~0x7UL;
1645 
1646                         mmu_hash_ops.hpte_remove(hpte_group);
1647                         goto repeat;
1648                 }
1649         }
1650 
1651         return slot;
1652 }
1653 
1654 #ifdef CONFIG_DEBUG_PAGEALLOC
1655 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1656 {
1657         unsigned long hash;
1658         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1659         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1660         unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1661         long ret;
1662 
1663         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1664 
1665         /* Don't create HPTE entries for bad address */
1666         if (!vsid)
1667                 return;
1668 
1669         ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1670                                     HPTE_V_BOLTED,
1671                                     mmu_linear_psize, mmu_kernel_ssize);
1672 
1673         BUG_ON (ret < 0);
1674         spin_lock(&linear_map_hash_lock);
1675         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1676         linear_map_hash_slots[lmi] = ret | 0x80;
1677         spin_unlock(&linear_map_hash_lock);
1678 }
1679 
1680 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1681 {
1682         unsigned long hash, hidx, slot;
1683         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1684         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1685 
1686         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1687         spin_lock(&linear_map_hash_lock);
1688         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1689         hidx = linear_map_hash_slots[lmi] & 0x7f;
1690         linear_map_hash_slots[lmi] = 0;
1691         spin_unlock(&linear_map_hash_lock);
1692         if (hidx & _PTEIDX_SECONDARY)
1693                 hash = ~hash;
1694         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1695         slot += hidx & _PTEIDX_GROUP_IX;
1696         mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1697                                      mmu_linear_psize,
1698                                      mmu_kernel_ssize, 0);
1699 }
1700 
1701 void __kernel_map_pages(struct page *page, int numpages, int enable)
1702 {
1703         unsigned long flags, vaddr, lmi;
1704         int i;
1705 
1706         local_irq_save(flags);
1707         for (i = 0; i < numpages; i++, page++) {
1708                 vaddr = (unsigned long)page_address(page);
1709                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1710                 if (lmi >= linear_map_hash_count)
1711                         continue;
1712                 if (enable)
1713                         kernel_map_linear_page(vaddr, lmi);
1714                 else
1715                         kernel_unmap_linear_page(vaddr, lmi);
1716         }
1717         local_irq_restore(flags);
1718 }
1719 #endif /* CONFIG_DEBUG_PAGEALLOC */
1720 
1721 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1722                                 phys_addr_t first_memblock_size)
1723 {
1724         /* We don't currently support the first MEMBLOCK not mapping 0
1725          * physical on those processors
1726          */
1727         BUG_ON(first_memblock_base != 0);
1728 
1729         /* On LPAR systems, the first entry is our RMA region,
1730          * non-LPAR 64-bit hash MMU systems don't have a limitation
1731          * on real mode access, but using the first entry works well
1732          * enough. We also clamp it to 1G to avoid some funky things
1733          * such as RTAS bugs etc...
1734          */
1735         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1736 
1737         /* Finally limit subsequent allocations */
1738         memblock_set_current_limit(ppc64_rma_size);
1739 }
1740 

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