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Linux/arch/powerpc/perf/e6500-pmu.c

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  1 /*
  2  * Performance counter support for e6500 family processors.
  3  *
  4  * Author: Priyanka Jain, Priyanka.Jain@freescale.com
  5  * Based on e500-pmu.c
  6  * Copyright 2013 Freescale Semiconductor, Inc.
  7  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
  8  *
  9  * This program is free software; you can redistribute it and/or
 10  * modify it under the terms of the GNU General Public License
 11  * as published by the Free Software Foundation; either version
 12  * 2 of the License, or (at your option) any later version.
 13  */
 14 
 15 #include <linux/string.h>
 16 #include <linux/perf_event.h>
 17 #include <asm/reg.h>
 18 #include <asm/cputable.h>
 19 
 20 /*
 21  * Map of generic hardware event types to hardware events
 22  * Zero if unsupported
 23  */
 24 static int e6500_generic_events[] = {
 25         [PERF_COUNT_HW_CPU_CYCLES] = 1,
 26         [PERF_COUNT_HW_INSTRUCTIONS] = 2,
 27         [PERF_COUNT_HW_CACHE_MISSES] = 221,
 28         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
 29         [PERF_COUNT_HW_BRANCH_MISSES] = 15,
 30 };
 31 
 32 #define C(x)    PERF_COUNT_HW_CACHE_##x
 33 
 34 /*
 35  * Table of generalized cache-related events.
 36  * 0 means not supported, -1 means nonsensical, other values
 37  * are event codes.
 38  */
 39 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 40         [C(L1D)] = {
 41                                 /*RESULT_ACCESS         RESULT_MISS */
 42                 [C(OP_READ)] = {        27,             222     },
 43                 [C(OP_WRITE)] = {       28,             223     },
 44                 [C(OP_PREFETCH)] = {    29,             0       },
 45         },
 46         [C(L1I)] = {
 47                                 /*RESULT_ACCESS         RESULT_MISS */
 48                 [C(OP_READ)] = {        2,              254     },
 49                 [C(OP_WRITE)] = {       -1,             -1      },
 50                 [C(OP_PREFETCH)] = {    37,             0       },
 51         },
 52         /*
 53          * Assuming LL means L2, it's not a good match for this model.
 54          * It does not have separate read/write events (but it does have
 55          * separate instruction/data events).
 56          */
 57         [C(LL)] = {
 58                                 /*RESULT_ACCESS         RESULT_MISS */
 59                 [C(OP_READ)] = {        0,              0       },
 60                 [C(OP_WRITE)] = {       0,              0       },
 61                 [C(OP_PREFETCH)] = {    0,              0       },
 62         },
 63         /*
 64          * There are data/instruction MMU misses, but that's a miss on
 65          * the chip's internal level-one TLB which is probably not
 66          * what the user wants.  Instead, unified level-two TLB misses
 67          * are reported here.
 68          */
 69         [C(DTLB)] = {
 70                                 /*RESULT_ACCESS         RESULT_MISS */
 71                 [C(OP_READ)] = {        26,             66      },
 72                 [C(OP_WRITE)] = {       -1,             -1      },
 73                 [C(OP_PREFETCH)] = {    -1,             -1      },
 74         },
 75         [C(BPU)] = {
 76                                 /*RESULT_ACCESS         RESULT_MISS */
 77                 [C(OP_READ)] = {        12,             15      },
 78                 [C(OP_WRITE)] = {       -1,             -1      },
 79                 [C(OP_PREFETCH)] = {    -1,             -1      },
 80         },
 81         [C(NODE)] = {
 82                                 /* RESULT_ACCESS        RESULT_MISS */
 83                 [C(OP_READ)] = {        -1,             -1      },
 84                 [C(OP_WRITE)] = {       -1,             -1      },
 85                 [C(OP_PREFETCH)] = {    -1,             -1      },
 86         },
 87 };
 88 
 89 static int num_events = 512;
 90 
 91 /* Upper half of event id is PMLCb, for threshold events */
 92 static u64 e6500_xlate_event(u64 event_id)
 93 {
 94         u32 event_low = (u32)event_id;
 95         if (event_low >= num_events ||
 96                 (event_id & (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)))
 97                 return 0;
 98 
 99         return FSL_EMB_EVENT_VALID;
100 }
101 
102 static struct fsl_emb_pmu e6500_pmu = {
103         .name                   = "e6500 family",
104         .n_counter              = 6,
105         .n_restricted           = 0,
106         .xlate_event            = e6500_xlate_event,
107         .n_generic              = ARRAY_SIZE(e6500_generic_events),
108         .generic_events         = e6500_generic_events,
109         .cache_events           = &e6500_cache_events,
110 };
111 
112 static int init_e6500_pmu(void)
113 {
114         if (!cur_cpu_spec->oprofile_cpu_type ||
115                 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e6500"))
116                 return -ENODEV;
117 
118         return register_fsl_emb_pmu(&e6500_pmu);
119 }
120 
121 early_initcall(init_e6500_pmu);
122 

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