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Linux/arch/powerpc/perf/imc-pmu.c

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  1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*
  3  * In-Memory Collection (IMC) Performance Monitor counter support.
  4  *
  5  * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
  6  *           (C) 2017 Anju T Sudhakar, IBM Corporation.
  7  *           (C) 2017 Hemant K Shaw, IBM Corporation.
  8  */
  9 #include <linux/perf_event.h>
 10 #include <linux/slab.h>
 11 #include <asm/opal.h>
 12 #include <asm/imc-pmu.h>
 13 #include <asm/cputhreads.h>
 14 #include <asm/smp.h>
 15 #include <linux/string.h>
 16 
 17 /* Nest IMC data structures and variables */
 18 
 19 /*
 20  * Used to avoid races in counting the nest-pmu units during hotplug
 21  * register and unregister
 22  */
 23 static DEFINE_MUTEX(nest_init_lock);
 24 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
 25 static struct imc_pmu **per_nest_pmu_arr;
 26 static cpumask_t nest_imc_cpumask;
 27 static struct imc_pmu_ref *nest_imc_refc;
 28 static int nest_pmus;
 29 
 30 /* Core IMC data structures and variables */
 31 
 32 static cpumask_t core_imc_cpumask;
 33 static struct imc_pmu_ref *core_imc_refc;
 34 static struct imc_pmu *core_imc_pmu;
 35 
 36 /* Thread IMC data structures and variables */
 37 
 38 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
 39 static struct imc_pmu *thread_imc_pmu;
 40 static int thread_imc_mem_size;
 41 
 42 /* Trace IMC data structures */
 43 static DEFINE_PER_CPU(u64 *, trace_imc_mem);
 44 static struct imc_pmu_ref *trace_imc_refc;
 45 static int trace_imc_mem_size;
 46 
 47 /*
 48  * Global data structure used to avoid races between thread,
 49  * core and trace-imc
 50  */
 51 static struct imc_pmu_ref imc_global_refc = {
 52         .lock = __MUTEX_INITIALIZER(imc_global_refc.lock),
 53         .id = 0,
 54         .refc = 0,
 55 };
 56 
 57 static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
 58 {
 59         return container_of(event->pmu, struct imc_pmu, pmu);
 60 }
 61 
 62 PMU_FORMAT_ATTR(event, "config:0-61");
 63 PMU_FORMAT_ATTR(offset, "config:0-31");
 64 PMU_FORMAT_ATTR(rvalue, "config:32");
 65 PMU_FORMAT_ATTR(mode, "config:33-40");
 66 static struct attribute *imc_format_attrs[] = {
 67         &format_attr_event.attr,
 68         &format_attr_offset.attr,
 69         &format_attr_rvalue.attr,
 70         &format_attr_mode.attr,
 71         NULL,
 72 };
 73 
 74 static struct attribute_group imc_format_group = {
 75         .name = "format",
 76         .attrs = imc_format_attrs,
 77 };
 78 
 79 /* Format attribute for imc trace-mode */
 80 PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
 81 PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
 82 PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
 83 PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
 84 static struct attribute *trace_imc_format_attrs[] = {
 85         &format_attr_event.attr,
 86         &format_attr_cpmc_reserved.attr,
 87         &format_attr_cpmc_event.attr,
 88         &format_attr_cpmc_samplesel.attr,
 89         &format_attr_cpmc_load.attr,
 90         NULL,
 91 };
 92 
 93 static struct attribute_group trace_imc_format_group = {
 94 .name = "format",
 95 .attrs = trace_imc_format_attrs,
 96 };
 97 
 98 /* Get the cpumask printed to a buffer "buf" */
 99 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
100                                         struct device_attribute *attr,
101                                         char *buf)
102 {
103         struct pmu *pmu = dev_get_drvdata(dev);
104         struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
105         cpumask_t *active_mask;
106 
107         switch(imc_pmu->domain){
108         case IMC_DOMAIN_NEST:
109                 active_mask = &nest_imc_cpumask;
110                 break;
111         case IMC_DOMAIN_CORE:
112                 active_mask = &core_imc_cpumask;
113                 break;
114         default:
115                 return 0;
116         }
117 
118         return cpumap_print_to_pagebuf(true, buf, active_mask);
119 }
120 
121 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
122 
123 static struct attribute *imc_pmu_cpumask_attrs[] = {
124         &dev_attr_cpumask.attr,
125         NULL,
126 };
127 
128 static struct attribute_group imc_pmu_cpumask_attr_group = {
129         .attrs = imc_pmu_cpumask_attrs,
130 };
131 
132 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
133 static struct attribute *device_str_attr_create(const char *name, const char *str)
134 {
135         struct perf_pmu_events_attr *attr;
136 
137         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
138         if (!attr)
139                 return NULL;
140         sysfs_attr_init(&attr->attr.attr);
141 
142         attr->event_str = str;
143         attr->attr.attr.name = name;
144         attr->attr.attr.mode = 0444;
145         attr->attr.show = perf_event_sysfs_show;
146 
147         return &attr->attr.attr;
148 }
149 
150 static int imc_parse_event(struct device_node *np, const char *scale,
151                                   const char *unit, const char *prefix,
152                                   u32 base, struct imc_events *event)
153 {
154         const char *s;
155         u32 reg;
156 
157         if (of_property_read_u32(np, "reg", &reg))
158                 goto error;
159         /* Add the base_reg value to the "reg" */
160         event->value = base + reg;
161 
162         if (of_property_read_string(np, "event-name", &s))
163                 goto error;
164 
165         event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
166         if (!event->name)
167                 goto error;
168 
169         if (of_property_read_string(np, "scale", &s))
170                 s = scale;
171 
172         if (s) {
173                 event->scale = kstrdup(s, GFP_KERNEL);
174                 if (!event->scale)
175                         goto error;
176         }
177 
178         if (of_property_read_string(np, "unit", &s))
179                 s = unit;
180 
181         if (s) {
182                 event->unit = kstrdup(s, GFP_KERNEL);
183                 if (!event->unit)
184                         goto error;
185         }
186 
187         return 0;
188 error:
189         kfree(event->unit);
190         kfree(event->scale);
191         kfree(event->name);
192         return -EINVAL;
193 }
194 
195 /*
196  * imc_free_events: Function to cleanup the events list, having
197  *                  "nr_entries".
198  */
199 static void imc_free_events(struct imc_events *events, int nr_entries)
200 {
201         int i;
202 
203         /* Nothing to clean, return */
204         if (!events)
205                 return;
206         for (i = 0; i < nr_entries; i++) {
207                 kfree(events[i].unit);
208                 kfree(events[i].scale);
209                 kfree(events[i].name);
210         }
211 
212         kfree(events);
213 }
214 
215 /*
216  * update_events_in_group: Update the "events" information in an attr_group
217  *                         and assign the attr_group to the pmu "pmu".
218  */
219 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
220 {
221         struct attribute_group *attr_group;
222         struct attribute **attrs, *dev_str;
223         struct device_node *np, *pmu_events;
224         u32 handle, base_reg;
225         int i = 0, j = 0, ct, ret;
226         const char *prefix, *g_scale, *g_unit;
227         const char *ev_val_str, *ev_scale_str, *ev_unit_str;
228 
229         if (!of_property_read_u32(node, "events", &handle))
230                 pmu_events = of_find_node_by_phandle(handle);
231         else
232                 return 0;
233 
234         /* Did not find any node with a given phandle */
235         if (!pmu_events)
236                 return 0;
237 
238         /* Get a count of number of child nodes */
239         ct = of_get_child_count(pmu_events);
240 
241         /* Get the event prefix */
242         if (of_property_read_string(node, "events-prefix", &prefix))
243                 return 0;
244 
245         /* Get a global unit and scale data if available */
246         if (of_property_read_string(node, "scale", &g_scale))
247                 g_scale = NULL;
248 
249         if (of_property_read_string(node, "unit", &g_unit))
250                 g_unit = NULL;
251 
252         /* "reg" property gives out the base offset of the counters data */
253         of_property_read_u32(node, "reg", &base_reg);
254 
255         /* Allocate memory for the events */
256         pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
257         if (!pmu->events)
258                 return -ENOMEM;
259 
260         ct = 0;
261         /* Parse the events and update the struct */
262         for_each_child_of_node(pmu_events, np) {
263                 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
264                 if (!ret)
265                         ct++;
266         }
267 
268         /* Allocate memory for attribute group */
269         attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
270         if (!attr_group) {
271                 imc_free_events(pmu->events, ct);
272                 return -ENOMEM;
273         }
274 
275         /*
276          * Allocate memory for attributes.
277          * Since we have count of events for this pmu, we also allocate
278          * memory for the scale and unit attribute for now.
279          * "ct" has the total event structs added from the events-parent node.
280          * So allocate three times the "ct" (this includes event, event_scale and
281          * event_unit).
282          */
283         attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
284         if (!attrs) {
285                 kfree(attr_group);
286                 imc_free_events(pmu->events, ct);
287                 return -ENOMEM;
288         }
289 
290         attr_group->name = "events";
291         attr_group->attrs = attrs;
292         do {
293                 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
294                 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
295                 if (!dev_str)
296                         continue;
297 
298                 attrs[j++] = dev_str;
299                 if (pmu->events[i].scale) {
300                         ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
301                         dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
302                         if (!dev_str)
303                                 continue;
304 
305                         attrs[j++] = dev_str;
306                 }
307 
308                 if (pmu->events[i].unit) {
309                         ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
310                         dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
311                         if (!dev_str)
312                                 continue;
313 
314                         attrs[j++] = dev_str;
315                 }
316         } while (++i < ct);
317 
318         /* Save the event attribute */
319         pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
320 
321         return 0;
322 }
323 
324 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
325 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
326 {
327         return per_cpu(local_nest_imc_refc, cpu);
328 }
329 
330 static void nest_change_cpu_context(int old_cpu, int new_cpu)
331 {
332         struct imc_pmu **pn = per_nest_pmu_arr;
333 
334         if (old_cpu < 0 || new_cpu < 0)
335                 return;
336 
337         while (*pn) {
338                 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
339                 pn++;
340         }
341 }
342 
343 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
344 {
345         int nid, target = -1;
346         const struct cpumask *l_cpumask;
347         struct imc_pmu_ref *ref;
348 
349         /*
350          * Check in the designated list for this cpu. Dont bother
351          * if not one of them.
352          */
353         if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
354                 return 0;
355 
356         /*
357          * Check whether nest_imc is registered. We could end up here if the
358          * cpuhotplug callback registration fails. i.e, callback invokes the
359          * offline path for all successfully registered nodes. At this stage,
360          * nest_imc pmu will not be registered and we should return here.
361          *
362          * We return with a zero since this is not an offline failure. And
363          * cpuhp_setup_state() returns the actual failure reason to the caller,
364          * which in turn will call the cleanup routine.
365          */
366         if (!nest_pmus)
367                 return 0;
368 
369         /*
370          * Now that this cpu is one of the designated,
371          * find a next cpu a) which is online and b) in same chip.
372          */
373         nid = cpu_to_node(cpu);
374         l_cpumask = cpumask_of_node(nid);
375         target = cpumask_last(l_cpumask);
376 
377         /*
378          * If this(target) is the last cpu in the cpumask for this chip,
379          * check for any possible online cpu in the chip.
380          */
381         if (unlikely(target == cpu))
382                 target = cpumask_any_but(l_cpumask, cpu);
383 
384         /*
385          * Update the cpumask with the target cpu and
386          * migrate the context if needed
387          */
388         if (target >= 0 && target < nr_cpu_ids) {
389                 cpumask_set_cpu(target, &nest_imc_cpumask);
390                 nest_change_cpu_context(cpu, target);
391         } else {
392                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
393                                        get_hard_smp_processor_id(cpu));
394                 /*
395                  * If this is the last cpu in this chip then, skip the reference
396                  * count mutex lock and make the reference count on this chip zero.
397                  */
398                 ref = get_nest_pmu_ref(cpu);
399                 if (!ref)
400                         return -EINVAL;
401 
402                 ref->refc = 0;
403         }
404         return 0;
405 }
406 
407 static int ppc_nest_imc_cpu_online(unsigned int cpu)
408 {
409         const struct cpumask *l_cpumask;
410         static struct cpumask tmp_mask;
411         int res;
412 
413         /* Get the cpumask of this node */
414         l_cpumask = cpumask_of_node(cpu_to_node(cpu));
415 
416         /*
417          * If this is not the first online CPU on this node, then
418          * just return.
419          */
420         if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
421                 return 0;
422 
423         /*
424          * If this is the first online cpu on this node
425          * disable the nest counters by making an OPAL call.
426          */
427         res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
428                                      get_hard_smp_processor_id(cpu));
429         if (res)
430                 return res;
431 
432         /* Make this CPU the designated target for counter collection */
433         cpumask_set_cpu(cpu, &nest_imc_cpumask);
434         return 0;
435 }
436 
437 static int nest_pmu_cpumask_init(void)
438 {
439         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
440                                  "perf/powerpc/imc:online",
441                                  ppc_nest_imc_cpu_online,
442                                  ppc_nest_imc_cpu_offline);
443 }
444 
445 static void nest_imc_counters_release(struct perf_event *event)
446 {
447         int rc, node_id;
448         struct imc_pmu_ref *ref;
449 
450         if (event->cpu < 0)
451                 return;
452 
453         node_id = cpu_to_node(event->cpu);
454 
455         /*
456          * See if we need to disable the nest PMU.
457          * If no events are currently in use, then we have to take a
458          * mutex to ensure that we don't race with another task doing
459          * enable or disable the nest counters.
460          */
461         ref = get_nest_pmu_ref(event->cpu);
462         if (!ref)
463                 return;
464 
465         /* Take the mutex lock for this node and then decrement the reference count */
466         mutex_lock(&ref->lock);
467         if (ref->refc == 0) {
468                 /*
469                  * The scenario where this is true is, when perf session is
470                  * started, followed by offlining of all cpus in a given node.
471                  *
472                  * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
473                  * function set the ref->count to zero, if the cpu which is
474                  * about to offline is the last cpu in a given node and make
475                  * an OPAL call to disable the engine in that node.
476                  *
477                  */
478                 mutex_unlock(&ref->lock);
479                 return;
480         }
481         ref->refc--;
482         if (ref->refc == 0) {
483                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
484                                             get_hard_smp_processor_id(event->cpu));
485                 if (rc) {
486                         mutex_unlock(&ref->lock);
487                         pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
488                         return;
489                 }
490         } else if (ref->refc < 0) {
491                 WARN(1, "nest-imc: Invalid event reference count\n");
492                 ref->refc = 0;
493         }
494         mutex_unlock(&ref->lock);
495 }
496 
497 static int nest_imc_event_init(struct perf_event *event)
498 {
499         int chip_id, rc, node_id;
500         u32 l_config, config = event->attr.config;
501         struct imc_mem_info *pcni;
502         struct imc_pmu *pmu;
503         struct imc_pmu_ref *ref;
504         bool flag = false;
505 
506         if (event->attr.type != event->pmu->type)
507                 return -ENOENT;
508 
509         /* Sampling not supported */
510         if (event->hw.sample_period)
511                 return -EINVAL;
512 
513         if (event->cpu < 0)
514                 return -EINVAL;
515 
516         pmu = imc_event_to_pmu(event);
517 
518         /* Sanity check for config (event offset) */
519         if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
520                 return -EINVAL;
521 
522         /*
523          * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
524          * Get the base memory addresss for this cpu.
525          */
526         chip_id = cpu_to_chip_id(event->cpu);
527 
528         /* Return, if chip_id is not valid */
529         if (chip_id < 0)
530                 return -ENODEV;
531 
532         pcni = pmu->mem_info;
533         do {
534                 if (pcni->id == chip_id) {
535                         flag = true;
536                         break;
537                 }
538                 pcni++;
539         } while (pcni->vbase != 0);
540 
541         if (!flag)
542                 return -ENODEV;
543 
544         /*
545          * Add the event offset to the base address.
546          */
547         l_config = config & IMC_EVENT_OFFSET_MASK;
548         event->hw.event_base = (u64)pcni->vbase + l_config;
549         node_id = cpu_to_node(event->cpu);
550 
551         /*
552          * Get the imc_pmu_ref struct for this node.
553          * Take the mutex lock and then increment the count of nest pmu events
554          * inited.
555          */
556         ref = get_nest_pmu_ref(event->cpu);
557         if (!ref)
558                 return -EINVAL;
559 
560         mutex_lock(&ref->lock);
561         if (ref->refc == 0) {
562                 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
563                                              get_hard_smp_processor_id(event->cpu));
564                 if (rc) {
565                         mutex_unlock(&ref->lock);
566                         pr_err("nest-imc: Unable to start the counters for node %d\n",
567                                                                         node_id);
568                         return rc;
569                 }
570         }
571         ++ref->refc;
572         mutex_unlock(&ref->lock);
573 
574         event->destroy = nest_imc_counters_release;
575         return 0;
576 }
577 
578 /*
579  * core_imc_mem_init : Initializes memory for the current core.
580  *
581  * Uses alloc_pages_node() and uses the returned address as an argument to
582  * an opal call to configure the pdbar. The address sent as an argument is
583  * converted to physical address before the opal call is made. This is the
584  * base address at which the core imc counters are populated.
585  */
586 static int core_imc_mem_init(int cpu, int size)
587 {
588         int nid, rc = 0, core_id = (cpu / threads_per_core);
589         struct imc_mem_info *mem_info;
590         struct page *page;
591 
592         /*
593          * alloc_pages_node() will allocate memory for core in the
594          * local node only.
595          */
596         nid = cpu_to_node(cpu);
597         mem_info = &core_imc_pmu->mem_info[core_id];
598         mem_info->id = core_id;
599 
600         /* We need only vbase for core counters */
601         page = alloc_pages_node(nid,
602                                 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
603                                 __GFP_NOWARN, get_order(size));
604         if (!page)
605                 return -ENOMEM;
606         mem_info->vbase = page_address(page);
607 
608         /* Init the mutex */
609         core_imc_refc[core_id].id = core_id;
610         mutex_init(&core_imc_refc[core_id].lock);
611 
612         rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
613                                 __pa((void *)mem_info->vbase),
614                                 get_hard_smp_processor_id(cpu));
615         if (rc) {
616                 free_pages((u64)mem_info->vbase, get_order(size));
617                 mem_info->vbase = NULL;
618         }
619 
620         return rc;
621 }
622 
623 static bool is_core_imc_mem_inited(int cpu)
624 {
625         struct imc_mem_info *mem_info;
626         int core_id = (cpu / threads_per_core);
627 
628         mem_info = &core_imc_pmu->mem_info[core_id];
629         if (!mem_info->vbase)
630                 return false;
631 
632         return true;
633 }
634 
635 static int ppc_core_imc_cpu_online(unsigned int cpu)
636 {
637         const struct cpumask *l_cpumask;
638         static struct cpumask tmp_mask;
639         int ret = 0;
640 
641         /* Get the cpumask for this core */
642         l_cpumask = cpu_sibling_mask(cpu);
643 
644         /* If a cpu for this core is already set, then, don't do anything */
645         if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
646                 return 0;
647 
648         if (!is_core_imc_mem_inited(cpu)) {
649                 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
650                 if (ret) {
651                         pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
652                         return ret;
653                 }
654         }
655 
656         /* set the cpu in the mask */
657         cpumask_set_cpu(cpu, &core_imc_cpumask);
658         return 0;
659 }
660 
661 static int ppc_core_imc_cpu_offline(unsigned int cpu)
662 {
663         unsigned int core_id;
664         int ncpu;
665         struct imc_pmu_ref *ref;
666 
667         /*
668          * clear this cpu out of the mask, if not present in the mask,
669          * don't bother doing anything.
670          */
671         if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
672                 return 0;
673 
674         /*
675          * Check whether core_imc is registered. We could end up here
676          * if the cpuhotplug callback registration fails. i.e, callback
677          * invokes the offline path for all sucessfully registered cpus.
678          * At this stage, core_imc pmu will not be registered and we
679          * should return here.
680          *
681          * We return with a zero since this is not an offline failure.
682          * And cpuhp_setup_state() returns the actual failure reason
683          * to the caller, which inturn will call the cleanup routine.
684          */
685         if (!core_imc_pmu->pmu.event_init)
686                 return 0;
687 
688         /* Find any online cpu in that core except the current "cpu" */
689         ncpu = cpumask_last(cpu_sibling_mask(cpu));
690 
691         if (unlikely(ncpu == cpu))
692                 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
693 
694         if (ncpu >= 0 && ncpu < nr_cpu_ids) {
695                 cpumask_set_cpu(ncpu, &core_imc_cpumask);
696                 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
697         } else {
698                 /*
699                  * If this is the last cpu in this core then, skip taking refernce
700                  * count mutex lock for this core and directly zero "refc" for
701                  * this core.
702                  */
703                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
704                                        get_hard_smp_processor_id(cpu));
705                 core_id = cpu / threads_per_core;
706                 ref = &core_imc_refc[core_id];
707                 if (!ref)
708                         return -EINVAL;
709 
710                 ref->refc = 0;
711                 /*
712                  * Reduce the global reference count, if this is the
713                  * last cpu in this core and core-imc event running
714                  * in this cpu.
715                  */
716                 mutex_lock(&imc_global_refc.lock);
717                 if (imc_global_refc.id == IMC_DOMAIN_CORE)
718                         imc_global_refc.refc--;
719 
720                 mutex_unlock(&imc_global_refc.lock);
721         }
722         return 0;
723 }
724 
725 static int core_imc_pmu_cpumask_init(void)
726 {
727         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
728                                  "perf/powerpc/imc_core:online",
729                                  ppc_core_imc_cpu_online,
730                                  ppc_core_imc_cpu_offline);
731 }
732 
733 static void reset_global_refc(struct perf_event *event)
734 {
735                 mutex_lock(&imc_global_refc.lock);
736                 imc_global_refc.refc--;
737 
738                 /*
739                  * If no other thread is running any
740                  * event for this domain(thread/core/trace),
741                  * set the global id to zero.
742                  */
743                 if (imc_global_refc.refc <= 0) {
744                         imc_global_refc.refc = 0;
745                         imc_global_refc.id = 0;
746                 }
747                 mutex_unlock(&imc_global_refc.lock);
748 }
749 
750 static void core_imc_counters_release(struct perf_event *event)
751 {
752         int rc, core_id;
753         struct imc_pmu_ref *ref;
754 
755         if (event->cpu < 0)
756                 return;
757         /*
758          * See if we need to disable the IMC PMU.
759          * If no events are currently in use, then we have to take a
760          * mutex to ensure that we don't race with another task doing
761          * enable or disable the core counters.
762          */
763         core_id = event->cpu / threads_per_core;
764 
765         /* Take the mutex lock and decrement the refernce count for this core */
766         ref = &core_imc_refc[core_id];
767         if (!ref)
768                 return;
769 
770         mutex_lock(&ref->lock);
771         if (ref->refc == 0) {
772                 /*
773                  * The scenario where this is true is, when perf session is
774                  * started, followed by offlining of all cpus in a given core.
775                  *
776                  * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
777                  * function set the ref->count to zero, if the cpu which is
778                  * about to offline is the last cpu in a given core and make
779                  * an OPAL call to disable the engine in that core.
780                  *
781                  */
782                 mutex_unlock(&ref->lock);
783                 return;
784         }
785         ref->refc--;
786         if (ref->refc == 0) {
787                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
788                                             get_hard_smp_processor_id(event->cpu));
789                 if (rc) {
790                         mutex_unlock(&ref->lock);
791                         pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
792                         return;
793                 }
794         } else if (ref->refc < 0) {
795                 WARN(1, "core-imc: Invalid event reference count\n");
796                 ref->refc = 0;
797         }
798         mutex_unlock(&ref->lock);
799 
800         reset_global_refc(event);
801 }
802 
803 static int core_imc_event_init(struct perf_event *event)
804 {
805         int core_id, rc;
806         u64 config = event->attr.config;
807         struct imc_mem_info *pcmi;
808         struct imc_pmu *pmu;
809         struct imc_pmu_ref *ref;
810 
811         if (event->attr.type != event->pmu->type)
812                 return -ENOENT;
813 
814         /* Sampling not supported */
815         if (event->hw.sample_period)
816                 return -EINVAL;
817 
818         if (event->cpu < 0)
819                 return -EINVAL;
820 
821         event->hw.idx = -1;
822         pmu = imc_event_to_pmu(event);
823 
824         /* Sanity check for config (event offset) */
825         if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
826                 return -EINVAL;
827 
828         if (!is_core_imc_mem_inited(event->cpu))
829                 return -ENODEV;
830 
831         core_id = event->cpu / threads_per_core;
832         pcmi = &core_imc_pmu->mem_info[core_id];
833         if ((!pcmi->vbase))
834                 return -ENODEV;
835 
836         /* Get the core_imc mutex for this core */
837         ref = &core_imc_refc[core_id];
838         if (!ref)
839                 return -EINVAL;
840 
841         /*
842          * Core pmu units are enabled only when it is used.
843          * See if this is triggered for the first time.
844          * If yes, take the mutex lock and enable the core counters.
845          * If not, just increment the count in core_imc_refc struct.
846          */
847         mutex_lock(&ref->lock);
848         if (ref->refc == 0) {
849                 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
850                                              get_hard_smp_processor_id(event->cpu));
851                 if (rc) {
852                         mutex_unlock(&ref->lock);
853                         pr_err("core-imc: Unable to start the counters for core %d\n",
854                                                                         core_id);
855                         return rc;
856                 }
857         }
858         ++ref->refc;
859         mutex_unlock(&ref->lock);
860 
861         /*
862          * Since the system can run either in accumulation or trace-mode
863          * of IMC at a time, core-imc events are allowed only if no other
864          * trace/thread imc events are enabled/monitored.
865          *
866          * Take the global lock, and check the refc.id
867          * to know whether any other trace/thread imc
868          * events are running.
869          */
870         mutex_lock(&imc_global_refc.lock);
871         if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_CORE) {
872                 /*
873                  * No other trace/thread imc events are running in
874                  * the system, so set the refc.id to core-imc.
875                  */
876                 imc_global_refc.id = IMC_DOMAIN_CORE;
877                 imc_global_refc.refc++;
878         } else {
879                 mutex_unlock(&imc_global_refc.lock);
880                 return -EBUSY;
881         }
882         mutex_unlock(&imc_global_refc.lock);
883 
884         event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
885         event->destroy = core_imc_counters_release;
886         return 0;
887 }
888 
889 /*
890  * Allocates a page of memory for each of the online cpus, and load
891  * LDBAR with 0.
892  * The physical base address of the page allocated for a cpu will be
893  * written to the LDBAR for that cpu, when the thread-imc event
894  * is added.
895  *
896  * LDBAR Register Layout:
897  *
898  *  0          4         8         12        16        20        24        28
899  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
900  *   | |       [   ]    [                   Counter Address [8:50]
901  *   | * Mode    |
902  *   |           * PB Scope
903  *   * Enable/Disable
904  *
905  *  32        36        40        44        48        52        56        60
906  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
907  *           Counter Address [8:50]              ]
908  *
909  */
910 static int thread_imc_mem_alloc(int cpu_id, int size)
911 {
912         u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
913         int nid = cpu_to_node(cpu_id);
914 
915         if (!local_mem) {
916                 struct page *page;
917                 /*
918                  * This case could happen only once at start, since we dont
919                  * free the memory in cpu offline path.
920                  */
921                 page = alloc_pages_node(nid,
922                                   GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
923                                   __GFP_NOWARN, get_order(size));
924                 if (!page)
925                         return -ENOMEM;
926                 local_mem = page_address(page);
927 
928                 per_cpu(thread_imc_mem, cpu_id) = local_mem;
929         }
930 
931         mtspr(SPRN_LDBAR, 0);
932         return 0;
933 }
934 
935 static int ppc_thread_imc_cpu_online(unsigned int cpu)
936 {
937         return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
938 }
939 
940 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
941 {
942         /*
943          * Set the bit 0 of LDBAR to zero.
944          *
945          * If bit 0 of LDBAR is unset, it will stop posting
946          * the counter data to memory.
947          * For thread-imc, bit 0 of LDBAR will be set to 1 in the
948          * event_add function. So reset this bit here, to stop the updates
949          * to memory in the cpu_offline path.
950          */
951         mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
952 
953         /* Reduce the refc if thread-imc event running on this cpu */
954         mutex_lock(&imc_global_refc.lock);
955         if (imc_global_refc.id == IMC_DOMAIN_THREAD)
956                 imc_global_refc.refc--;
957         mutex_unlock(&imc_global_refc.lock);
958 
959         return 0;
960 }
961 
962 static int thread_imc_cpu_init(void)
963 {
964         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
965                           "perf/powerpc/imc_thread:online",
966                           ppc_thread_imc_cpu_online,
967                           ppc_thread_imc_cpu_offline);
968 }
969 
970 static int thread_imc_event_init(struct perf_event *event)
971 {
972         u32 config = event->attr.config;
973         struct task_struct *target;
974         struct imc_pmu *pmu;
975 
976         if (event->attr.type != event->pmu->type)
977                 return -ENOENT;
978 
979         if (!perfmon_capable())
980                 return -EACCES;
981 
982         /* Sampling not supported */
983         if (event->hw.sample_period)
984                 return -EINVAL;
985 
986         event->hw.idx = -1;
987         pmu = imc_event_to_pmu(event);
988 
989         /* Sanity check for config offset */
990         if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
991                 return -EINVAL;
992 
993         target = event->hw.target;
994         if (!target)
995                 return -EINVAL;
996 
997         mutex_lock(&imc_global_refc.lock);
998         /*
999          * Check if any other trace/core imc events are running in the
1000          * system, if not set the global id to thread-imc.
1001          */
1002         if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_THREAD) {
1003                 imc_global_refc.id = IMC_DOMAIN_THREAD;
1004                 imc_global_refc.refc++;
1005         } else {
1006                 mutex_unlock(&imc_global_refc.lock);
1007                 return -EBUSY;
1008         }
1009         mutex_unlock(&imc_global_refc.lock);
1010 
1011         event->pmu->task_ctx_nr = perf_sw_context;
1012         event->destroy = reset_global_refc;
1013         return 0;
1014 }
1015 
1016 static bool is_thread_imc_pmu(struct perf_event *event)
1017 {
1018         if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
1019                 return true;
1020 
1021         return false;
1022 }
1023 
1024 static u64 * get_event_base_addr(struct perf_event *event)
1025 {
1026         u64 addr;
1027 
1028         if (is_thread_imc_pmu(event)) {
1029                 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
1030                 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
1031         }
1032 
1033         return (u64 *)event->hw.event_base;
1034 }
1035 
1036 static void thread_imc_pmu_start_txn(struct pmu *pmu,
1037                                      unsigned int txn_flags)
1038 {
1039         if (txn_flags & ~PERF_PMU_TXN_ADD)
1040                 return;
1041         perf_pmu_disable(pmu);
1042 }
1043 
1044 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
1045 {
1046         perf_pmu_enable(pmu);
1047 }
1048 
1049 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
1050 {
1051         perf_pmu_enable(pmu);
1052         return 0;
1053 }
1054 
1055 static u64 imc_read_counter(struct perf_event *event)
1056 {
1057         u64 *addr, data;
1058 
1059         /*
1060          * In-Memory Collection (IMC) counters are free flowing counters.
1061          * So we take a snapshot of the counter value on enable and save it
1062          * to calculate the delta at later stage to present the event counter
1063          * value.
1064          */
1065         addr = get_event_base_addr(event);
1066         data = be64_to_cpu(READ_ONCE(*addr));
1067         local64_set(&event->hw.prev_count, data);
1068 
1069         return data;
1070 }
1071 
1072 static void imc_event_update(struct perf_event *event)
1073 {
1074         u64 counter_prev, counter_new, final_count;
1075 
1076         counter_prev = local64_read(&event->hw.prev_count);
1077         counter_new = imc_read_counter(event);
1078         final_count = counter_new - counter_prev;
1079 
1080         /* Update the delta to the event count */
1081         local64_add(final_count, &event->count);
1082 }
1083 
1084 static void imc_event_start(struct perf_event *event, int flags)
1085 {
1086         /*
1087          * In Memory Counters are free flowing counters. HW or the microcode
1088          * keeps adding to the counter offset in memory. To get event
1089          * counter value, we snapshot the value here and we calculate
1090          * delta at later point.
1091          */
1092         imc_read_counter(event);
1093 }
1094 
1095 static void imc_event_stop(struct perf_event *event, int flags)
1096 {
1097         /*
1098          * Take a snapshot and calculate the delta and update
1099          * the event counter values.
1100          */
1101         imc_event_update(event);
1102 }
1103 
1104 static int imc_event_add(struct perf_event *event, int flags)
1105 {
1106         if (flags & PERF_EF_START)
1107                 imc_event_start(event, flags);
1108 
1109         return 0;
1110 }
1111 
1112 static int thread_imc_event_add(struct perf_event *event, int flags)
1113 {
1114         int core_id;
1115         struct imc_pmu_ref *ref;
1116         u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1117 
1118         if (flags & PERF_EF_START)
1119                 imc_event_start(event, flags);
1120 
1121         if (!is_core_imc_mem_inited(smp_processor_id()))
1122                 return -EINVAL;
1123 
1124         core_id = smp_processor_id() / threads_per_core;
1125         ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1126         mtspr(SPRN_LDBAR, ldbar_value);
1127 
1128         /*
1129          * imc pmus are enabled only when it is used.
1130          * See if this is triggered for the first time.
1131          * If yes, take the mutex lock and enable the counters.
1132          * If not, just increment the count in ref count struct.
1133          */
1134         ref = &core_imc_refc[core_id];
1135         if (!ref)
1136                 return -EINVAL;
1137 
1138         mutex_lock(&ref->lock);
1139         if (ref->refc == 0) {
1140                 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1141                     get_hard_smp_processor_id(smp_processor_id()))) {
1142                         mutex_unlock(&ref->lock);
1143                         pr_err("thread-imc: Unable to start the counter\
1144                                 for core %d\n", core_id);
1145                         return -EINVAL;
1146                 }
1147         }
1148         ++ref->refc;
1149         mutex_unlock(&ref->lock);
1150         return 0;
1151 }
1152 
1153 static void thread_imc_event_del(struct perf_event *event, int flags)
1154 {
1155 
1156         int core_id;
1157         struct imc_pmu_ref *ref;
1158 
1159         core_id = smp_processor_id() / threads_per_core;
1160         ref = &core_imc_refc[core_id];
1161         if (!ref) {
1162                 pr_debug("imc: Failed to get event reference count\n");
1163                 return;
1164         }
1165 
1166         mutex_lock(&ref->lock);
1167         ref->refc--;
1168         if (ref->refc == 0) {
1169                 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1170                     get_hard_smp_processor_id(smp_processor_id()))) {
1171                         mutex_unlock(&ref->lock);
1172                         pr_err("thread-imc: Unable to stop the counters\
1173                                 for core %d\n", core_id);
1174                         return;
1175                 }
1176         } else if (ref->refc < 0) {
1177                 ref->refc = 0;
1178         }
1179         mutex_unlock(&ref->lock);
1180 
1181         /* Set bit 0 of LDBAR to zero, to stop posting updates to memory */
1182         mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1183 
1184         /*
1185          * Take a snapshot and calculate the delta and update
1186          * the event counter values.
1187          */
1188         imc_event_update(event);
1189 }
1190 
1191 /*
1192  * Allocate a page of memory for each cpu, and load LDBAR with 0.
1193  */
1194 static int trace_imc_mem_alloc(int cpu_id, int size)
1195 {
1196         u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1197         int phys_id = cpu_to_node(cpu_id), rc = 0;
1198         int core_id = (cpu_id / threads_per_core);
1199 
1200         if (!local_mem) {
1201                 struct page *page;
1202 
1203                 page = alloc_pages_node(phys_id,
1204                                 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1205                                 __GFP_NOWARN, get_order(size));
1206                 if (!page)
1207                         return -ENOMEM;
1208                 local_mem = page_address(page);
1209                 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1210 
1211                 /* Initialise the counters for trace mode */
1212                 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1213                                             get_hard_smp_processor_id(cpu_id));
1214                 if (rc) {
1215                         pr_info("IMC:opal init failed for trace imc\n");
1216                         return rc;
1217                 }
1218         }
1219 
1220         /* Init the mutex, if not already */
1221         trace_imc_refc[core_id].id = core_id;
1222         mutex_init(&trace_imc_refc[core_id].lock);
1223 
1224         mtspr(SPRN_LDBAR, 0);
1225         return 0;
1226 }
1227 
1228 static int ppc_trace_imc_cpu_online(unsigned int cpu)
1229 {
1230         return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1231 }
1232 
1233 static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1234 {
1235         /*
1236          * No need to set bit 0 of LDBAR to zero, as
1237          * it is set to zero for imc trace-mode
1238          *
1239          * Reduce the refc if any trace-imc event running
1240          * on this cpu.
1241          */
1242         mutex_lock(&imc_global_refc.lock);
1243         if (imc_global_refc.id == IMC_DOMAIN_TRACE)
1244                 imc_global_refc.refc--;
1245         mutex_unlock(&imc_global_refc.lock);
1246 
1247         return 0;
1248 }
1249 
1250 static int trace_imc_cpu_init(void)
1251 {
1252         return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1253                           "perf/powerpc/imc_trace:online",
1254                           ppc_trace_imc_cpu_online,
1255                           ppc_trace_imc_cpu_offline);
1256 }
1257 
1258 static u64 get_trace_imc_event_base_addr(void)
1259 {
1260         return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1261 }
1262 
1263 /*
1264  * Function to parse trace-imc data obtained
1265  * and to prepare the perf sample.
1266  */
1267 static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1268                                     struct perf_sample_data *data,
1269                                     u64 *prev_tb,
1270                                     struct perf_event_header *header,
1271                                     struct perf_event *event)
1272 {
1273         /* Sanity checks for a valid record */
1274         if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1275                 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1276         else
1277                 return -EINVAL;
1278 
1279         if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1280                          be64_to_cpu(READ_ONCE(mem->tb2)))
1281                 return -EINVAL;
1282 
1283         /* Prepare perf sample */
1284         data->ip =  be64_to_cpu(READ_ONCE(mem->ip));
1285         data->period = event->hw.last_period;
1286 
1287         header->type = PERF_RECORD_SAMPLE;
1288         header->size = sizeof(*header) + event->header_size;
1289         header->misc = 0;
1290 
1291         if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1292                 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1293                 case 0:/* when MSR HV and PR not set in the trace-record */
1294                         header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1295                         break;
1296                 case 1: /* MSR HV is 0 and PR is 1 */
1297                         header->misc |= PERF_RECORD_MISC_GUEST_USER;
1298                         break;
1299                 case 2: /* MSR HV is 1 and PR is 0 */
1300                         header->misc |= PERF_RECORD_MISC_KERNEL;
1301                         break;
1302                 case 3: /* MSR HV is 1 and PR is 1 */
1303                         header->misc |= PERF_RECORD_MISC_USER;
1304                         break;
1305                 default:
1306                         pr_info("IMC: Unable to set the flag based on MSR bits\n");
1307                         break;
1308                 }
1309         } else {
1310                 if (is_kernel_addr(data->ip))
1311                         header->misc |= PERF_RECORD_MISC_KERNEL;
1312                 else
1313                         header->misc |= PERF_RECORD_MISC_USER;
1314         }
1315         perf_event_header__init_id(header, data, event);
1316 
1317         return 0;
1318 }
1319 
1320 static void dump_trace_imc_data(struct perf_event *event)
1321 {
1322         struct trace_imc_data *mem;
1323         int i, ret;
1324         u64 prev_tb = 0;
1325 
1326         mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1327         for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1328                 i++, mem++) {
1329                 struct perf_sample_data data;
1330                 struct perf_event_header header;
1331 
1332                 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1333                 if (ret) /* Exit, if not a valid record */
1334                         break;
1335                 else {
1336                         /* If this is a valid record, create the sample */
1337                         struct perf_output_handle handle;
1338 
1339                         if (perf_output_begin(&handle, &data, event, header.size))
1340                                 return;
1341 
1342                         perf_output_sample(&handle, &header, &data, event);
1343                         perf_output_end(&handle);
1344                 }
1345         }
1346 }
1347 
1348 static int trace_imc_event_add(struct perf_event *event, int flags)
1349 {
1350         int core_id = smp_processor_id() / threads_per_core;
1351         struct imc_pmu_ref *ref = NULL;
1352         u64 local_mem, ldbar_value;
1353 
1354         /* Set trace-imc bit in ldbar and load ldbar with per-thread memory address */
1355         local_mem = get_trace_imc_event_base_addr();
1356         ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1357 
1358         /* trace-imc reference count */
1359         if (trace_imc_refc)
1360                 ref = &trace_imc_refc[core_id];
1361         if (!ref) {
1362                 pr_debug("imc: Failed to get the event reference count\n");
1363                 return -EINVAL;
1364         }
1365 
1366         mtspr(SPRN_LDBAR, ldbar_value);
1367         mutex_lock(&ref->lock);
1368         if (ref->refc == 0) {
1369                 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1370                                 get_hard_smp_processor_id(smp_processor_id()))) {
1371                         mutex_unlock(&ref->lock);
1372                         pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1373                         return -EINVAL;
1374                 }
1375         }
1376         ++ref->refc;
1377         mutex_unlock(&ref->lock);
1378         return 0;
1379 }
1380 
1381 static void trace_imc_event_read(struct perf_event *event)
1382 {
1383         return;
1384 }
1385 
1386 static void trace_imc_event_stop(struct perf_event *event, int flags)
1387 {
1388         u64 local_mem = get_trace_imc_event_base_addr();
1389         dump_trace_imc_data(event);
1390         memset((void *)local_mem, 0, sizeof(u64));
1391 }
1392 
1393 static void trace_imc_event_start(struct perf_event *event, int flags)
1394 {
1395         return;
1396 }
1397 
1398 static void trace_imc_event_del(struct perf_event *event, int flags)
1399 {
1400         int core_id = smp_processor_id() / threads_per_core;
1401         struct imc_pmu_ref *ref = NULL;
1402 
1403         if (trace_imc_refc)
1404                 ref = &trace_imc_refc[core_id];
1405         if (!ref) {
1406                 pr_debug("imc: Failed to get event reference count\n");
1407                 return;
1408         }
1409 
1410         mutex_lock(&ref->lock);
1411         ref->refc--;
1412         if (ref->refc == 0) {
1413                 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1414                                 get_hard_smp_processor_id(smp_processor_id()))) {
1415                         mutex_unlock(&ref->lock);
1416                         pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1417                         return;
1418                 }
1419         } else if (ref->refc < 0) {
1420                 ref->refc = 0;
1421         }
1422         mutex_unlock(&ref->lock);
1423 
1424         trace_imc_event_stop(event, flags);
1425 }
1426 
1427 static int trace_imc_event_init(struct perf_event *event)
1428 {
1429         if (event->attr.type != event->pmu->type)
1430                 return -ENOENT;
1431 
1432         if (!perfmon_capable())
1433                 return -EACCES;
1434 
1435         /* Return if this is a couting event */
1436         if (event->attr.sample_period == 0)
1437                 return -ENOENT;
1438 
1439         /*
1440          * Take the global lock, and make sure
1441          * no other thread is running any core/thread imc
1442          * events
1443          */
1444         mutex_lock(&imc_global_refc.lock);
1445         if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_TRACE) {
1446                 /*
1447                  * No core/thread imc events are running in the
1448                  * system, so set the refc.id to trace-imc.
1449                  */
1450                 imc_global_refc.id = IMC_DOMAIN_TRACE;
1451                 imc_global_refc.refc++;
1452         } else {
1453                 mutex_unlock(&imc_global_refc.lock);
1454                 return -EBUSY;
1455         }
1456         mutex_unlock(&imc_global_refc.lock);
1457 
1458         event->hw.idx = -1;
1459 
1460         event->pmu->task_ctx_nr = perf_hw_context;
1461         event->destroy = reset_global_refc;
1462         return 0;
1463 }
1464 
1465 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1466 static int update_pmu_ops(struct imc_pmu *pmu)
1467 {
1468         pmu->pmu.task_ctx_nr = perf_invalid_context;
1469         pmu->pmu.add = imc_event_add;
1470         pmu->pmu.del = imc_event_stop;
1471         pmu->pmu.start = imc_event_start;
1472         pmu->pmu.stop = imc_event_stop;
1473         pmu->pmu.read = imc_event_update;
1474         pmu->pmu.attr_groups = pmu->attr_groups;
1475         pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1476         pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1477 
1478         switch (pmu->domain) {
1479         case IMC_DOMAIN_NEST:
1480                 pmu->pmu.event_init = nest_imc_event_init;
1481                 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1482                 break;
1483         case IMC_DOMAIN_CORE:
1484                 pmu->pmu.event_init = core_imc_event_init;
1485                 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1486                 break;
1487         case IMC_DOMAIN_THREAD:
1488                 pmu->pmu.event_init = thread_imc_event_init;
1489                 pmu->pmu.add = thread_imc_event_add;
1490                 pmu->pmu.del = thread_imc_event_del;
1491                 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1492                 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1493                 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1494                 break;
1495         case IMC_DOMAIN_TRACE:
1496                 pmu->pmu.event_init = trace_imc_event_init;
1497                 pmu->pmu.add = trace_imc_event_add;
1498                 pmu->pmu.del = trace_imc_event_del;
1499                 pmu->pmu.start = trace_imc_event_start;
1500                 pmu->pmu.stop = trace_imc_event_stop;
1501                 pmu->pmu.read = trace_imc_event_read;
1502                 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1503                 break;
1504         default:
1505                 break;
1506         }
1507 
1508         return 0;
1509 }
1510 
1511 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1512 static int init_nest_pmu_ref(void)
1513 {
1514         int nid, i, cpu;
1515 
1516         nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1517                                                                 GFP_KERNEL);
1518 
1519         if (!nest_imc_refc)
1520                 return -ENOMEM;
1521 
1522         i = 0;
1523         for_each_node(nid) {
1524                 /*
1525                  * Mutex lock to avoid races while tracking the number of
1526                  * sessions using the chip's nest pmu units.
1527                  */
1528                 mutex_init(&nest_imc_refc[i].lock);
1529 
1530                 /*
1531                  * Loop to init the "id" with the node_id. Variable "i" initialized to
1532                  * 0 and will be used as index to the array. "i" will not go off the
1533                  * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1534                  * nodes only.
1535                  */
1536                 nest_imc_refc[i++].id = nid;
1537         }
1538 
1539         /*
1540          * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1541          * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1542          */
1543         for_each_possible_cpu(cpu) {
1544                 nid = cpu_to_node(cpu);
1545                 for (i = 0; i < num_possible_nodes(); i++) {
1546                         if (nest_imc_refc[i].id == nid) {
1547                                 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1548                                 break;
1549                         }
1550                 }
1551         }
1552         return 0;
1553 }
1554 
1555 static void cleanup_all_core_imc_memory(void)
1556 {
1557         int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1558         struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1559         int size = core_imc_pmu->counter_mem_size;
1560 
1561         /* mem_info will never be NULL */
1562         for (i = 0; i < nr_cores; i++) {
1563                 if (ptr[i].vbase)
1564                         free_pages((u64)ptr[i].vbase, get_order(size));
1565         }
1566 
1567         kfree(ptr);
1568         kfree(core_imc_refc);
1569 }
1570 
1571 static void thread_imc_ldbar_disable(void *dummy)
1572 {
1573         /*
1574          * By setting 0th bit of LDBAR to zero, we disable thread-imc
1575          * updates to memory.
1576          */
1577         mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1578 }
1579 
1580 void thread_imc_disable(void)
1581 {
1582         on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1583 }
1584 
1585 static void cleanup_all_thread_imc_memory(void)
1586 {
1587         int i, order = get_order(thread_imc_mem_size);
1588 
1589         for_each_online_cpu(i) {
1590                 if (per_cpu(thread_imc_mem, i))
1591                         free_pages((u64)per_cpu(thread_imc_mem, i), order);
1592 
1593         }
1594 }
1595 
1596 static void cleanup_all_trace_imc_memory(void)
1597 {
1598         int i, order = get_order(trace_imc_mem_size);
1599 
1600         for_each_online_cpu(i) {
1601                 if (per_cpu(trace_imc_mem, i))
1602                         free_pages((u64)per_cpu(trace_imc_mem, i), order);
1603 
1604         }
1605         kfree(trace_imc_refc);
1606 }
1607 
1608 /* Function to free the attr_groups which are dynamically allocated */
1609 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1610 {
1611         if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1612                 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1613         kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1614 }
1615 
1616 /*
1617  * Common function to unregister cpu hotplug callback and
1618  * free the memory.
1619  * TODO: Need to handle pmu unregistering, which will be
1620  * done in followup series.
1621  */
1622 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1623 {
1624         if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1625                 mutex_lock(&nest_init_lock);
1626                 if (nest_pmus == 1) {
1627                         cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1628                         kfree(nest_imc_refc);
1629                         kfree(per_nest_pmu_arr);
1630                         per_nest_pmu_arr = NULL;
1631                 }
1632 
1633                 if (nest_pmus > 0)
1634                         nest_pmus--;
1635                 mutex_unlock(&nest_init_lock);
1636         }
1637 
1638         /* Free core_imc memory */
1639         if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1640                 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1641                 cleanup_all_core_imc_memory();
1642         }
1643 
1644         /* Free thread_imc memory */
1645         if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1646                 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1647                 cleanup_all_thread_imc_memory();
1648         }
1649 
1650         if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1651                 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1652                 cleanup_all_trace_imc_memory();
1653         }
1654 }
1655 
1656 /*
1657  * Function to unregister thread-imc if core-imc
1658  * is not registered.
1659  */
1660 void unregister_thread_imc(void)
1661 {
1662         imc_common_cpuhp_mem_free(thread_imc_pmu);
1663         imc_common_mem_free(thread_imc_pmu);
1664         perf_pmu_unregister(&thread_imc_pmu->pmu);
1665 }
1666 
1667 /*
1668  * imc_mem_init : Function to support memory allocation for core imc.
1669  */
1670 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1671                                                                 int pmu_index)
1672 {
1673         const char *s;
1674         int nr_cores, cpu, res = -ENOMEM;
1675 
1676         if (of_property_read_string(parent, "name", &s))
1677                 return -ENODEV;
1678 
1679         switch (pmu_ptr->domain) {
1680         case IMC_DOMAIN_NEST:
1681                 /* Update the pmu name */
1682                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1683                 if (!pmu_ptr->pmu.name)
1684                         goto err;
1685 
1686                 /* Needed for hotplug/migration */
1687                 if (!per_nest_pmu_arr) {
1688                         per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1689                                                 sizeof(struct imc_pmu *),
1690                                                 GFP_KERNEL);
1691                         if (!per_nest_pmu_arr)
1692                                 goto err;
1693                 }
1694                 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1695                 break;
1696         case IMC_DOMAIN_CORE:
1697                 /* Update the pmu name */
1698                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1699                 if (!pmu_ptr->pmu.name)
1700                         goto err;
1701 
1702                 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1703                 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1704                                                                 GFP_KERNEL);
1705 
1706                 if (!pmu_ptr->mem_info)
1707                         goto err;
1708 
1709                 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1710                                                                 GFP_KERNEL);
1711 
1712                 if (!core_imc_refc) {
1713                         kfree(pmu_ptr->mem_info);
1714                         goto err;
1715                 }
1716 
1717                 core_imc_pmu = pmu_ptr;
1718                 break;
1719         case IMC_DOMAIN_THREAD:
1720                 /* Update the pmu name */
1721                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1722                 if (!pmu_ptr->pmu.name)
1723                         goto err;
1724 
1725                 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1726                 for_each_online_cpu(cpu) {
1727                         res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1728                         if (res) {
1729                                 cleanup_all_thread_imc_memory();
1730                                 goto err;
1731                         }
1732                 }
1733 
1734                 thread_imc_pmu = pmu_ptr;
1735                 break;
1736         case IMC_DOMAIN_TRACE:
1737                 /* Update the pmu name */
1738                 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1739                 if (!pmu_ptr->pmu.name)
1740                         return -ENOMEM;
1741 
1742                 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1743                 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1744                                                                 GFP_KERNEL);
1745                 if (!trace_imc_refc)
1746                         return -ENOMEM;
1747 
1748                 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1749                 for_each_online_cpu(cpu) {
1750                         res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1751                         if (res) {
1752                                 cleanup_all_trace_imc_memory();
1753                                 goto err;
1754                         }
1755                 }
1756                 break;
1757         default:
1758                 return -EINVAL;
1759         }
1760 
1761         return 0;
1762 err:
1763         return res;
1764 }
1765 
1766 /*
1767  * init_imc_pmu : Setup and register the IMC pmu device.
1768  *
1769  * @parent:     Device tree unit node
1770  * @pmu_ptr:    memory allocated for this pmu
1771  * @pmu_idx:    Count of nest pmc registered
1772  *
1773  * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1774  * Handles failure cases and accordingly frees memory.
1775  */
1776 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1777 {
1778         int ret;
1779 
1780         ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1781         if (ret)
1782                 goto err_free_mem;
1783 
1784         switch (pmu_ptr->domain) {
1785         case IMC_DOMAIN_NEST:
1786                 /*
1787                 * Nest imc pmu need only one cpu per chip, we initialize the
1788                 * cpumask for the first nest imc pmu and use the same for the
1789                 * rest. To handle the cpuhotplug callback unregister, we track
1790                 * the number of nest pmus in "nest_pmus".
1791                 */
1792                 mutex_lock(&nest_init_lock);
1793                 if (nest_pmus == 0) {
1794                         ret = init_nest_pmu_ref();
1795                         if (ret) {
1796                                 mutex_unlock(&nest_init_lock);
1797                                 kfree(per_nest_pmu_arr);
1798                                 per_nest_pmu_arr = NULL;
1799                                 goto err_free_mem;
1800                         }
1801                         /* Register for cpu hotplug notification. */
1802                         ret = nest_pmu_cpumask_init();
1803                         if (ret) {
1804                                 mutex_unlock(&nest_init_lock);
1805                                 kfree(nest_imc_refc);
1806                                 kfree(per_nest_pmu_arr);
1807                                 per_nest_pmu_arr = NULL;
1808                                 goto err_free_mem;
1809                         }
1810                 }
1811                 nest_pmus++;
1812                 mutex_unlock(&nest_init_lock);
1813                 break;
1814         case IMC_DOMAIN_CORE:
1815                 ret = core_imc_pmu_cpumask_init();
1816                 if (ret) {
1817                         cleanup_all_core_imc_memory();
1818                         goto err_free_mem;
1819                 }
1820 
1821                 break;
1822         case IMC_DOMAIN_THREAD:
1823                 ret = thread_imc_cpu_init();
1824                 if (ret) {
1825                         cleanup_all_thread_imc_memory();
1826                         goto err_free_mem;
1827                 }
1828 
1829                 break;
1830         case IMC_DOMAIN_TRACE:
1831                 ret = trace_imc_cpu_init();
1832                 if (ret) {
1833                         cleanup_all_trace_imc_memory();
1834                         goto err_free_mem;
1835                 }
1836 
1837                 break;
1838         default:
1839                 return  -EINVAL;        /* Unknown domain */
1840         }
1841 
1842         ret = update_events_in_group(parent, pmu_ptr);
1843         if (ret)
1844                 goto err_free_cpuhp_mem;
1845 
1846         ret = update_pmu_ops(pmu_ptr);
1847         if (ret)
1848                 goto err_free_cpuhp_mem;
1849 
1850         ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1851         if (ret)
1852                 goto err_free_cpuhp_mem;
1853 
1854         pr_debug("%s performance monitor hardware support registered\n",
1855                                                         pmu_ptr->pmu.name);
1856 
1857         return 0;
1858 
1859 err_free_cpuhp_mem:
1860         imc_common_cpuhp_mem_free(pmu_ptr);
1861 err_free_mem:
1862         imc_common_mem_free(pmu_ptr);
1863         return ret;
1864 }
1865 

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