1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2016 Anju T, IBM Corporation.
4 */
5
6 #include <linux/errno.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/sched/task_stack.h>
10 #include <linux/perf_event.h>
11 #include <linux/bug.h>
12 #include <linux/stddef.h>
13 #include <asm/ptrace.h>
14 #include <asm/perf_regs.h>
15
16 #define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
17
18 #define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
19
20 static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
21 PT_REGS_OFFSET(PERF_REG_POWERPC_R0, gpr[0]),
22 PT_REGS_OFFSET(PERF_REG_POWERPC_R1, gpr[1]),
23 PT_REGS_OFFSET(PERF_REG_POWERPC_R2, gpr[2]),
24 PT_REGS_OFFSET(PERF_REG_POWERPC_R3, gpr[3]),
25 PT_REGS_OFFSET(PERF_REG_POWERPC_R4, gpr[4]),
26 PT_REGS_OFFSET(PERF_REG_POWERPC_R5, gpr[5]),
27 PT_REGS_OFFSET(PERF_REG_POWERPC_R6, gpr[6]),
28 PT_REGS_OFFSET(PERF_REG_POWERPC_R7, gpr[7]),
29 PT_REGS_OFFSET(PERF_REG_POWERPC_R8, gpr[8]),
30 PT_REGS_OFFSET(PERF_REG_POWERPC_R9, gpr[9]),
31 PT_REGS_OFFSET(PERF_REG_POWERPC_R10, gpr[10]),
32 PT_REGS_OFFSET(PERF_REG_POWERPC_R11, gpr[11]),
33 PT_REGS_OFFSET(PERF_REG_POWERPC_R12, gpr[12]),
34 PT_REGS_OFFSET(PERF_REG_POWERPC_R13, gpr[13]),
35 PT_REGS_OFFSET(PERF_REG_POWERPC_R14, gpr[14]),
36 PT_REGS_OFFSET(PERF_REG_POWERPC_R15, gpr[15]),
37 PT_REGS_OFFSET(PERF_REG_POWERPC_R16, gpr[16]),
38 PT_REGS_OFFSET(PERF_REG_POWERPC_R17, gpr[17]),
39 PT_REGS_OFFSET(PERF_REG_POWERPC_R18, gpr[18]),
40 PT_REGS_OFFSET(PERF_REG_POWERPC_R19, gpr[19]),
41 PT_REGS_OFFSET(PERF_REG_POWERPC_R20, gpr[20]),
42 PT_REGS_OFFSET(PERF_REG_POWERPC_R21, gpr[21]),
43 PT_REGS_OFFSET(PERF_REG_POWERPC_R22, gpr[22]),
44 PT_REGS_OFFSET(PERF_REG_POWERPC_R23, gpr[23]),
45 PT_REGS_OFFSET(PERF_REG_POWERPC_R24, gpr[24]),
46 PT_REGS_OFFSET(PERF_REG_POWERPC_R25, gpr[25]),
47 PT_REGS_OFFSET(PERF_REG_POWERPC_R26, gpr[26]),
48 PT_REGS_OFFSET(PERF_REG_POWERPC_R27, gpr[27]),
49 PT_REGS_OFFSET(PERF_REG_POWERPC_R28, gpr[28]),
50 PT_REGS_OFFSET(PERF_REG_POWERPC_R29, gpr[29]),
51 PT_REGS_OFFSET(PERF_REG_POWERPC_R30, gpr[30]),
52 PT_REGS_OFFSET(PERF_REG_POWERPC_R31, gpr[31]),
53 PT_REGS_OFFSET(PERF_REG_POWERPC_NIP, nip),
54 PT_REGS_OFFSET(PERF_REG_POWERPC_MSR, msr),
55 PT_REGS_OFFSET(PERF_REG_POWERPC_ORIG_R3, orig_gpr3),
56 PT_REGS_OFFSET(PERF_REG_POWERPC_CTR, ctr),
57 PT_REGS_OFFSET(PERF_REG_POWERPC_LINK, link),
58 PT_REGS_OFFSET(PERF_REG_POWERPC_XER, xer),
59 PT_REGS_OFFSET(PERF_REG_POWERPC_CCR, ccr),
60 #ifdef CONFIG_PPC64
61 PT_REGS_OFFSET(PERF_REG_POWERPC_SOFTE, softe),
62 #else
63 PT_REGS_OFFSET(PERF_REG_POWERPC_SOFTE, mq),
64 #endif
65 PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap),
66 PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar),
67 PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr),
68 PT_REGS_OFFSET(PERF_REG_POWERPC_SIER, dar),
69 PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr),
70 };
71
72 u64 perf_reg_value(struct pt_regs *regs, int idx)
73 {
74 if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX))
75 return 0;
76
77 if (idx == PERF_REG_POWERPC_SIER &&
78 (IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
79 IS_ENABLED(CONFIG_PPC32) ||
80 !is_sier_available()))
81 return 0;
82
83 if (idx == PERF_REG_POWERPC_MMCRA &&
84 (IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
85 IS_ENABLED(CONFIG_PPC32)))
86 return 0;
87
88 return regs_get_register(regs, pt_regs_offset[idx]);
89 }
90
91 int perf_reg_validate(u64 mask)
92 {
93 if (!mask || mask & REG_RESERVED)
94 return -EINVAL;
95 return 0;
96 }
97
98 u64 perf_reg_abi(struct task_struct *task)
99 {
100 #ifdef CONFIG_PPC64
101 if (!test_tsk_thread_flag(task, TIF_32BIT))
102 return PERF_SAMPLE_REGS_ABI_64;
103 else
104 #endif
105 return PERF_SAMPLE_REGS_ABI_32;
106 }
107
108 void perf_get_regs_user(struct perf_regs *regs_user,
109 struct pt_regs *regs,
110 struct pt_regs *regs_user_copy)
111 {
112 regs_user->regs = task_pt_regs(current);
113 regs_user->abi = (regs_user->regs) ? perf_reg_abi(current) :
114 PERF_SAMPLE_REGS_ABI_NONE;
115 }
116
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