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Linux/arch/powerpc/platforms/4xx/gpio.c

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  1 /*
  2  * PPC4xx gpio driver
  3  *
  4  * Copyright (c) 2008 Harris Corporation
  5  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  6  * Copyright (c) MontaVista Software, Inc. 2008.
  7  *
  8  * Author: Steve Falco <sfalco@harris.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2
 12  * as published by the Free Software Foundation.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  * You should have received a copy of the GNU General Public License
 20  * along with this program; if not, write to the Free Software
 21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 22  */
 23 
 24 #include <linux/kernel.h>
 25 #include <linux/init.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/io.h>
 28 #include <linux/of.h>
 29 #include <linux/of_gpio.h>
 30 #include <linux/gpio/driver.h>
 31 #include <linux/types.h>
 32 #include <linux/slab.h>
 33 
 34 #define GPIO_MASK(gpio)         (0x80000000 >> (gpio))
 35 #define GPIO_MASK2(gpio)        (0xc0000000 >> ((gpio) * 2))
 36 
 37 /* Physical GPIO register layout */
 38 struct ppc4xx_gpio {
 39         __be32 or;
 40         __be32 tcr;
 41         __be32 osrl;
 42         __be32 osrh;
 43         __be32 tsrl;
 44         __be32 tsrh;
 45         __be32 odr;
 46         __be32 ir;
 47         __be32 rr1;
 48         __be32 rr2;
 49         __be32 rr3;
 50         __be32 reserved1;
 51         __be32 isr1l;
 52         __be32 isr1h;
 53         __be32 isr2l;
 54         __be32 isr2h;
 55         __be32 isr3l;
 56         __be32 isr3h;
 57 };
 58 
 59 struct ppc4xx_gpio_chip {
 60         struct of_mm_gpio_chip mm_gc;
 61         spinlock_t lock;
 62 };
 63 
 64 /*
 65  * GPIO LIB API implementation for GPIOs
 66  *
 67  * There are a maximum of 32 gpios in each gpio controller.
 68  */
 69 
 70 static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 71 {
 72         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 73         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 74 
 75         return !!(in_be32(&regs->ir) & GPIO_MASK(gpio));
 76 }
 77 
 78 static inline void
 79 __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 80 {
 81         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 82         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 83 
 84         if (val)
 85                 setbits32(&regs->or, GPIO_MASK(gpio));
 86         else
 87                 clrbits32(&regs->or, GPIO_MASK(gpio));
 88 }
 89 
 90 static void
 91 ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 92 {
 93         struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
 94         unsigned long flags;
 95 
 96         spin_lock_irqsave(&chip->lock, flags);
 97 
 98         __ppc4xx_gpio_set(gc, gpio, val);
 99 
100         spin_unlock_irqrestore(&chip->lock, flags);
101 
102         pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
103 }
104 
105 static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
106 {
107         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
108         struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
109         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
110         unsigned long flags;
111 
112         spin_lock_irqsave(&chip->lock, flags);
113 
114         /* Disable open-drain function */
115         clrbits32(&regs->odr, GPIO_MASK(gpio));
116 
117         /* Float the pin */
118         clrbits32(&regs->tcr, GPIO_MASK(gpio));
119 
120         /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
121         if (gpio < 16) {
122                 clrbits32(&regs->osrl, GPIO_MASK2(gpio));
123                 clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
124         } else {
125                 clrbits32(&regs->osrh, GPIO_MASK2(gpio));
126                 clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
127         }
128 
129         spin_unlock_irqrestore(&chip->lock, flags);
130 
131         return 0;
132 }
133 
134 static int
135 ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
136 {
137         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
138         struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
139         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
140         unsigned long flags;
141 
142         spin_lock_irqsave(&chip->lock, flags);
143 
144         /* First set initial value */
145         __ppc4xx_gpio_set(gc, gpio, val);
146 
147         /* Disable open-drain function */
148         clrbits32(&regs->odr, GPIO_MASK(gpio));
149 
150         /* Drive the pin */
151         setbits32(&regs->tcr, GPIO_MASK(gpio));
152 
153         /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
154         if (gpio < 16) {
155                 clrbits32(&regs->osrl, GPIO_MASK2(gpio));
156                 clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
157         } else {
158                 clrbits32(&regs->osrh, GPIO_MASK2(gpio));
159                 clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
160         }
161 
162         spin_unlock_irqrestore(&chip->lock, flags);
163 
164         pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
165 
166         return 0;
167 }
168 
169 static int __init ppc4xx_add_gpiochips(void)
170 {
171         struct device_node *np;
172 
173         for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
174                 int ret;
175                 struct ppc4xx_gpio_chip *ppc4xx_gc;
176                 struct of_mm_gpio_chip *mm_gc;
177                 struct gpio_chip *gc;
178 
179                 ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
180                 if (!ppc4xx_gc) {
181                         ret = -ENOMEM;
182                         goto err;
183                 }
184 
185                 spin_lock_init(&ppc4xx_gc->lock);
186 
187                 mm_gc = &ppc4xx_gc->mm_gc;
188                 gc = &mm_gc->gc;
189 
190                 gc->ngpio = 32;
191                 gc->direction_input = ppc4xx_gpio_dir_in;
192                 gc->direction_output = ppc4xx_gpio_dir_out;
193                 gc->get = ppc4xx_gpio_get;
194                 gc->set = ppc4xx_gpio_set;
195 
196                 ret = of_mm_gpiochip_add_data(np, mm_gc, ppc4xx_gc);
197                 if (ret)
198                         goto err;
199                 continue;
200 err:
201                 pr_err("%pOF: registration failed with status %d\n", np, ret);
202                 kfree(ppc4xx_gc);
203                 /* try others anyway */
204         }
205         return 0;
206 }
207 arch_initcall(ppc4xx_add_gpiochips);
208 

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