1 /*
2 * MPC85xx RDB Board Setup
3 *
4 * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 #include <linux/stddef.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/kdev_t.h>
16 #include <linux/delay.h>
17 #include <linux/seq_file.h>
18 #include <linux/interrupt.h>
19 #include <linux/of_platform.h>
20 #include <linux/fsl/guts.h>
21
22 #include <asm/time.h>
23 #include <asm/machdep.h>
24 #include <asm/pci-bridge.h>
25 #include <mm/mmu_decl.h>
26 #include <asm/prom.h>
27 #include <asm/udbg.h>
28 #include <asm/mpic.h>
29 #include <soc/fsl/qe/qe.h>
30 #include <soc/fsl/qe/qe_ic.h>
31
32 #include <sysdev/fsl_soc.h>
33 #include <sysdev/fsl_pci.h>
34 #include "smp.h"
35
36 #include "mpc85xx.h"
37
38 #undef DEBUG
39
40 #ifdef DEBUG
41 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
42 #else
43 #define DBG(fmt, args...)
44 #endif
45
46
47 void __init mpc85xx_rdb_pic_init(void)
48 {
49 struct mpic *mpic;
50
51 #ifdef CONFIG_QUICC_ENGINE
52 struct device_node *np;
53 #endif
54
55 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
56 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
57 MPIC_BIG_ENDIAN |
58 MPIC_SINGLE_DEST_CPU,
59 0, 256, " OpenPIC ");
60 } else {
61 mpic = mpic_alloc(NULL, 0,
62 MPIC_BIG_ENDIAN |
63 MPIC_SINGLE_DEST_CPU,
64 0, 256, " OpenPIC ");
65 }
66
67 BUG_ON(mpic == NULL);
68 mpic_init(mpic);
69
70 #ifdef CONFIG_QUICC_ENGINE
71 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
72 if (np) {
73 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
74 qe_ic_cascade_high_mpic);
75 of_node_put(np);
76
77 } else
78 pr_err("%s: Could not find qe-ic node\n", __func__);
79 #endif
80
81 }
82
83 /*
84 * Setup the architecture
85 */
86 static void __init mpc85xx_rdb_setup_arch(void)
87 {
88 if (ppc_md.progress)
89 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
90
91 mpc85xx_smp_init();
92
93 fsl_pci_assign_primary();
94
95 #ifdef CONFIG_QUICC_ENGINE
96 mpc85xx_qe_init();
97 mpc85xx_qe_par_io_init();
98 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
99 if (machine_is(p1025_rdb)) {
100 struct device_node *np;
101
102 struct ccsr_guts __iomem *guts;
103
104 np = of_find_node_by_name(NULL, "global-utilities");
105 if (np) {
106 guts = of_iomap(np, 0);
107 if (!guts) {
108
109 pr_err("mpc85xx-rdb: could not map global utilities register\n");
110
111 } else {
112 /* P1025 has pins muxed for QE and other functions. To
113 * enable QE UEC mode, we need to set bit QE0 for UCC1
114 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
115 * and QE12 for QE MII management singals in PMUXCR
116 * register.
117 */
118 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
119 MPC85xx_PMUXCR_QE(3) |
120 MPC85xx_PMUXCR_QE(9) |
121 MPC85xx_PMUXCR_QE(12));
122 iounmap(guts);
123 }
124 of_node_put(np);
125 }
126
127 }
128 #endif
129 #endif /* CONFIG_QUICC_ENGINE */
130
131 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
132 }
133
134 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
135 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
136 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
137 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
138 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
139 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices);
140 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
141 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
142 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
143 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
144
145 /*
146 * Called very early, device-tree isn't unflattened
147 */
148 static int __init p2020_rdb_probe(void)
149 {
150 if (of_machine_is_compatible("fsl,P2020RDB"))
151 return 1;
152 return 0;
153 }
154
155 static int __init p1020_rdb_probe(void)
156 {
157 if (of_machine_is_compatible("fsl,P1020RDB"))
158 return 1;
159 return 0;
160 }
161
162 static int __init p1020_rdb_pc_probe(void)
163 {
164 return of_machine_is_compatible("fsl,P1020RDB-PC");
165 }
166
167 static int __init p1020_rdb_pd_probe(void)
168 {
169 return of_machine_is_compatible("fsl,P1020RDB-PD");
170 }
171
172 static int __init p1021_rdb_pc_probe(void)
173 {
174 if (of_machine_is_compatible("fsl,P1021RDB-PC"))
175 return 1;
176 return 0;
177 }
178
179 static int __init p2020_rdb_pc_probe(void)
180 {
181 if (of_machine_is_compatible("fsl,P2020RDB-PC"))
182 return 1;
183 return 0;
184 }
185
186 static int __init p1025_rdb_probe(void)
187 {
188 return of_machine_is_compatible("fsl,P1025RDB");
189 }
190
191 static int __init p1020_mbg_pc_probe(void)
192 {
193 return of_machine_is_compatible("fsl,P1020MBG-PC");
194 }
195
196 static int __init p1020_utm_pc_probe(void)
197 {
198 return of_machine_is_compatible("fsl,P1020UTM-PC");
199 }
200
201 static int __init p1024_rdb_probe(void)
202 {
203 return of_machine_is_compatible("fsl,P1024RDB");
204 }
205
206 define_machine(p2020_rdb) {
207 .name = "P2020 RDB",
208 .probe = p2020_rdb_probe,
209 .setup_arch = mpc85xx_rdb_setup_arch,
210 .init_IRQ = mpc85xx_rdb_pic_init,
211 #ifdef CONFIG_PCI
212 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
213 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
214 #endif
215 .get_irq = mpic_get_irq,
216 .calibrate_decr = generic_calibrate_decr,
217 .progress = udbg_progress,
218 };
219
220 define_machine(p1020_rdb) {
221 .name = "P1020 RDB",
222 .probe = p1020_rdb_probe,
223 .setup_arch = mpc85xx_rdb_setup_arch,
224 .init_IRQ = mpc85xx_rdb_pic_init,
225 #ifdef CONFIG_PCI
226 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
227 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
228 #endif
229 .get_irq = mpic_get_irq,
230 .calibrate_decr = generic_calibrate_decr,
231 .progress = udbg_progress,
232 };
233
234 define_machine(p1021_rdb_pc) {
235 .name = "P1021 RDB-PC",
236 .probe = p1021_rdb_pc_probe,
237 .setup_arch = mpc85xx_rdb_setup_arch,
238 .init_IRQ = mpc85xx_rdb_pic_init,
239 #ifdef CONFIG_PCI
240 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
241 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
242 #endif
243 .get_irq = mpic_get_irq,
244 .calibrate_decr = generic_calibrate_decr,
245 .progress = udbg_progress,
246 };
247
248 define_machine(p2020_rdb_pc) {
249 .name = "P2020RDB-PC",
250 .probe = p2020_rdb_pc_probe,
251 .setup_arch = mpc85xx_rdb_setup_arch,
252 .init_IRQ = mpc85xx_rdb_pic_init,
253 #ifdef CONFIG_PCI
254 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
255 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
256 #endif
257 .get_irq = mpic_get_irq,
258 .calibrate_decr = generic_calibrate_decr,
259 .progress = udbg_progress,
260 };
261
262 define_machine(p1025_rdb) {
263 .name = "P1025 RDB",
264 .probe = p1025_rdb_probe,
265 .setup_arch = mpc85xx_rdb_setup_arch,
266 .init_IRQ = mpc85xx_rdb_pic_init,
267 #ifdef CONFIG_PCI
268 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
269 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
270 #endif
271 .get_irq = mpic_get_irq,
272 .calibrate_decr = generic_calibrate_decr,
273 .progress = udbg_progress,
274 };
275
276 define_machine(p1020_mbg_pc) {
277 .name = "P1020 MBG-PC",
278 .probe = p1020_mbg_pc_probe,
279 .setup_arch = mpc85xx_rdb_setup_arch,
280 .init_IRQ = mpc85xx_rdb_pic_init,
281 #ifdef CONFIG_PCI
282 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
283 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
284 #endif
285 .get_irq = mpic_get_irq,
286 .calibrate_decr = generic_calibrate_decr,
287 .progress = udbg_progress,
288 };
289
290 define_machine(p1020_utm_pc) {
291 .name = "P1020 UTM-PC",
292 .probe = p1020_utm_pc_probe,
293 .setup_arch = mpc85xx_rdb_setup_arch,
294 .init_IRQ = mpc85xx_rdb_pic_init,
295 #ifdef CONFIG_PCI
296 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
297 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
298 #endif
299 .get_irq = mpic_get_irq,
300 .calibrate_decr = generic_calibrate_decr,
301 .progress = udbg_progress,
302 };
303
304 define_machine(p1020_rdb_pc) {
305 .name = "P1020RDB-PC",
306 .probe = p1020_rdb_pc_probe,
307 .setup_arch = mpc85xx_rdb_setup_arch,
308 .init_IRQ = mpc85xx_rdb_pic_init,
309 #ifdef CONFIG_PCI
310 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
311 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
312 #endif
313 .get_irq = mpic_get_irq,
314 .calibrate_decr = generic_calibrate_decr,
315 .progress = udbg_progress,
316 };
317
318 define_machine(p1020_rdb_pd) {
319 .name = "P1020RDB-PD",
320 .probe = p1020_rdb_pd_probe,
321 .setup_arch = mpc85xx_rdb_setup_arch,
322 .init_IRQ = mpc85xx_rdb_pic_init,
323 #ifdef CONFIG_PCI
324 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
325 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
326 #endif
327 .get_irq = mpic_get_irq,
328 .calibrate_decr = generic_calibrate_decr,
329 .progress = udbg_progress,
330 };
331
332 define_machine(p1024_rdb) {
333 .name = "P1024 RDB",
334 .probe = p1024_rdb_probe,
335 .setup_arch = mpc85xx_rdb_setup_arch,
336 .init_IRQ = mpc85xx_rdb_pic_init,
337 #ifdef CONFIG_PCI
338 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
339 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
340 #endif
341 .get_irq = mpic_get_irq,
342 .calibrate_decr = generic_calibrate_decr,
343 .progress = udbg_progress,
344 };
345
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