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TOMOYO Linux Cross Reference
Linux/arch/powerpc/platforms/iseries/lpardata.c

Version: ~ [ linux-5.2-rc1 ] ~ [ linux-5.1.2 ] ~ [ linux-5.0.16 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.43 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.119 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.176 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.179 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.139 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.67 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.39.4 ] ~ [ linux-2.6.38.8 ] ~ [ linux-2.6.37.6 ] ~ [ linux-2.6.36.4 ] ~ [ linux-2.6.35.14 ] ~ [ linux-2.6.34.15 ] ~ [ linux-2.6.33.20 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright 2001 Mike Corrigan, IBM Corp
  3  *
  4  * This program is free software; you can redistribute it and/or
  5  * modify it under the terms of the GNU General Public License
  6  * as published by the Free Software Foundation; either version
  7  * 2 of the License, or (at your option) any later version.
  8  */
  9 #include <linux/types.h>
 10 #include <linux/threads.h>
 11 #include <linux/module.h>
 12 #include <linux/bitops.h>
 13 #include <asm/processor.h>
 14 #include <asm/ptrace.h>
 15 #include <asm/abs_addr.h>
 16 #include <asm/lppaca.h>
 17 #include <asm/paca.h>
 18 #include <asm/iseries/lpar_map.h>
 19 #include <asm/iseries/it_lp_queue.h>
 20 #include <asm/iseries/alpaca.h>
 21 
 22 #include "naca.h"
 23 #include "vpd_areas.h"
 24 #include "spcomm_area.h"
 25 #include "ipl_parms.h"
 26 #include "processor_vpd.h"
 27 #include "release_data.h"
 28 #include "it_exp_vpd_panel.h"
 29 #include "it_lp_naca.h"
 30 
 31 /* The HvReleaseData is the root of the information shared between
 32  * the hypervisor and Linux.
 33  */
 34 const struct HvReleaseData hvReleaseData = {
 35         .xDesc = 0xc8a5d9c4,    /* "HvRD" ebcdic */
 36         .xSize = sizeof(struct HvReleaseData),
 37         .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
 38         .xSlicNacaAddr = &naca,         /* 64-bit Naca address */
 39         .xMsNucDataOffset = LPARMAP_PHYS,
 40         .xFlags = HVREL_TAGSINACTIVE    /* tags inactive       */
 41                                         /* 64 bit              */
 42                                         /* shared processors   */
 43                                         /* HMT allowed         */
 44                   | 6,                  /* TEMP: This allows non-GA driver */
 45         .xVrmIndex = 4,                 /* We are v5r2m0               */
 46         .xMinSupportedPlicVrmIndex = 3,         /* v5r1m0 */
 47         .xMinCompatablePlicVrmIndex = 3,        /* v5r1m0 */
 48         .xVrmName = { 0xd3, 0x89, 0x95, 0xa4,   /* "Linux 2.4.64" ebcdic */
 49                 0xa7, 0x40, 0xf2, 0x4b,
 50                 0xf4, 0x4b, 0xf6, 0xf4 },
 51 };
 52 
 53 /*
 54  * The NACA.  The first dword of the naca is required by the iSeries
 55  * hypervisor to point to itVpdAreas.  The hypervisor finds the NACA
 56  * through the pointer in hvReleaseData.
 57  */
 58 struct naca_struct naca = {
 59         .xItVpdAreas = &itVpdAreas,
 60         .xRamDisk = 0,
 61         .xRamDiskSize = 0,
 62 };
 63 
 64 struct ItLpRegSave {
 65         u32     xDesc;          // Eye catcher  "LpRS" ebcdic   000-003
 66         u16     xSize;          // Size of this class           004-005
 67         u8      xInUse;         // Area is live                 006-007
 68         u8      xRsvd1[9];      // Reserved                     007-00F
 69 
 70         u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F
 71         u32     xCTRL;          // Control Register             170-173
 72         u32     xDEC;           // Decrementer                  174-177
 73         u32     xFPSCR;         // FP Status and Control Reg    178-17B
 74         u32     xPVR;           // Processor Version Number     17C-17F
 75 
 76         u64     xMMCR0;         // Monitor Mode Control Reg 0   180-187
 77         u32     xPMC1;          // Perf Monitor Counter 1       188-18B
 78         u32     xPMC2;          // Perf Monitor Counter 2       18C-18F
 79         u32     xPMC3;          // Perf Monitor Counter 3       190-193
 80         u32     xPMC4;          // Perf Monitor Counter 4       194-197
 81         u32     xPIR;           // Processor ID Reg             198-19B
 82 
 83         u32     xMMCR1;         // Monitor Mode Control Reg 1   19C-19F
 84         u32     xMMCRA;         // Monitor Mode Control Reg A   1A0-1A3
 85         u32     xPMC5;          // Perf Monitor Counter 5       1A4-1A7
 86         u32     xPMC6;          // Perf Monitor Counter 6       1A8-1AB
 87         u32     xPMC7;          // Perf Monitor Counter 7       1AC-1AF
 88         u32     xPMC8;          // Perf Monitor Counter 8       1B0-1B3
 89         u32     xTSC;           // Thread Switch Control        1B4-1B7
 90         u32     xTST;           // Thread Switch Timeout        1B8-1BB
 91         u32     xRsvd;          // Reserved                     1BC-1BF
 92 
 93         u64     xACCR;          // Address Compare Control Reg  1C0-1C7
 94         u64     xIMR;           // Instruction Match Register   1C8-1CF
 95         u64     xSDR1;          // Storage Description Reg 1    1D0-1D7
 96         u64     xSPRG0;         // Special Purpose Reg General0 1D8-1DF
 97         u64     xSPRG1;         // Special Purpose Reg General1 1E0-1E7
 98         u64     xSPRG2;         // Special Purpose Reg General2 1E8-1EF
 99         u64     xSPRG3;         // Special Purpose Reg General3 1F0-1F7
100         u64     xTB;            // Time Base Register           1F8-1FF
101 
102         u64     xFPR[32];       // Floating Point Registers     200-2FF
103 
104         u64     xMSR;           // Machine State Register       300-307
105         u64     xNIA;           // Next Instruction Address     308-30F
106 
107         u64     xDABR;          // Data Address Breakpoint Reg  310-317
108         u64     xIABR;          // Inst Address Breakpoint Reg  318-31F
109 
110         u64     xHID0;          // HW Implementation Dependent0 320-327
111 
112         u64     xHID4;          // HW Implementation Dependent4 328-32F
113         u64     xSCOMd;         // SCON Data Reg (SPRG4)        330-337
114         u64     xSCOMc;         // SCON Command Reg (SPRG5)     338-33F
115         u64     xSDAR;          // Sample Data Address Register 340-347
116         u64     xSIAR;          // Sample Inst Address Register 348-34F
117 
118         u8      xRsvd3[176];    // Reserved                     350-3FF
119 };
120 
121 extern void system_reset_iSeries(void);
122 extern void machine_check_iSeries(void);
123 extern void data_access_iSeries(void);
124 extern void instruction_access_iSeries(void);
125 extern void hardware_interrupt_iSeries(void);
126 extern void alignment_iSeries(void);
127 extern void program_check_iSeries(void);
128 extern void fp_unavailable_iSeries(void);
129 extern void decrementer_iSeries(void);
130 extern void trap_0a_iSeries(void);
131 extern void trap_0b_iSeries(void);
132 extern void system_call_iSeries(void);
133 extern void single_step_iSeries(void);
134 extern void trap_0e_iSeries(void);
135 extern void performance_monitor_iSeries(void);
136 extern void data_access_slb_iSeries(void);
137 extern void instruction_access_slb_iSeries(void);
138 
139 struct ItLpNaca itLpNaca = {
140         .xDesc = 0xd397d581,            /* "LpNa" ebcdic */
141         .xSize = 0x0400,                /* size of ItLpNaca */
142         .xIntHdlrOffset = 0x0300,       /* offset to int array */
143         .xMaxIntHdlrEntries = 19,       /* # ents */
144         .xPrimaryLpIndex = 0,           /* Part # of primary */
145         .xServiceLpIndex = 0,           /* Part # of serv */
146         .xLpIndex = 0,                  /* Part # of me */
147         .xMaxLpQueues = 0,              /* # of LP queues */
148         .xLpQueueOffset = 0x100,        /* offset of start of LP queues */
149         .xPirEnvironMode = 0,           /* Piranha stuff */
150         .xPirConsoleMode = 0,
151         .xPirDasdMode = 0,
152         .flags = 0,
153         .xSpVpdFormat = 0,
154         .xIntProcRatio = 0,
155         .xPlicVrmIndex = 0,             /* VRM index of PLIC */
156         .xMinSupportedSlicVrmInd = 0,   /* min supported SLIC */
157         .xMinCompatableSlicVrmInd = 0,  /* min compat SLIC */
158         .xLoadAreaAddr = 0,             /* 64-bit addr of load area */
159         .xLoadAreaChunks = 0,           /* chunks for load area */
160         .xPaseSysCallCRMask = 0,        /* PASE mask */
161         .xSlicSegmentTablePtr = 0,      /* seg table */
162         .xOldLpQueue = { 0 },           /* Old LP Queue */
163         .xInterruptHdlr = {
164                 (u64)system_reset_iSeries,      /* 0x100 System Reset */
165                 (u64)machine_check_iSeries,     /* 0x200 Machine Check */
166                 (u64)data_access_iSeries,       /* 0x300 Data Access */
167                 (u64)instruction_access_iSeries, /* 0x400 Instruction Access */
168                 (u64)hardware_interrupt_iSeries, /* 0x500 External */
169                 (u64)alignment_iSeries,         /* 0x600 Alignment */
170                 (u64)program_check_iSeries,     /* 0x700 Program Check */
171                 (u64)fp_unavailable_iSeries,    /* 0x800 FP Unavailable */
172                 (u64)decrementer_iSeries,       /* 0x900 Decrementer */
173                 (u64)trap_0a_iSeries,           /* 0xa00 Trap 0A */
174                 (u64)trap_0b_iSeries,           /* 0xb00 Trap 0B */
175                 (u64)system_call_iSeries,       /* 0xc00 System Call */
176                 (u64)single_step_iSeries,       /* 0xd00 Single Step */
177                 (u64)trap_0e_iSeries,           /* 0xe00 Trap 0E */
178                 (u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */
179                 0,                              /* int 0x1000 */
180                 0,                              /* int 0x1010 */
181                 0,                              /* int 0x1020 CPU ctls */
182                 (u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */
183                 (u64)data_access_slb_iSeries,   /* 0x380 D-SLB */
184                 (u64)instruction_access_slb_iSeries /* 0x480 I-SLB */
185         }
186 };
187 
188 /* May be filled in by the hypervisor so cannot end up in the BSS */
189 static struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
190 
191 /* May be filled in by the hypervisor so cannot end up in the BSS */
192 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
193 
194 #define maxPhysicalProcessors 32
195 
196 struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
197         {
198                 .xInstCacheOperandSize = 32,
199                 .xDataCacheOperandSize = 32,
200                 .xProcFreq     = 50000000,
201                 .xTimeBaseFreq = 50000000,
202                 .xPVR = 0x3600
203         }
204 };
205 
206 /* Space for Main Store Vpd 27,200 bytes */
207 /* May be filled in by the hypervisor so cannot end up in the BSS */
208 u64    xMsVpd[3400] __attribute__((__section__(".data")));
209 
210 /* Space for Recovery Log Buffer */
211 /* May be filled in by the hypervisor so cannot end up in the BSS */
212 static u64    xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
213 
214 static const struct SpCommArea xSpCommArea = {
215         .xDesc = 0xE2D7C3C2,
216         .xFormat = 1,
217 };
218 
219 static const struct ItLpRegSave iseries_reg_save[] = {
220         [0 ... (NR_CPUS-1)] = {
221                 .xDesc = 0xd397d9e2,    /* "LpRS" */
222                 .xSize = sizeof(struct ItLpRegSave),
223         },
224 };
225 
226 #define ALPACA_INIT(number)                                             \
227 {                                                                       \
228         .lppaca_ptr = &lppaca[number],                                  \
229         .reg_save_ptr = &iseries_reg_save[number],                      \
230 }
231 
232 const struct alpaca alpaca[] = {
233         ALPACA_INIT( 0),
234 #if NR_CPUS > 1
235         ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3),
236 #if NR_CPUS > 4
237         ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7),
238 #if NR_CPUS > 8
239         ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11),
240         ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15),
241         ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19),
242         ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23),
243         ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27),
244         ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31),
245 #if NR_CPUS > 32
246         ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35),
247         ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39),
248         ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43),
249         ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47),
250         ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51),
251         ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55),
252         ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59),
253         ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63),
254 #endif
255 #endif
256 #endif
257 #endif
258 };
259 
260 /* The LparMap data is now located at offset 0x6000 in head.S
261  * It was put there so that the HvReleaseData could address it
262  * with a 32-bit offset as required by the iSeries hypervisor
263  *
264  * The Naca has a pointer to the ItVpdAreas.  The hypervisor finds
265  * the Naca via the HvReleaseData area.  The HvReleaseData has the
266  * offset into the Naca of the pointer to the ItVpdAreas.
267  */
268 const struct ItVpdAreas itVpdAreas = {
269         .xSlicDesc = 0xc9a3e5c1,                /* "ItVA" */
270         .xSlicSize = sizeof(struct ItVpdAreas),
271         .xSlicVpdEntries = ItVpdMaxEntries,     /* # VPD array entries */
272         .xSlicDmaEntries = ItDmaMaxEntries,     /* # DMA array entries */
273         .xSlicMaxLogicalProcs = NR_CPUS * 2,    /* Max logical procs */
274         .xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */
275         .xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks),
276         .xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs),
277         .xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens),
278         .xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens),
279         .xSlicMaxSlotLabels = 0,                /* max slot labels */
280         .xSlicMaxLpQueues = 1,                  /* max LP queues */
281         .xPlicDmaLens = { 0 },                  /* DMA lengths */
282         .xPlicDmaToks = { 0 },                  /* DMA tokens */
283         .xSlicVpdLens = {                       /* VPD lengths */
284                 0,0,0,                  /*  0 - 2 */
285                 sizeof(xItExtVpdPanel), /*       3 Extended VPD   */
286                 sizeof(struct alpaca),  /*       4 length of (fake) Paca  */
287                 0,                      /*       5 */
288                 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
289                 26992,                  /*       7 length of MS VPD */
290                 0,                      /*       8 */
291                 sizeof(struct ItLpNaca),/*       9 length of LP Naca */
292                 0,                      /*      10 */
293                 256,                    /*      11 length of Recovery Log Buf */
294                 sizeof(struct SpCommArea), /*   12 length of SP Comm Area */
295                 0,0,0,                  /* 13 - 15 */
296                 sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
297                 0,0,0,0,0,0,            /* 17 - 22  */
298                 sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */
299                 0,0                     /* 24 - 25 */
300                 },
301         .xSlicVpdAdrs = {                       /* VPD addresses */
302                 0,0,0,                  /*       0 -  2 */
303                 &xItExtVpdPanel,        /*       3 Extended VPD */
304                 &alpaca[0],             /*       4 first (fake) Paca */
305                 0,                      /*       5 */
306                 &xItIplParmsReal,       /*       6 IPL parms */
307                 &xMsVpd,                /*       7 MS Vpd */
308                 0,                      /*       8 */
309                 &itLpNaca,              /*       9 LpNaca */
310                 0,                      /*      10 */
311                 &xRecoveryLogBuffer,    /*      11 Recovery Log Buffer */
312                 &xSpCommArea,           /*      12 SP Comm Area */
313                 0,0,0,                  /* 13 - 15 */
314                 &xIoHriProcessorVpd,    /*      16 Proc Vpd */
315                 0,0,0,0,0,0,            /* 17 - 22 */
316                 &hvlpevent_queue,       /*      23 Lp Queue */
317                 0,0
318         }
319 };
320 

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