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TOMOYO Linux Cross Reference
Linux/arch/powerpc/platforms/powernv/eeh-powernv.c

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  1 /*
  2  * The file intends to implement the platform dependent EEH operations on
  3  * powernv platform. Actually, the powernv was created in order to fully
  4  * hypervisor support.
  5  *
  6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  */
 13 
 14 #include <linux/atomic.h>
 15 #include <linux/debugfs.h>
 16 #include <linux/delay.h>
 17 #include <linux/export.h>
 18 #include <linux/init.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/list.h>
 21 #include <linux/msi.h>
 22 #include <linux/of.h>
 23 #include <linux/pci.h>
 24 #include <linux/proc_fs.h>
 25 #include <linux/rbtree.h>
 26 #include <linux/sched.h>
 27 #include <linux/seq_file.h>
 28 #include <linux/spinlock.h>
 29 
 30 #include <asm/eeh.h>
 31 #include <asm/eeh_event.h>
 32 #include <asm/firmware.h>
 33 #include <asm/io.h>
 34 #include <asm/iommu.h>
 35 #include <asm/machdep.h>
 36 #include <asm/msi_bitmap.h>
 37 #include <asm/opal.h>
 38 #include <asm/ppc-pci.h>
 39 #include <asm/pnv-pci.h>
 40 
 41 #include "powernv.h"
 42 #include "pci.h"
 43 
 44 static int eeh_event_irq = -EINVAL;
 45 
 46 void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
 47 {
 48         struct pci_dn *pdn = pci_get_pdn(pdev);
 49 
 50         if (!pdev->is_virtfn)
 51                 return;
 52 
 53         /*
 54          * The following operations will fail if VF's sysfs files
 55          * aren't created or its resources aren't finalized.
 56          */
 57         eeh_add_device_early(pdn);
 58         eeh_add_device_late(pdev);
 59         eeh_sysfs_add_device(pdev);
 60 }
 61 
 62 static int pnv_eeh_init(void)
 63 {
 64         struct pci_controller *hose;
 65         struct pnv_phb *phb;
 66         int max_diag_size = PNV_PCI_DIAG_BUF_SIZE;
 67 
 68         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 69                 pr_warn("%s: OPAL is required !\n",
 70                         __func__);
 71                 return -EINVAL;
 72         }
 73 
 74         /* Set probe mode */
 75         eeh_add_flag(EEH_PROBE_MODE_DEV);
 76 
 77         /*
 78          * P7IOC blocks PCI config access to frozen PE, but PHB3
 79          * doesn't do that. So we have to selectively enable I/O
 80          * prior to collecting error log.
 81          */
 82         list_for_each_entry(hose, &hose_list, list_node) {
 83                 phb = hose->private_data;
 84 
 85                 if (phb->model == PNV_PHB_MODEL_P7IOC)
 86                         eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
 87 
 88                 if (phb->diag_data_size > max_diag_size)
 89                         max_diag_size = phb->diag_data_size;
 90 
 91                 /*
 92                  * PE#0 should be regarded as valid by EEH core
 93                  * if it's not the reserved one. Currently, we
 94                  * have the reserved PE#255 and PE#127 for PHB3
 95                  * and P7IOC separately. So we should regard
 96                  * PE#0 as valid for PHB3 and P7IOC.
 97                  */
 98                 if (phb->ioda.reserved_pe_idx != 0)
 99                         eeh_add_flag(EEH_VALID_PE_ZERO);
100 
101                 break;
102         }
103 
104         eeh_set_pe_aux_size(max_diag_size);
105         ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device;
106 
107         return 0;
108 }
109 
110 static irqreturn_t pnv_eeh_event(int irq, void *data)
111 {
112         /*
113          * We simply send a special EEH event if EEH has been
114          * enabled. We don't care about EEH events until we've
115          * finished processing the outstanding ones. Event processing
116          * gets unmasked in next_error() if EEH is enabled.
117          */
118         disable_irq_nosync(irq);
119 
120         if (eeh_enabled())
121                 eeh_send_failure_event(NULL);
122 
123         return IRQ_HANDLED;
124 }
125 
126 #ifdef CONFIG_DEBUG_FS
127 static ssize_t pnv_eeh_ei_write(struct file *filp,
128                                 const char __user *user_buf,
129                                 size_t count, loff_t *ppos)
130 {
131         struct pci_controller *hose = filp->private_data;
132         struct eeh_pe *pe;
133         int pe_no, type, func;
134         unsigned long addr, mask;
135         char buf[50];
136         int ret;
137 
138         if (!eeh_ops || !eeh_ops->err_inject)
139                 return -ENXIO;
140 
141         /* Copy over argument buffer */
142         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
143         if (!ret)
144                 return -EFAULT;
145 
146         /* Retrieve parameters */
147         ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
148                      &pe_no, &type, &func, &addr, &mask);
149         if (ret != 5)
150                 return -EINVAL;
151 
152         /* Retrieve PE */
153         pe = eeh_pe_get(hose, pe_no, 0);
154         if (!pe)
155                 return -ENODEV;
156 
157         /* Do error injection */
158         ret = eeh_ops->err_inject(pe, type, func, addr, mask);
159         return ret < 0 ? ret : count;
160 }
161 
162 static const struct file_operations pnv_eeh_ei_fops = {
163         .open   = simple_open,
164         .llseek = no_llseek,
165         .write  = pnv_eeh_ei_write,
166 };
167 
168 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
169 {
170         struct pci_controller *hose = data;
171         struct pnv_phb *phb = hose->private_data;
172 
173         out_be64(phb->regs + offset, val);
174         return 0;
175 }
176 
177 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
178 {
179         struct pci_controller *hose = data;
180         struct pnv_phb *phb = hose->private_data;
181 
182         *val = in_be64(phb->regs + offset);
183         return 0;
184 }
185 
186 #define PNV_EEH_DBGFS_ENTRY(name, reg)                          \
187 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val)        \
188 {                                                               \
189         return pnv_eeh_dbgfs_set(data, reg, val);               \
190 }                                                               \
191                                                                 \
192 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val)       \
193 {                                                               \
194         return pnv_eeh_dbgfs_get(data, reg, val);               \
195 }                                                               \
196                                                                 \
197 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name,               \
198                         pnv_eeh_dbgfs_get_##name,               \
199                         pnv_eeh_dbgfs_set_##name,               \
200                         "0x%llx\n")
201 
202 PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
203 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
204 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
205 
206 #endif /* CONFIG_DEBUG_FS */
207 
208 /**
209  * pnv_eeh_post_init - EEH platform dependent post initialization
210  *
211  * EEH platform dependent post initialization on powernv. When
212  * the function is called, the EEH PEs and devices should have
213  * been built. If the I/O cache staff has been built, EEH is
214  * ready to supply service.
215  */
216 int pnv_eeh_post_init(void)
217 {
218         struct pci_controller *hose;
219         struct pnv_phb *phb;
220         int ret = 0;
221 
222         /* Probe devices & build address cache */
223         eeh_probe_devices();
224         eeh_addr_cache_build();
225 
226         /* Register OPAL event notifier */
227         eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
228         if (eeh_event_irq < 0) {
229                 pr_err("%s: Can't register OPAL event interrupt (%d)\n",
230                        __func__, eeh_event_irq);
231                 return eeh_event_irq;
232         }
233 
234         ret = request_irq(eeh_event_irq, pnv_eeh_event,
235                           IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
236         if (ret < 0) {
237                 irq_dispose_mapping(eeh_event_irq);
238                 pr_err("%s: Can't request OPAL event interrupt (%d)\n",
239                        __func__, eeh_event_irq);
240                 return ret;
241         }
242 
243         if (!eeh_enabled())
244                 disable_irq(eeh_event_irq);
245 
246         list_for_each_entry(hose, &hose_list, list_node) {
247                 phb = hose->private_data;
248 
249                 /*
250                  * If EEH is enabled, we're going to rely on that.
251                  * Otherwise, we restore to conventional mechanism
252                  * to clear frozen PE during PCI config access.
253                  */
254                 if (eeh_enabled())
255                         phb->flags |= PNV_PHB_FLAG_EEH;
256                 else
257                         phb->flags &= ~PNV_PHB_FLAG_EEH;
258 
259                 /* Create debugfs entries */
260 #ifdef CONFIG_DEBUG_FS
261                 if (phb->has_dbgfs || !phb->dbgfs)
262                         continue;
263 
264                 phb->has_dbgfs = 1;
265                 debugfs_create_file("err_injct", 0200,
266                                     phb->dbgfs, hose,
267                                     &pnv_eeh_ei_fops);
268 
269                 debugfs_create_file("err_injct_outbound", 0600,
270                                     phb->dbgfs, hose,
271                                     &pnv_eeh_dbgfs_ops_outb);
272                 debugfs_create_file("err_injct_inboundA", 0600,
273                                     phb->dbgfs, hose,
274                                     &pnv_eeh_dbgfs_ops_inbA);
275                 debugfs_create_file("err_injct_inboundB", 0600,
276                                     phb->dbgfs, hose,
277                                     &pnv_eeh_dbgfs_ops_inbB);
278 #endif /* CONFIG_DEBUG_FS */
279         }
280 
281         return ret;
282 }
283 
284 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
285 {
286         int pos = PCI_CAPABILITY_LIST;
287         int cnt = 48;   /* Maximal number of capabilities */
288         u32 status, id;
289 
290         if (!pdn)
291                 return 0;
292 
293         /* Check if the device supports capabilities */
294         pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
295         if (!(status & PCI_STATUS_CAP_LIST))
296                 return 0;
297 
298         while (cnt--) {
299                 pnv_pci_cfg_read(pdn, pos, 1, &pos);
300                 if (pos < 0x40)
301                         break;
302 
303                 pos &= ~3;
304                 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
305                 if (id == 0xff)
306                         break;
307 
308                 /* Found */
309                 if (id == cap)
310                         return pos;
311 
312                 /* Next one */
313                 pos += PCI_CAP_LIST_NEXT;
314         }
315 
316         return 0;
317 }
318 
319 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
320 {
321         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
322         u32 header;
323         int pos = 256, ttl = (4096 - 256) / 8;
324 
325         if (!edev || !edev->pcie_cap)
326                 return 0;
327         if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
328                 return 0;
329         else if (!header)
330                 return 0;
331 
332         while (ttl-- > 0) {
333                 if (PCI_EXT_CAP_ID(header) == cap && pos)
334                         return pos;
335 
336                 pos = PCI_EXT_CAP_NEXT(header);
337                 if (pos < 256)
338                         break;
339 
340                 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
341                         break;
342         }
343 
344         return 0;
345 }
346 
347 /**
348  * pnv_eeh_probe - Do probe on PCI device
349  * @pdn: PCI device node
350  * @data: unused
351  *
352  * When EEH module is installed during system boot, all PCI devices
353  * are checked one by one to see if it supports EEH. The function
354  * is introduced for the purpose. By default, EEH has been enabled
355  * on all PCI devices. That's to say, we only need do necessary
356  * initialization on the corresponding eeh device and create PE
357  * accordingly.
358  *
359  * It's notable that's unsafe to retrieve the EEH device through
360  * the corresponding PCI device. During the PCI device hotplug, which
361  * was possiblly triggered by EEH core, the binding between EEH device
362  * and the PCI device isn't built yet.
363  */
364 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
365 {
366         struct pci_controller *hose = pdn->phb;
367         struct pnv_phb *phb = hose->private_data;
368         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
369         uint32_t pcie_flags;
370         int ret;
371         int config_addr = (pdn->busno << 8) | (pdn->devfn);
372 
373         /*
374          * When probing the root bridge, which doesn't have any
375          * subordinate PCI devices. We don't have OF node for
376          * the root bridge. So it's not reasonable to continue
377          * the probing.
378          */
379         if (!edev || edev->pe)
380                 return NULL;
381 
382         /* Skip for PCI-ISA bridge */
383         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
384                 return NULL;
385 
386         /* Initialize eeh device */
387         edev->class_code = pdn->class_code;
388         edev->mode      &= 0xFFFFFF00;
389         edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
390         edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
391         edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
392         edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
393         if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
394                 edev->mode |= EEH_DEV_BRIDGE;
395                 if (edev->pcie_cap) {
396                         pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
397                                          2, &pcie_flags);
398                         pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
399                         if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
400                                 edev->mode |= EEH_DEV_ROOT_PORT;
401                         else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
402                                 edev->mode |= EEH_DEV_DS_PORT;
403                 }
404         }
405 
406         edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];
407 
408         /* Create PE */
409         ret = eeh_add_to_parent_pe(edev);
410         if (ret) {
411                 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n",
412                         __func__, hose->global_number, pdn->busno,
413                         PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
414                 return NULL;
415         }
416 
417         /*
418          * If the PE contains any one of following adapters, the
419          * PCI config space can't be accessed when dumping EEH log.
420          * Otherwise, we will run into fenced PHB caused by shortage
421          * of outbound credits in the adapter. The PCI config access
422          * should be blocked until PE reset. MMIO access is dropped
423          * by hardware certainly. In order to drop PCI config requests,
424          * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
425          * will be checked in the backend for PE state retrival. If
426          * the PE becomes frozen for the first time and the flag has
427          * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
428          * that PE to block its config space.
429          *
430          * Broadcom BCM5718 2-ports NICs (14e4:1656)
431          * Broadcom Austin 4-ports NICs (14e4:1657)
432          * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
433          * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
434          */
435         if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
436              pdn->device_id == 0x1656) ||
437             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
438              pdn->device_id == 0x1657) ||
439             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
440              pdn->device_id == 0x168a) ||
441             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
442              pdn->device_id == 0x168e))
443                 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
444 
445         /*
446          * Cache the PE primary bus, which can't be fetched when
447          * full hotplug is in progress. In that case, all child
448          * PCI devices of the PE are expected to be removed prior
449          * to PE reset.
450          */
451         if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
452                 edev->pe->bus = pci_find_bus(hose->global_number,
453                                              pdn->busno);
454                 if (edev->pe->bus)
455                         edev->pe->state |= EEH_PE_PRI_BUS;
456         }
457 
458         /*
459          * Enable EEH explicitly so that we will do EEH check
460          * while accessing I/O stuff
461          */
462         eeh_add_flag(EEH_ENABLED);
463 
464         /* Save memory bars */
465         eeh_save_bars(edev);
466 
467         return NULL;
468 }
469 
470 /**
471  * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
472  * @pe: EEH PE
473  * @option: operation to be issued
474  *
475  * The function is used to control the EEH functionality globally.
476  * Currently, following options are support according to PAPR:
477  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
478  */
479 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
480 {
481         struct pci_controller *hose = pe->phb;
482         struct pnv_phb *phb = hose->private_data;
483         bool freeze_pe = false;
484         int opt;
485         s64 rc;
486 
487         switch (option) {
488         case EEH_OPT_DISABLE:
489                 return -EPERM;
490         case EEH_OPT_ENABLE:
491                 return 0;
492         case EEH_OPT_THAW_MMIO:
493                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
494                 break;
495         case EEH_OPT_THAW_DMA:
496                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
497                 break;
498         case EEH_OPT_FREEZE_PE:
499                 freeze_pe = true;
500                 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
501                 break;
502         default:
503                 pr_warn("%s: Invalid option %d\n", __func__, option);
504                 return -EINVAL;
505         }
506 
507         /* Freeze master and slave PEs if PHB supports compound PEs */
508         if (freeze_pe) {
509                 if (phb->freeze_pe) {
510                         phb->freeze_pe(phb, pe->addr);
511                         return 0;
512                 }
513 
514                 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
515                 if (rc != OPAL_SUCCESS) {
516                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
517                                 __func__, rc, phb->hose->global_number,
518                                 pe->addr);
519                         return -EIO;
520                 }
521 
522                 return 0;
523         }
524 
525         /* Unfreeze master and slave PEs if PHB supports */
526         if (phb->unfreeze_pe)
527                 return phb->unfreeze_pe(phb, pe->addr, opt);
528 
529         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
530         if (rc != OPAL_SUCCESS) {
531                 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
532                         __func__, rc, option, phb->hose->global_number,
533                         pe->addr);
534                 return -EIO;
535         }
536 
537         return 0;
538 }
539 
540 /**
541  * pnv_eeh_get_pe_addr - Retrieve PE address
542  * @pe: EEH PE
543  *
544  * Retrieve the PE address according to the given tranditional
545  * PCI BDF (Bus/Device/Function) address.
546  */
547 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
548 {
549         return pe->addr;
550 }
551 
552 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
553 {
554         struct pnv_phb *phb = pe->phb->private_data;
555         s64 rc;
556 
557         rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
558                                          phb->diag_data_size);
559         if (rc != OPAL_SUCCESS)
560                 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
561                         __func__, rc, pe->phb->global_number);
562 }
563 
564 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
565 {
566         struct pnv_phb *phb = pe->phb->private_data;
567         u8 fstate;
568         __be16 pcierr;
569         s64 rc;
570         int result = 0;
571 
572         rc = opal_pci_eeh_freeze_status(phb->opal_id,
573                                         pe->addr,
574                                         &fstate,
575                                         &pcierr,
576                                         NULL);
577         if (rc != OPAL_SUCCESS) {
578                 pr_warn("%s: Failure %lld getting PHB#%x state\n",
579                         __func__, rc, phb->hose->global_number);
580                 return EEH_STATE_NOT_SUPPORT;
581         }
582 
583         /*
584          * Check PHB state. If the PHB is frozen for the
585          * first time, to dump the PHB diag-data.
586          */
587         if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
588                 result = (EEH_STATE_MMIO_ACTIVE  |
589                           EEH_STATE_DMA_ACTIVE   |
590                           EEH_STATE_MMIO_ENABLED |
591                           EEH_STATE_DMA_ENABLED);
592         } else if (!(pe->state & EEH_PE_ISOLATED)) {
593                 eeh_pe_mark_isolated(pe);
594                 pnv_eeh_get_phb_diag(pe);
595 
596                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
597                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
598         }
599 
600         return result;
601 }
602 
603 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
604 {
605         struct pnv_phb *phb = pe->phb->private_data;
606         u8 fstate;
607         __be16 pcierr;
608         s64 rc;
609         int result;
610 
611         /*
612          * We don't clobber hardware frozen state until PE
613          * reset is completed. In order to keep EEH core
614          * moving forward, we have to return operational
615          * state during PE reset.
616          */
617         if (pe->state & EEH_PE_RESET) {
618                 result = (EEH_STATE_MMIO_ACTIVE  |
619                           EEH_STATE_DMA_ACTIVE   |
620                           EEH_STATE_MMIO_ENABLED |
621                           EEH_STATE_DMA_ENABLED);
622                 return result;
623         }
624 
625         /*
626          * Fetch PE state from hardware. If the PHB
627          * supports compound PE, let it handle that.
628          */
629         if (phb->get_pe_state) {
630                 fstate = phb->get_pe_state(phb, pe->addr);
631         } else {
632                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
633                                                 pe->addr,
634                                                 &fstate,
635                                                 &pcierr,
636                                                 NULL);
637                 if (rc != OPAL_SUCCESS) {
638                         pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
639                                 __func__, rc, phb->hose->global_number,
640                                 pe->addr);
641                         return EEH_STATE_NOT_SUPPORT;
642                 }
643         }
644 
645         /* Figure out state */
646         switch (fstate) {
647         case OPAL_EEH_STOPPED_NOT_FROZEN:
648                 result = (EEH_STATE_MMIO_ACTIVE  |
649                           EEH_STATE_DMA_ACTIVE   |
650                           EEH_STATE_MMIO_ENABLED |
651                           EEH_STATE_DMA_ENABLED);
652                 break;
653         case OPAL_EEH_STOPPED_MMIO_FREEZE:
654                 result = (EEH_STATE_DMA_ACTIVE |
655                           EEH_STATE_DMA_ENABLED);
656                 break;
657         case OPAL_EEH_STOPPED_DMA_FREEZE:
658                 result = (EEH_STATE_MMIO_ACTIVE |
659                           EEH_STATE_MMIO_ENABLED);
660                 break;
661         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
662                 result = 0;
663                 break;
664         case OPAL_EEH_STOPPED_RESET:
665                 result = EEH_STATE_RESET_ACTIVE;
666                 break;
667         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
668                 result = EEH_STATE_UNAVAILABLE;
669                 break;
670         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
671                 result = EEH_STATE_NOT_SUPPORT;
672                 break;
673         default:
674                 result = EEH_STATE_NOT_SUPPORT;
675                 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
676                         __func__, phb->hose->global_number,
677                         pe->addr, fstate);
678         }
679 
680         /*
681          * If PHB supports compound PE, to freeze all
682          * slave PEs for consistency.
683          *
684          * If the PE is switching to frozen state for the
685          * first time, to dump the PHB diag-data.
686          */
687         if (!(result & EEH_STATE_NOT_SUPPORT) &&
688             !(result & EEH_STATE_UNAVAILABLE) &&
689             !(result & EEH_STATE_MMIO_ACTIVE) &&
690             !(result & EEH_STATE_DMA_ACTIVE)  &&
691             !(pe->state & EEH_PE_ISOLATED)) {
692                 if (phb->freeze_pe)
693                         phb->freeze_pe(phb, pe->addr);
694 
695                 eeh_pe_mark_isolated(pe);
696                 pnv_eeh_get_phb_diag(pe);
697 
698                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
699                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
700         }
701 
702         return result;
703 }
704 
705 /**
706  * pnv_eeh_get_state - Retrieve PE state
707  * @pe: EEH PE
708  * @delay: delay while PE state is temporarily unavailable
709  *
710  * Retrieve the state of the specified PE. For IODA-compitable
711  * platform, it should be retrieved from IODA table. Therefore,
712  * we prefer passing down to hardware implementation to handle
713  * it.
714  */
715 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
716 {
717         int ret;
718 
719         if (pe->type & EEH_PE_PHB)
720                 ret = pnv_eeh_get_phb_state(pe);
721         else
722                 ret = pnv_eeh_get_pe_state(pe);
723 
724         if (!delay)
725                 return ret;
726 
727         /*
728          * If the PE state is temporarily unavailable,
729          * to inform the EEH core delay for default
730          * period (1 second)
731          */
732         *delay = 0;
733         if (ret & EEH_STATE_UNAVAILABLE)
734                 *delay = 1000;
735 
736         return ret;
737 }
738 
739 static s64 pnv_eeh_poll(unsigned long id)
740 {
741         s64 rc = OPAL_HARDWARE;
742 
743         while (1) {
744                 rc = opal_pci_poll(id);
745                 if (rc <= 0)
746                         break;
747 
748                 if (system_state < SYSTEM_RUNNING)
749                         udelay(1000 * rc);
750                 else
751                         msleep(rc);
752         }
753 
754         return rc;
755 }
756 
757 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
758 {
759         struct pnv_phb *phb = hose->private_data;
760         s64 rc = OPAL_HARDWARE;
761 
762         pr_debug("%s: Reset PHB#%x, option=%d\n",
763                  __func__, hose->global_number, option);
764 
765         /* Issue PHB complete reset request */
766         if (option == EEH_RESET_FUNDAMENTAL ||
767             option == EEH_RESET_HOT)
768                 rc = opal_pci_reset(phb->opal_id,
769                                     OPAL_RESET_PHB_COMPLETE,
770                                     OPAL_ASSERT_RESET);
771         else if (option == EEH_RESET_DEACTIVATE)
772                 rc = opal_pci_reset(phb->opal_id,
773                                     OPAL_RESET_PHB_COMPLETE,
774                                     OPAL_DEASSERT_RESET);
775         if (rc < 0)
776                 goto out;
777 
778         /*
779          * Poll state of the PHB until the request is done
780          * successfully. The PHB reset is usually PHB complete
781          * reset followed by hot reset on root bus. So we also
782          * need the PCI bus settlement delay.
783          */
784         if (rc > 0)
785                 rc = pnv_eeh_poll(phb->opal_id);
786         if (option == EEH_RESET_DEACTIVATE) {
787                 if (system_state < SYSTEM_RUNNING)
788                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
789                 else
790                         msleep(EEH_PE_RST_SETTLE_TIME);
791         }
792 out:
793         if (rc != OPAL_SUCCESS)
794                 return -EIO;
795 
796         return 0;
797 }
798 
799 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
800 {
801         struct pnv_phb *phb = hose->private_data;
802         s64 rc = OPAL_HARDWARE;
803 
804         pr_debug("%s: Reset PHB#%x, option=%d\n",
805                  __func__, hose->global_number, option);
806 
807         /*
808          * During the reset deassert time, we needn't care
809          * the reset scope because the firmware does nothing
810          * for fundamental or hot reset during deassert phase.
811          */
812         if (option == EEH_RESET_FUNDAMENTAL)
813                 rc = opal_pci_reset(phb->opal_id,
814                                     OPAL_RESET_PCI_FUNDAMENTAL,
815                                     OPAL_ASSERT_RESET);
816         else if (option == EEH_RESET_HOT)
817                 rc = opal_pci_reset(phb->opal_id,
818                                     OPAL_RESET_PCI_HOT,
819                                     OPAL_ASSERT_RESET);
820         else if (option == EEH_RESET_DEACTIVATE)
821                 rc = opal_pci_reset(phb->opal_id,
822                                     OPAL_RESET_PCI_HOT,
823                                     OPAL_DEASSERT_RESET);
824         if (rc < 0)
825                 goto out;
826 
827         /* Poll state of the PHB until the request is done */
828         if (rc > 0)
829                 rc = pnv_eeh_poll(phb->opal_id);
830         if (option == EEH_RESET_DEACTIVATE)
831                 msleep(EEH_PE_RST_SETTLE_TIME);
832 out:
833         if (rc != OPAL_SUCCESS)
834                 return -EIO;
835 
836         return 0;
837 }
838 
839 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
840 {
841         struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
842         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
843         int aer = edev ? edev->aer_cap : 0;
844         u32 ctrl;
845 
846         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
847                  __func__, pci_domain_nr(dev->bus),
848                  dev->bus->number, option);
849 
850         switch (option) {
851         case EEH_RESET_FUNDAMENTAL:
852         case EEH_RESET_HOT:
853                 /* Don't report linkDown event */
854                 if (aer) {
855                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
856                                              4, &ctrl);
857                         ctrl |= PCI_ERR_UNC_SURPDN;
858                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
859                                               4, ctrl);
860                 }
861 
862                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
863                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
864                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
865 
866                 msleep(EEH_PE_RST_HOLD_TIME);
867                 break;
868         case EEH_RESET_DEACTIVATE:
869                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
870                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
871                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
872 
873                 msleep(EEH_PE_RST_SETTLE_TIME);
874 
875                 /* Continue reporting linkDown event */
876                 if (aer) {
877                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
878                                              4, &ctrl);
879                         ctrl &= ~PCI_ERR_UNC_SURPDN;
880                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
881                                               4, ctrl);
882                 }
883 
884                 break;
885         }
886 
887         return 0;
888 }
889 
890 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
891 {
892         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
893         struct pnv_phb *phb = hose->private_data;
894         struct device_node *dn = pci_device_to_OF_node(pdev);
895         uint64_t id = PCI_SLOT_ID(phb->opal_id,
896                                   (pdev->bus->number << 8) | pdev->devfn);
897         uint8_t scope;
898         int64_t rc;
899 
900         /* Hot reset to the bus if firmware cannot handle */
901         if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
902                 return __pnv_eeh_bridge_reset(pdev, option);
903 
904         switch (option) {
905         case EEH_RESET_FUNDAMENTAL:
906                 scope = OPAL_RESET_PCI_FUNDAMENTAL;
907                 break;
908         case EEH_RESET_HOT:
909                 scope = OPAL_RESET_PCI_HOT;
910                 break;
911         case EEH_RESET_DEACTIVATE:
912                 return 0;
913         default:
914                 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
915                         __func__, option);
916                 return -EINVAL;
917         }
918 
919         rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
920         if (rc <= OPAL_SUCCESS)
921                 goto out;
922 
923         rc = pnv_eeh_poll(id);
924 out:
925         return (rc == OPAL_SUCCESS) ? 0 : -EIO;
926 }
927 
928 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
929 {
930         struct pci_controller *hose;
931 
932         if (pci_is_root_bus(dev->bus)) {
933                 hose = pci_bus_to_host(dev->bus);
934                 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
935                 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
936         } else {
937                 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
938                 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
939         }
940 }
941 
942 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
943                                      int pos, u16 mask)
944 {
945         int i, status = 0;
946 
947         /* Wait for Transaction Pending bit to be cleared */
948         for (i = 0; i < 4; i++) {
949                 eeh_ops->read_config(pdn, pos, 2, &status);
950                 if (!(status & mask))
951                         return;
952 
953                 msleep((1 << i) * 100);
954         }
955 
956         pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
957                 __func__, type,
958                 pdn->phb->global_number, pdn->busno,
959                 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
960 }
961 
962 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
963 {
964         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
965         u32 reg = 0;
966 
967         if (WARN_ON(!edev->pcie_cap))
968                 return -ENOTTY;
969 
970         eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
971         if (!(reg & PCI_EXP_DEVCAP_FLR))
972                 return -ENOTTY;
973 
974         switch (option) {
975         case EEH_RESET_HOT:
976         case EEH_RESET_FUNDAMENTAL:
977                 pnv_eeh_wait_for_pending(pdn, "",
978                                          edev->pcie_cap + PCI_EXP_DEVSTA,
979                                          PCI_EXP_DEVSTA_TRPND);
980                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
981                                      4, &reg);
982                 reg |= PCI_EXP_DEVCTL_BCR_FLR;
983                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
984                                       4, reg);
985                 msleep(EEH_PE_RST_HOLD_TIME);
986                 break;
987         case EEH_RESET_DEACTIVATE:
988                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
989                                      4, &reg);
990                 reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
991                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
992                                       4, reg);
993                 msleep(EEH_PE_RST_SETTLE_TIME);
994                 break;
995         }
996 
997         return 0;
998 }
999 
1000 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
1001 {
1002         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1003         u32 cap = 0;
1004 
1005         if (WARN_ON(!edev->af_cap))
1006                 return -ENOTTY;
1007 
1008         eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
1009         if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
1010                 return -ENOTTY;
1011 
1012         switch (option) {
1013         case EEH_RESET_HOT:
1014         case EEH_RESET_FUNDAMENTAL:
1015                 /*
1016                  * Wait for Transaction Pending bit to clear. A word-aligned
1017                  * test is used, so we use the conrol offset rather than status
1018                  * and shift the test bit to match.
1019                  */
1020                 pnv_eeh_wait_for_pending(pdn, "AF",
1021                                          edev->af_cap + PCI_AF_CTRL,
1022                                          PCI_AF_STATUS_TP << 8);
1023                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
1024                                       1, PCI_AF_CTRL_FLR);
1025                 msleep(EEH_PE_RST_HOLD_TIME);
1026                 break;
1027         case EEH_RESET_DEACTIVATE:
1028                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
1029                 msleep(EEH_PE_RST_SETTLE_TIME);
1030                 break;
1031         }
1032 
1033         return 0;
1034 }
1035 
1036 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
1037 {
1038         struct eeh_dev *edev;
1039         struct pci_dn *pdn;
1040         int ret;
1041 
1042         /* The VF PE should have only one child device */
1043         edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
1044         pdn = eeh_dev_to_pdn(edev);
1045         if (!pdn)
1046                 return -ENXIO;
1047 
1048         ret = pnv_eeh_do_flr(pdn, option);
1049         if (!ret)
1050                 return ret;
1051 
1052         return pnv_eeh_do_af_flr(pdn, option);
1053 }
1054 
1055 /**
1056  * pnv_eeh_reset - Reset the specified PE
1057  * @pe: EEH PE
1058  * @option: reset option
1059  *
1060  * Do reset on the indicated PE. For PCI bus sensitive PE,
1061  * we need to reset the parent p2p bridge. The PHB has to
1062  * be reinitialized if the p2p bridge is root bridge. For
1063  * PCI device sensitive PE, we will try to reset the device
1064  * through FLR. For now, we don't have OPAL APIs to do HARD
1065  * reset yet, so all reset would be SOFT (HOT) reset.
1066  */
1067 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1068 {
1069         struct pci_controller *hose = pe->phb;
1070         struct pnv_phb *phb;
1071         struct pci_bus *bus;
1072         int64_t rc;
1073 
1074         /*
1075          * For PHB reset, we always have complete reset. For those PEs whose
1076          * primary bus derived from root complex (root bus) or root port
1077          * (usually bus#1), we apply hot or fundamental reset on the root port.
1078          * For other PEs, we always have hot reset on the PE primary bus.
1079          *
1080          * Here, we have different design to pHyp, which always clear the
1081          * frozen state during PE reset. However, the good idea here from
1082          * benh is to keep frozen state before we get PE reset done completely
1083          * (until BAR restore). With the frozen state, HW drops illegal IO
1084          * or MMIO access, which can incur recrusive frozen PE during PE
1085          * reset. The side effect is that EEH core has to clear the frozen
1086          * state explicitly after BAR restore.
1087          */
1088         if (pe->type & EEH_PE_PHB)
1089                 return pnv_eeh_phb_reset(hose, option);
1090 
1091         /*
1092          * The frozen PE might be caused by PAPR error injection
1093          * registers, which are expected to be cleared after hitting
1094          * frozen PE as stated in the hardware spec. Unfortunately,
1095          * that's not true on P7IOC. So we have to clear it manually
1096          * to avoid recursive EEH errors during recovery.
1097          */
1098         phb = hose->private_data;
1099         if (phb->model == PNV_PHB_MODEL_P7IOC &&
1100             (option == EEH_RESET_HOT ||
1101              option == EEH_RESET_FUNDAMENTAL)) {
1102                 rc = opal_pci_reset(phb->opal_id,
1103                                     OPAL_RESET_PHB_ERROR,
1104                                     OPAL_ASSERT_RESET);
1105                 if (rc != OPAL_SUCCESS) {
1106                         pr_warn("%s: Failure %lld clearing error injection registers\n",
1107                                 __func__, rc);
1108                         return -EIO;
1109                 }
1110         }
1111 
1112         if (pe->type & EEH_PE_VF)
1113                 return pnv_eeh_reset_vf_pe(pe, option);
1114 
1115         bus = eeh_pe_bus_get(pe);
1116         if (!bus) {
1117                 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n",
1118                         __func__, pe->phb->global_number, pe->addr);
1119                 return -EIO;
1120         }
1121 
1122         /*
1123          * If dealing with the root bus (or the bus underneath the
1124          * root port), we reset the bus underneath the root port.
1125          *
1126          * The cxl driver depends on this behaviour for bi-modal card
1127          * switching.
1128          */
1129         if (pci_is_root_bus(bus) ||
1130             pci_is_root_bus(bus->parent))
1131                 return pnv_eeh_root_reset(hose, option);
1132 
1133         return pnv_eeh_bridge_reset(bus->self, option);
1134 }
1135 
1136 /**
1137  * pnv_eeh_get_log - Retrieve error log
1138  * @pe: EEH PE
1139  * @severity: temporary or permanent error log
1140  * @drv_log: driver log to be combined with retrieved error log
1141  * @len: length of driver log
1142  *
1143  * Retrieve the temporary or permanent error from the PE.
1144  */
1145 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1146                            char *drv_log, unsigned long len)
1147 {
1148         if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1149                 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1150 
1151         return 0;
1152 }
1153 
1154 /**
1155  * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1156  * @pe: EEH PE
1157  *
1158  * The function will be called to reconfigure the bridges included
1159  * in the specified PE so that the mulfunctional PE would be recovered
1160  * again.
1161  */
1162 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1163 {
1164         return 0;
1165 }
1166 
1167 /**
1168  * pnv_pe_err_inject - Inject specified error to the indicated PE
1169  * @pe: the indicated PE
1170  * @type: error type
1171  * @func: specific error type
1172  * @addr: address
1173  * @mask: address mask
1174  *
1175  * The routine is called to inject specified error, which is
1176  * determined by @type and @func, to the indicated PE for
1177  * testing purpose.
1178  */
1179 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1180                               unsigned long addr, unsigned long mask)
1181 {
1182         struct pci_controller *hose = pe->phb;
1183         struct pnv_phb *phb = hose->private_data;
1184         s64 rc;
1185 
1186         if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1187             type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1188                 pr_warn("%s: Invalid error type %d\n",
1189                         __func__, type);
1190                 return -ERANGE;
1191         }
1192 
1193         if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1194             func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1195                 pr_warn("%s: Invalid error function %d\n",
1196                         __func__, func);
1197                 return -ERANGE;
1198         }
1199 
1200         /* Firmware supports error injection ? */
1201         if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1202                 pr_warn("%s: Firmware doesn't support error injection\n",
1203                         __func__);
1204                 return -ENXIO;
1205         }
1206 
1207         /* Do error injection */
1208         rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1209                                  type, func, addr, mask);
1210         if (rc != OPAL_SUCCESS) {
1211                 pr_warn("%s: Failure %lld injecting error "
1212                         "%d-%d to PHB#%x-PE#%x\n",
1213                         __func__, rc, type, func,
1214                         hose->global_number, pe->addr);
1215                 return -EIO;
1216         }
1217 
1218         return 0;
1219 }
1220 
1221 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1222 {
1223         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1224 
1225         if (!edev || !edev->pe)
1226                 return false;
1227 
1228         /*
1229          * We will issue FLR or AF FLR to all VFs, which are contained
1230          * in VF PE. It relies on the EEH PCI config accessors. So we
1231          * can't block them during the window.
1232          */
1233         if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1234                 return false;
1235 
1236         if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1237                 return true;
1238 
1239         return false;
1240 }
1241 
1242 static int pnv_eeh_read_config(struct pci_dn *pdn,
1243                                int where, int size, u32 *val)
1244 {
1245         if (!pdn)
1246                 return PCIBIOS_DEVICE_NOT_FOUND;
1247 
1248         if (pnv_eeh_cfg_blocked(pdn)) {
1249                 *val = 0xFFFFFFFF;
1250                 return PCIBIOS_SET_FAILED;
1251         }
1252 
1253         return pnv_pci_cfg_read(pdn, where, size, val);
1254 }
1255 
1256 static int pnv_eeh_write_config(struct pci_dn *pdn,
1257                                 int where, int size, u32 val)
1258 {
1259         if (!pdn)
1260                 return PCIBIOS_DEVICE_NOT_FOUND;
1261 
1262         if (pnv_eeh_cfg_blocked(pdn))
1263                 return PCIBIOS_SET_FAILED;
1264 
1265         return pnv_pci_cfg_write(pdn, where, size, val);
1266 }
1267 
1268 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1269 {
1270         /* GEM */
1271         if (data->gemXfir || data->gemRfir ||
1272             data->gemRirqfir || data->gemMask || data->gemRwof)
1273                 pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1274                         be64_to_cpu(data->gemXfir),
1275                         be64_to_cpu(data->gemRfir),
1276                         be64_to_cpu(data->gemRirqfir),
1277                         be64_to_cpu(data->gemMask),
1278                         be64_to_cpu(data->gemRwof));
1279 
1280         /* LEM */
1281         if (data->lemFir || data->lemErrMask ||
1282             data->lemAction0 || data->lemAction1 || data->lemWof)
1283                 pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1284                         be64_to_cpu(data->lemFir),
1285                         be64_to_cpu(data->lemErrMask),
1286                         be64_to_cpu(data->lemAction0),
1287                         be64_to_cpu(data->lemAction1),
1288                         be64_to_cpu(data->lemWof));
1289 }
1290 
1291 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1292 {
1293         struct pnv_phb *phb = hose->private_data;
1294         struct OpalIoP7IOCErrorData *data =
1295                 (struct OpalIoP7IOCErrorData*)phb->diag_data;
1296         long rc;
1297 
1298         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1299         if (rc != OPAL_SUCCESS) {
1300                 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1301                         __func__, phb->hub_id, rc);
1302                 return;
1303         }
1304 
1305         switch (be16_to_cpu(data->type)) {
1306         case OPAL_P7IOC_DIAG_TYPE_RGC:
1307                 pr_info("P7IOC diag-data for RGC\n\n");
1308                 pnv_eeh_dump_hub_diag_common(data);
1309                 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1310                         pr_info("  RGC: %016llx %016llx\n",
1311                                 be64_to_cpu(data->rgc.rgcStatus),
1312                                 be64_to_cpu(data->rgc.rgcLdcp));
1313                 break;
1314         case OPAL_P7IOC_DIAG_TYPE_BI:
1315                 pr_info("P7IOC diag-data for BI %s\n\n",
1316                         data->bi.biDownbound ? "Downbound" : "Upbound");
1317                 pnv_eeh_dump_hub_diag_common(data);
1318                 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1319                     data->bi.biLdcp2 || data->bi.biFenceStatus)
1320                         pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1321                                 be64_to_cpu(data->bi.biLdcp0),
1322                                 be64_to_cpu(data->bi.biLdcp1),
1323                                 be64_to_cpu(data->bi.biLdcp2),
1324                                 be64_to_cpu(data->bi.biFenceStatus));
1325                 break;
1326         case OPAL_P7IOC_DIAG_TYPE_CI:
1327                 pr_info("P7IOC diag-data for CI Port %d\n\n",
1328                         data->ci.ciPort);
1329                 pnv_eeh_dump_hub_diag_common(data);
1330                 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1331                         pr_info("  CI:  %016llx %016llx\n",
1332                                 be64_to_cpu(data->ci.ciPortStatus),
1333                                 be64_to_cpu(data->ci.ciPortLdcp));
1334                 break;
1335         case OPAL_P7IOC_DIAG_TYPE_MISC:
1336                 pr_info("P7IOC diag-data for MISC\n\n");
1337                 pnv_eeh_dump_hub_diag_common(data);
1338                 break;
1339         case OPAL_P7IOC_DIAG_TYPE_I2C:
1340                 pr_info("P7IOC diag-data for I2C\n\n");
1341                 pnv_eeh_dump_hub_diag_common(data);
1342                 break;
1343         default:
1344                 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1345                         __func__, phb->hub_id, data->type);
1346         }
1347 }
1348 
1349 static int pnv_eeh_get_pe(struct pci_controller *hose,
1350                           u16 pe_no, struct eeh_pe **pe)
1351 {
1352         struct pnv_phb *phb = hose->private_data;
1353         struct pnv_ioda_pe *pnv_pe;
1354         struct eeh_pe *dev_pe;
1355 
1356         /*
1357          * If PHB supports compound PE, to fetch
1358          * the master PE because slave PE is invisible
1359          * to EEH core.
1360          */
1361         pnv_pe = &phb->ioda.pe_array[pe_no];
1362         if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1363                 pnv_pe = pnv_pe->master;
1364                 WARN_ON(!pnv_pe ||
1365                         !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1366                 pe_no = pnv_pe->pe_number;
1367         }
1368 
1369         /* Find the PE according to PE# */
1370         dev_pe = eeh_pe_get(hose, pe_no, 0);
1371         if (!dev_pe)
1372                 return -EEXIST;
1373 
1374         /* Freeze the (compound) PE */
1375         *pe = dev_pe;
1376         if (!(dev_pe->state & EEH_PE_ISOLATED))
1377                 phb->freeze_pe(phb, pe_no);
1378 
1379         /*
1380          * At this point, we're sure the (compound) PE should
1381          * have been frozen. However, we still need poke until
1382          * hitting the frozen PE on top level.
1383          */
1384         dev_pe = dev_pe->parent;
1385         while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1386                 int ret;
1387                 ret = eeh_ops->get_state(dev_pe, NULL);
1388                 if (ret <= 0 || eeh_state_active(ret)) {
1389                         dev_pe = dev_pe->parent;
1390                         continue;
1391                 }
1392 
1393                 /* Frozen parent PE */
1394                 *pe = dev_pe;
1395                 if (!(dev_pe->state & EEH_PE_ISOLATED))
1396                         phb->freeze_pe(phb, dev_pe->addr);
1397 
1398                 /* Next one */
1399                 dev_pe = dev_pe->parent;
1400         }
1401 
1402         return 0;
1403 }
1404 
1405 /**
1406  * pnv_eeh_next_error - Retrieve next EEH error to handle
1407  * @pe: Affected PE
1408  *
1409  * The function is expected to be called by EEH core while it gets
1410  * special EEH event (without binding PE). The function calls to
1411  * OPAL APIs for next error to handle. The informational error is
1412  * handled internally by platform. However, the dead IOC, dead PHB,
1413  * fenced PHB and frozen PE should be handled by EEH core eventually.
1414  */
1415 static int pnv_eeh_next_error(struct eeh_pe **pe)
1416 {
1417         struct pci_controller *hose;
1418         struct pnv_phb *phb;
1419         struct eeh_pe *phb_pe, *parent_pe;
1420         __be64 frozen_pe_no;
1421         __be16 err_type, severity;
1422         long rc;
1423         int state, ret = EEH_NEXT_ERR_NONE;
1424 
1425         /*
1426          * While running here, it's safe to purge the event queue. The
1427          * event should still be masked.
1428          */
1429         eeh_remove_event(NULL, false);
1430 
1431         list_for_each_entry(hose, &hose_list, list_node) {
1432                 /*
1433                  * If the subordinate PCI buses of the PHB has been
1434                  * removed or is exactly under error recovery, we
1435                  * needn't take care of it any more.
1436                  */
1437                 phb = hose->private_data;
1438                 phb_pe = eeh_phb_pe_get(hose);
1439                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1440                         continue;
1441 
1442                 rc = opal_pci_next_error(phb->opal_id,
1443                                          &frozen_pe_no, &err_type, &severity);
1444                 if (rc != OPAL_SUCCESS) {
1445                         pr_devel("%s: Invalid return value on "
1446                                  "PHB#%x (0x%lx) from opal_pci_next_error",
1447                                  __func__, hose->global_number, rc);
1448                         continue;
1449                 }
1450 
1451                 /* If the PHB doesn't have error, stop processing */
1452                 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1453                     be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1454                         pr_devel("%s: No error found on PHB#%x\n",
1455                                  __func__, hose->global_number);
1456                         continue;
1457                 }
1458 
1459                 /*
1460                  * Processing the error. We're expecting the error with
1461                  * highest priority reported upon multiple errors on the
1462                  * specific PHB.
1463                  */
1464                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1465                         __func__, be16_to_cpu(err_type),
1466                         be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1467                         hose->global_number);
1468                 switch (be16_to_cpu(err_type)) {
1469                 case OPAL_EEH_IOC_ERROR:
1470                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1471                                 pr_err("EEH: dead IOC detected\n");
1472                                 ret = EEH_NEXT_ERR_DEAD_IOC;
1473                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1474                                 pr_info("EEH: IOC informative error "
1475                                         "detected\n");
1476                                 pnv_eeh_get_and_dump_hub_diag(hose);
1477                                 ret = EEH_NEXT_ERR_NONE;
1478                         }
1479 
1480                         break;
1481                 case OPAL_EEH_PHB_ERROR:
1482                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1483                                 *pe = phb_pe;
1484                                 pr_err("EEH: dead PHB#%x detected, "
1485                                        "location: %s\n",
1486                                         hose->global_number,
1487                                         eeh_pe_loc_get(phb_pe));
1488                                 ret = EEH_NEXT_ERR_DEAD_PHB;
1489                         } else if (be16_to_cpu(severity) ==
1490                                    OPAL_EEH_SEV_PHB_FENCED) {
1491                                 *pe = phb_pe;
1492                                 pr_err("EEH: Fenced PHB#%x detected, "
1493                                        "location: %s\n",
1494                                         hose->global_number,
1495                                         eeh_pe_loc_get(phb_pe));
1496                                 ret = EEH_NEXT_ERR_FENCED_PHB;
1497                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1498                                 pr_info("EEH: PHB#%x informative error "
1499                                         "detected, location: %s\n",
1500                                         hose->global_number,
1501                                         eeh_pe_loc_get(phb_pe));
1502                                 pnv_eeh_get_phb_diag(phb_pe);
1503                                 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1504                                 ret = EEH_NEXT_ERR_NONE;
1505                         }
1506 
1507                         break;
1508                 case OPAL_EEH_PE_ERROR:
1509                         /*
1510                          * If we can't find the corresponding PE, we
1511                          * just try to unfreeze.
1512                          */
1513                         if (pnv_eeh_get_pe(hose,
1514                                 be64_to_cpu(frozen_pe_no), pe)) {
1515                                 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1516                                         hose->global_number, be64_to_cpu(frozen_pe_no));
1517                                 pr_info("EEH: PHB location: %s\n",
1518                                         eeh_pe_loc_get(phb_pe));
1519 
1520                                 /* Dump PHB diag-data */
1521                                 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1522                                         phb->diag_data, phb->diag_data_size);
1523                                 if (rc == OPAL_SUCCESS)
1524                                         pnv_pci_dump_phb_diag_data(hose,
1525                                                         phb->diag_data);
1526 
1527                                 /* Try best to clear it */
1528                                 opal_pci_eeh_freeze_clear(phb->opal_id,
1529                                         be64_to_cpu(frozen_pe_no),
1530                                         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1531                                 ret = EEH_NEXT_ERR_NONE;
1532                         } else if ((*pe)->state & EEH_PE_ISOLATED ||
1533                                    eeh_pe_passed(*pe)) {
1534                                 ret = EEH_NEXT_ERR_NONE;
1535                         } else {
1536                                 pr_err("EEH: Frozen PE#%x "
1537                                        "on PHB#%x detected\n",
1538                                        (*pe)->addr,
1539                                         (*pe)->phb->global_number);
1540                                 pr_err("EEH: PE location: %s, "
1541                                        "PHB location: %s\n",
1542                                        eeh_pe_loc_get(*pe),
1543                                        eeh_pe_loc_get(phb_pe));
1544                                 ret = EEH_NEXT_ERR_FROZEN_PE;
1545                         }
1546 
1547                         break;
1548                 default:
1549                         pr_warn("%s: Unexpected error type %d\n",
1550                                 __func__, be16_to_cpu(err_type));
1551                 }
1552 
1553                 /*
1554                  * EEH core will try recover from fenced PHB or
1555                  * frozen PE. In the time for frozen PE, EEH core
1556                  * enable IO path for that before collecting logs,
1557                  * but it ruins the site. So we have to dump the
1558                  * log in advance here.
1559                  */
1560                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1561                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
1562                     !((*pe)->state & EEH_PE_ISOLATED)) {
1563                         eeh_pe_mark_isolated(*pe);
1564                         pnv_eeh_get_phb_diag(*pe);
1565 
1566                         if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1567                                 pnv_pci_dump_phb_diag_data((*pe)->phb,
1568                                                            (*pe)->data);
1569                 }
1570 
1571                 /*
1572                  * We probably have the frozen parent PE out there and
1573                  * we need have to handle frozen parent PE firstly.
1574                  */
1575                 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1576                         parent_pe = (*pe)->parent;
1577                         while (parent_pe) {
1578                                 /* Hit the ceiling ? */
1579                                 if (parent_pe->type & EEH_PE_PHB)
1580                                         break;
1581 
1582                                 /* Frozen parent PE ? */
1583                                 state = eeh_ops->get_state(parent_pe, NULL);
1584                                 if (state > 0 && !eeh_state_active(state))
1585                                         *pe = parent_pe;
1586 
1587                                 /* Next parent level */
1588                                 parent_pe = parent_pe->parent;
1589                         }
1590 
1591                         /* We possibly migrate to another PE */
1592                         eeh_pe_mark_isolated(*pe);
1593                 }
1594 
1595                 /*
1596                  * If we have no errors on the specific PHB or only
1597                  * informative error there, we continue poking it.
1598                  * Otherwise, we need actions to be taken by upper
1599                  * layer.
1600                  */
1601                 if (ret > EEH_NEXT_ERR_INF)
1602                         break;
1603         }
1604 
1605         /* Unmask the event */
1606         if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1607                 enable_irq(eeh_event_irq);
1608 
1609         return ret;
1610 }
1611 
1612 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1613 {
1614         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1615         struct pnv_phb *phb;
1616         s64 ret = 0;
1617         int config_addr = (pdn->busno << 8) | (pdn->devfn);
1618 
1619         if (!edev)
1620                 return -EEXIST;
1621 
1622         /*
1623          * We have to restore the PCI config space after reset since the
1624          * firmware can't see SRIOV VFs.
1625          *
1626          * FIXME: The MPS, error routing rules, timeout setting are worthy
1627          * to be exported by firmware in extendible way.
1628          */
1629         if (edev->physfn) {
1630                 ret = eeh_restore_vf_config(pdn);
1631         } else {
1632                 phb = pdn->phb->private_data;
1633                 ret = opal_pci_reinit(phb->opal_id,
1634                                       OPAL_REINIT_PCI_DEV, config_addr);
1635         }
1636 
1637         if (ret) {
1638                 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1639                         __func__, config_addr, ret);
1640                 return -EIO;
1641         }
1642 
1643         return ret;
1644 }
1645 
1646 static struct eeh_ops pnv_eeh_ops = {
1647         .name                   = "powernv",
1648         .init                   = pnv_eeh_init,
1649         .probe                  = pnv_eeh_probe,
1650         .set_option             = pnv_eeh_set_option,
1651         .get_pe_addr            = pnv_eeh_get_pe_addr,
1652         .get_state              = pnv_eeh_get_state,
1653         .reset                  = pnv_eeh_reset,
1654         .get_log                = pnv_eeh_get_log,
1655         .configure_bridge       = pnv_eeh_configure_bridge,
1656         .err_inject             = pnv_eeh_err_inject,
1657         .read_config            = pnv_eeh_read_config,
1658         .write_config           = pnv_eeh_write_config,
1659         .next_error             = pnv_eeh_next_error,
1660         .restore_config         = pnv_eeh_restore_config,
1661         .notify_resume          = NULL
1662 };
1663 
1664 #ifdef CONFIG_PCI_IOV
1665 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
1666 {
1667         struct pci_dn *pdn = pci_get_pdn(pdev);
1668         int parent_mps;
1669 
1670         if (!pdev->is_virtfn)
1671                 return;
1672 
1673         /* Synchronize MPS for VF and PF */
1674         parent_mps = pcie_get_mps(pdev->physfn);
1675         if ((128 << pdev->pcie_mpss) >= parent_mps)
1676                 pcie_set_mps(pdev, parent_mps);
1677         pdn->mps = pcie_get_mps(pdev);
1678 }
1679 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
1680 #endif /* CONFIG_PCI_IOV */
1681 
1682 /**
1683  * eeh_powernv_init - Register platform dependent EEH operations
1684  *
1685  * EEH initialization on powernv platform. This function should be
1686  * called before any EEH related functions.
1687  */
1688 static int __init eeh_powernv_init(void)
1689 {
1690         int ret = -EINVAL;
1691 
1692         ret = eeh_ops_register(&pnv_eeh_ops);
1693         if (!ret)
1694                 pr_info("EEH: PowerNV platform initialized\n");
1695         else
1696                 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1697 
1698         return ret;
1699 }
1700 machine_early_initcall(powernv, eeh_powernv_init);
1701 

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