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TOMOYO Linux Cross Reference
Linux/arch/powerpc/platforms/powernv/eeh-powernv.c

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  1 /*
  2  * The file intends to implement the platform dependent EEH operations on
  3  * powernv platform. Actually, the powernv was created in order to fully
  4  * hypervisor support.
  5  *
  6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  */
 13 
 14 #include <linux/atomic.h>
 15 #include <linux/debugfs.h>
 16 #include <linux/delay.h>
 17 #include <linux/export.h>
 18 #include <linux/init.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/list.h>
 21 #include <linux/msi.h>
 22 #include <linux/of.h>
 23 #include <linux/pci.h>
 24 #include <linux/proc_fs.h>
 25 #include <linux/rbtree.h>
 26 #include <linux/sched.h>
 27 #include <linux/seq_file.h>
 28 #include <linux/spinlock.h>
 29 
 30 #include <asm/eeh.h>
 31 #include <asm/eeh_event.h>
 32 #include <asm/firmware.h>
 33 #include <asm/io.h>
 34 #include <asm/iommu.h>
 35 #include <asm/machdep.h>
 36 #include <asm/msi_bitmap.h>
 37 #include <asm/opal.h>
 38 #include <asm/ppc-pci.h>
 39 #include <asm/pnv-pci.h>
 40 
 41 #include "powernv.h"
 42 #include "pci.h"
 43 
 44 static int eeh_event_irq = -EINVAL;
 45 
 46 void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
 47 {
 48         struct pci_dn *pdn = pci_get_pdn(pdev);
 49 
 50         if (!pdev->is_virtfn)
 51                 return;
 52 
 53         /*
 54          * The following operations will fail if VF's sysfs files
 55          * aren't created or its resources aren't finalized.
 56          */
 57         eeh_add_device_early(pdn);
 58         eeh_add_device_late(pdev);
 59         eeh_sysfs_add_device(pdev);
 60 }
 61 
 62 static int pnv_eeh_init(void)
 63 {
 64         struct pci_controller *hose;
 65         struct pnv_phb *phb;
 66         int max_diag_size = PNV_PCI_DIAG_BUF_SIZE;
 67 
 68         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 69                 pr_warn("%s: OPAL is required !\n",
 70                         __func__);
 71                 return -EINVAL;
 72         }
 73 
 74         /* Set probe mode */
 75         eeh_add_flag(EEH_PROBE_MODE_DEV);
 76 
 77         /*
 78          * P7IOC blocks PCI config access to frozen PE, but PHB3
 79          * doesn't do that. So we have to selectively enable I/O
 80          * prior to collecting error log.
 81          */
 82         list_for_each_entry(hose, &hose_list, list_node) {
 83                 phb = hose->private_data;
 84 
 85                 if (phb->model == PNV_PHB_MODEL_P7IOC)
 86                         eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
 87 
 88                 if (phb->diag_data_size > max_diag_size)
 89                         max_diag_size = phb->diag_data_size;
 90 
 91                 /*
 92                  * PE#0 should be regarded as valid by EEH core
 93                  * if it's not the reserved one. Currently, we
 94                  * have the reserved PE#255 and PE#127 for PHB3
 95                  * and P7IOC separately. So we should regard
 96                  * PE#0 as valid for PHB3 and P7IOC.
 97                  */
 98                 if (phb->ioda.reserved_pe_idx != 0)
 99                         eeh_add_flag(EEH_VALID_PE_ZERO);
100 
101                 break;
102         }
103 
104         eeh_set_pe_aux_size(max_diag_size);
105         ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device;
106 
107         return 0;
108 }
109 
110 static irqreturn_t pnv_eeh_event(int irq, void *data)
111 {
112         /*
113          * We simply send a special EEH event if EEH has been
114          * enabled. We don't care about EEH events until we've
115          * finished processing the outstanding ones. Event processing
116          * gets unmasked in next_error() if EEH is enabled.
117          */
118         disable_irq_nosync(irq);
119 
120         if (eeh_enabled())
121                 eeh_send_failure_event(NULL);
122 
123         return IRQ_HANDLED;
124 }
125 
126 #ifdef CONFIG_DEBUG_FS
127 static ssize_t pnv_eeh_ei_write(struct file *filp,
128                                 const char __user *user_buf,
129                                 size_t count, loff_t *ppos)
130 {
131         struct pci_controller *hose = filp->private_data;
132         struct eeh_pe *pe;
133         int pe_no, type, func;
134         unsigned long addr, mask;
135         char buf[50];
136         int ret;
137 
138         if (!eeh_ops || !eeh_ops->err_inject)
139                 return -ENXIO;
140 
141         /* Copy over argument buffer */
142         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
143         if (!ret)
144                 return -EFAULT;
145 
146         /* Retrieve parameters */
147         ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
148                      &pe_no, &type, &func, &addr, &mask);
149         if (ret != 5)
150                 return -EINVAL;
151 
152         /* Retrieve PE */
153         pe = eeh_pe_get(hose, pe_no, 0);
154         if (!pe)
155                 return -ENODEV;
156 
157         /* Do error injection */
158         ret = eeh_ops->err_inject(pe, type, func, addr, mask);
159         return ret < 0 ? ret : count;
160 }
161 
162 static const struct file_operations pnv_eeh_ei_fops = {
163         .open   = simple_open,
164         .llseek = no_llseek,
165         .write  = pnv_eeh_ei_write,
166 };
167 
168 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
169 {
170         struct pci_controller *hose = data;
171         struct pnv_phb *phb = hose->private_data;
172 
173         out_be64(phb->regs + offset, val);
174         return 0;
175 }
176 
177 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
178 {
179         struct pci_controller *hose = data;
180         struct pnv_phb *phb = hose->private_data;
181 
182         *val = in_be64(phb->regs + offset);
183         return 0;
184 }
185 
186 #define PNV_EEH_DBGFS_ENTRY(name, reg)                          \
187 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val)        \
188 {                                                               \
189         return pnv_eeh_dbgfs_set(data, reg, val);               \
190 }                                                               \
191                                                                 \
192 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val)       \
193 {                                                               \
194         return pnv_eeh_dbgfs_get(data, reg, val);               \
195 }                                                               \
196                                                                 \
197 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name,               \
198                         pnv_eeh_dbgfs_get_##name,               \
199                         pnv_eeh_dbgfs_set_##name,               \
200                         "0x%llx\n")
201 
202 PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
203 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
204 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
205 
206 #endif /* CONFIG_DEBUG_FS */
207 
208 /**
209  * pnv_eeh_post_init - EEH platform dependent post initialization
210  *
211  * EEH platform dependent post initialization on powernv. When
212  * the function is called, the EEH PEs and devices should have
213  * been built. If the I/O cache staff has been built, EEH is
214  * ready to supply service.
215  */
216 int pnv_eeh_post_init(void)
217 {
218         struct pci_controller *hose;
219         struct pnv_phb *phb;
220         int ret = 0;
221 
222         /* Probe devices & build address cache */
223         eeh_probe_devices();
224         eeh_addr_cache_build();
225 
226         if (eeh_has_flag(EEH_POSTPONED_PROBE)) {
227                 eeh_clear_flag(EEH_POSTPONED_PROBE);
228                 if (eeh_enabled())
229                         pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
230                 else
231                         pr_info("EEH: No capable adapters found\n");
232         }
233 
234         /* Register OPAL event notifier */
235         eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
236         if (eeh_event_irq < 0) {
237                 pr_err("%s: Can't register OPAL event interrupt (%d)\n",
238                        __func__, eeh_event_irq);
239                 return eeh_event_irq;
240         }
241 
242         ret = request_irq(eeh_event_irq, pnv_eeh_event,
243                           IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
244         if (ret < 0) {
245                 irq_dispose_mapping(eeh_event_irq);
246                 pr_err("%s: Can't request OPAL event interrupt (%d)\n",
247                        __func__, eeh_event_irq);
248                 return ret;
249         }
250 
251         if (!eeh_enabled())
252                 disable_irq(eeh_event_irq);
253 
254         list_for_each_entry(hose, &hose_list, list_node) {
255                 phb = hose->private_data;
256 
257                 /*
258                  * If EEH is enabled, we're going to rely on that.
259                  * Otherwise, we restore to conventional mechanism
260                  * to clear frozen PE during PCI config access.
261                  */
262                 if (eeh_enabled())
263                         phb->flags |= PNV_PHB_FLAG_EEH;
264                 else
265                         phb->flags &= ~PNV_PHB_FLAG_EEH;
266 
267                 /* Create debugfs entries */
268 #ifdef CONFIG_DEBUG_FS
269                 if (phb->has_dbgfs || !phb->dbgfs)
270                         continue;
271 
272                 phb->has_dbgfs = 1;
273                 debugfs_create_file("err_injct", 0200,
274                                     phb->dbgfs, hose,
275                                     &pnv_eeh_ei_fops);
276 
277                 debugfs_create_file("err_injct_outbound", 0600,
278                                     phb->dbgfs, hose,
279                                     &pnv_eeh_dbgfs_ops_outb);
280                 debugfs_create_file("err_injct_inboundA", 0600,
281                                     phb->dbgfs, hose,
282                                     &pnv_eeh_dbgfs_ops_inbA);
283                 debugfs_create_file("err_injct_inboundB", 0600,
284                                     phb->dbgfs, hose,
285                                     &pnv_eeh_dbgfs_ops_inbB);
286 #endif /* CONFIG_DEBUG_FS */
287         }
288 
289         return ret;
290 }
291 
292 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
293 {
294         int pos = PCI_CAPABILITY_LIST;
295         int cnt = 48;   /* Maximal number of capabilities */
296         u32 status, id;
297 
298         if (!pdn)
299                 return 0;
300 
301         /* Check if the device supports capabilities */
302         pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
303         if (!(status & PCI_STATUS_CAP_LIST))
304                 return 0;
305 
306         while (cnt--) {
307                 pnv_pci_cfg_read(pdn, pos, 1, &pos);
308                 if (pos < 0x40)
309                         break;
310 
311                 pos &= ~3;
312                 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
313                 if (id == 0xff)
314                         break;
315 
316                 /* Found */
317                 if (id == cap)
318                         return pos;
319 
320                 /* Next one */
321                 pos += PCI_CAP_LIST_NEXT;
322         }
323 
324         return 0;
325 }
326 
327 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
328 {
329         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
330         u32 header;
331         int pos = 256, ttl = (4096 - 256) / 8;
332 
333         if (!edev || !edev->pcie_cap)
334                 return 0;
335         if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
336                 return 0;
337         else if (!header)
338                 return 0;
339 
340         while (ttl-- > 0) {
341                 if (PCI_EXT_CAP_ID(header) == cap && pos)
342                         return pos;
343 
344                 pos = PCI_EXT_CAP_NEXT(header);
345                 if (pos < 256)
346                         break;
347 
348                 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
349                         break;
350         }
351 
352         return 0;
353 }
354 
355 /**
356  * pnv_eeh_probe - Do probe on PCI device
357  * @pdn: PCI device node
358  * @data: unused
359  *
360  * When EEH module is installed during system boot, all PCI devices
361  * are checked one by one to see if it supports EEH. The function
362  * is introduced for the purpose. By default, EEH has been enabled
363  * on all PCI devices. That's to say, we only need do necessary
364  * initialization on the corresponding eeh device and create PE
365  * accordingly.
366  *
367  * It's notable that's unsafe to retrieve the EEH device through
368  * the corresponding PCI device. During the PCI device hotplug, which
369  * was possiblly triggered by EEH core, the binding between EEH device
370  * and the PCI device isn't built yet.
371  */
372 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
373 {
374         struct pci_controller *hose = pdn->phb;
375         struct pnv_phb *phb = hose->private_data;
376         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
377         uint32_t pcie_flags;
378         int ret;
379         int config_addr = (pdn->busno << 8) | (pdn->devfn);
380 
381         /*
382          * When probing the root bridge, which doesn't have any
383          * subordinate PCI devices. We don't have OF node for
384          * the root bridge. So it's not reasonable to continue
385          * the probing.
386          */
387         if (!edev || edev->pe)
388                 return NULL;
389 
390         /* Skip for PCI-ISA bridge */
391         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
392                 return NULL;
393 
394         /* Skip if we haven't probed yet */
395         if (phb->ioda.pe_rmap[config_addr] == IODA_INVALID_PE) {
396                 eeh_add_flag(EEH_POSTPONED_PROBE);
397                 return NULL;
398         }
399 
400         /* Initialize eeh device */
401         edev->class_code = pdn->class_code;
402         edev->mode      &= 0xFFFFFF00;
403         edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
404         edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
405         edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
406         edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
407         if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
408                 edev->mode |= EEH_DEV_BRIDGE;
409                 if (edev->pcie_cap) {
410                         pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
411                                          2, &pcie_flags);
412                         pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
413                         if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
414                                 edev->mode |= EEH_DEV_ROOT_PORT;
415                         else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
416                                 edev->mode |= EEH_DEV_DS_PORT;
417                 }
418         }
419 
420         edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];
421 
422         /* Create PE */
423         ret = eeh_add_to_parent_pe(edev);
424         if (ret) {
425                 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n",
426                         __func__, hose->global_number, pdn->busno,
427                         PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
428                 return NULL;
429         }
430 
431         /*
432          * If the PE contains any one of following adapters, the
433          * PCI config space can't be accessed when dumping EEH log.
434          * Otherwise, we will run into fenced PHB caused by shortage
435          * of outbound credits in the adapter. The PCI config access
436          * should be blocked until PE reset. MMIO access is dropped
437          * by hardware certainly. In order to drop PCI config requests,
438          * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
439          * will be checked in the backend for PE state retrival. If
440          * the PE becomes frozen for the first time and the flag has
441          * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
442          * that PE to block its config space.
443          *
444          * Broadcom BCM5718 2-ports NICs (14e4:1656)
445          * Broadcom Austin 4-ports NICs (14e4:1657)
446          * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
447          * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
448          */
449         if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
450              pdn->device_id == 0x1656) ||
451             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
452              pdn->device_id == 0x1657) ||
453             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
454              pdn->device_id == 0x168a) ||
455             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
456              pdn->device_id == 0x168e))
457                 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
458 
459         /*
460          * Cache the PE primary bus, which can't be fetched when
461          * full hotplug is in progress. In that case, all child
462          * PCI devices of the PE are expected to be removed prior
463          * to PE reset.
464          */
465         if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
466                 edev->pe->bus = pci_find_bus(hose->global_number,
467                                              pdn->busno);
468                 if (edev->pe->bus)
469                         edev->pe->state |= EEH_PE_PRI_BUS;
470         }
471 
472         /*
473          * Enable EEH explicitly so that we will do EEH check
474          * while accessing I/O stuff
475          */
476         eeh_add_flag(EEH_ENABLED);
477 
478         /* Save memory bars */
479         eeh_save_bars(edev);
480 
481         return NULL;
482 }
483 
484 /**
485  * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
486  * @pe: EEH PE
487  * @option: operation to be issued
488  *
489  * The function is used to control the EEH functionality globally.
490  * Currently, following options are support according to PAPR:
491  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
492  */
493 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
494 {
495         struct pci_controller *hose = pe->phb;
496         struct pnv_phb *phb = hose->private_data;
497         bool freeze_pe = false;
498         int opt;
499         s64 rc;
500 
501         switch (option) {
502         case EEH_OPT_DISABLE:
503                 return -EPERM;
504         case EEH_OPT_ENABLE:
505                 return 0;
506         case EEH_OPT_THAW_MMIO:
507                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
508                 break;
509         case EEH_OPT_THAW_DMA:
510                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
511                 break;
512         case EEH_OPT_FREEZE_PE:
513                 freeze_pe = true;
514                 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
515                 break;
516         default:
517                 pr_warn("%s: Invalid option %d\n", __func__, option);
518                 return -EINVAL;
519         }
520 
521         /* Freeze master and slave PEs if PHB supports compound PEs */
522         if (freeze_pe) {
523                 if (phb->freeze_pe) {
524                         phb->freeze_pe(phb, pe->addr);
525                         return 0;
526                 }
527 
528                 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
529                 if (rc != OPAL_SUCCESS) {
530                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
531                                 __func__, rc, phb->hose->global_number,
532                                 pe->addr);
533                         return -EIO;
534                 }
535 
536                 return 0;
537         }
538 
539         /* Unfreeze master and slave PEs if PHB supports */
540         if (phb->unfreeze_pe)
541                 return phb->unfreeze_pe(phb, pe->addr, opt);
542 
543         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
544         if (rc != OPAL_SUCCESS) {
545                 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
546                         __func__, rc, option, phb->hose->global_number,
547                         pe->addr);
548                 return -EIO;
549         }
550 
551         return 0;
552 }
553 
554 /**
555  * pnv_eeh_get_pe_addr - Retrieve PE address
556  * @pe: EEH PE
557  *
558  * Retrieve the PE address according to the given tranditional
559  * PCI BDF (Bus/Device/Function) address.
560  */
561 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
562 {
563         return pe->addr;
564 }
565 
566 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
567 {
568         struct pnv_phb *phb = pe->phb->private_data;
569         s64 rc;
570 
571         rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
572                                          phb->diag_data_size);
573         if (rc != OPAL_SUCCESS)
574                 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
575                         __func__, rc, pe->phb->global_number);
576 }
577 
578 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
579 {
580         struct pnv_phb *phb = pe->phb->private_data;
581         u8 fstate;
582         __be16 pcierr;
583         s64 rc;
584         int result = 0;
585 
586         rc = opal_pci_eeh_freeze_status(phb->opal_id,
587                                         pe->addr,
588                                         &fstate,
589                                         &pcierr,
590                                         NULL);
591         if (rc != OPAL_SUCCESS) {
592                 pr_warn("%s: Failure %lld getting PHB#%x state\n",
593                         __func__, rc, phb->hose->global_number);
594                 return EEH_STATE_NOT_SUPPORT;
595         }
596 
597         /*
598          * Check PHB state. If the PHB is frozen for the
599          * first time, to dump the PHB diag-data.
600          */
601         if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
602                 result = (EEH_STATE_MMIO_ACTIVE  |
603                           EEH_STATE_DMA_ACTIVE   |
604                           EEH_STATE_MMIO_ENABLED |
605                           EEH_STATE_DMA_ENABLED);
606         } else if (!(pe->state & EEH_PE_ISOLATED)) {
607                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
608                 pnv_eeh_get_phb_diag(pe);
609 
610                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
611                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
612         }
613 
614         return result;
615 }
616 
617 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
618 {
619         struct pnv_phb *phb = pe->phb->private_data;
620         u8 fstate;
621         __be16 pcierr;
622         s64 rc;
623         int result;
624 
625         /*
626          * We don't clobber hardware frozen state until PE
627          * reset is completed. In order to keep EEH core
628          * moving forward, we have to return operational
629          * state during PE reset.
630          */
631         if (pe->state & EEH_PE_RESET) {
632                 result = (EEH_STATE_MMIO_ACTIVE  |
633                           EEH_STATE_DMA_ACTIVE   |
634                           EEH_STATE_MMIO_ENABLED |
635                           EEH_STATE_DMA_ENABLED);
636                 return result;
637         }
638 
639         /*
640          * Fetch PE state from hardware. If the PHB
641          * supports compound PE, let it handle that.
642          */
643         if (phb->get_pe_state) {
644                 fstate = phb->get_pe_state(phb, pe->addr);
645         } else {
646                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
647                                                 pe->addr,
648                                                 &fstate,
649                                                 &pcierr,
650                                                 NULL);
651                 if (rc != OPAL_SUCCESS) {
652                         pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
653                                 __func__, rc, phb->hose->global_number,
654                                 pe->addr);
655                         return EEH_STATE_NOT_SUPPORT;
656                 }
657         }
658 
659         /* Figure out state */
660         switch (fstate) {
661         case OPAL_EEH_STOPPED_NOT_FROZEN:
662                 result = (EEH_STATE_MMIO_ACTIVE  |
663                           EEH_STATE_DMA_ACTIVE   |
664                           EEH_STATE_MMIO_ENABLED |
665                           EEH_STATE_DMA_ENABLED);
666                 break;
667         case OPAL_EEH_STOPPED_MMIO_FREEZE:
668                 result = (EEH_STATE_DMA_ACTIVE |
669                           EEH_STATE_DMA_ENABLED);
670                 break;
671         case OPAL_EEH_STOPPED_DMA_FREEZE:
672                 result = (EEH_STATE_MMIO_ACTIVE |
673                           EEH_STATE_MMIO_ENABLED);
674                 break;
675         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
676                 result = 0;
677                 break;
678         case OPAL_EEH_STOPPED_RESET:
679                 result = EEH_STATE_RESET_ACTIVE;
680                 break;
681         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
682                 result = EEH_STATE_UNAVAILABLE;
683                 break;
684         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
685                 result = EEH_STATE_NOT_SUPPORT;
686                 break;
687         default:
688                 result = EEH_STATE_NOT_SUPPORT;
689                 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
690                         __func__, phb->hose->global_number,
691                         pe->addr, fstate);
692         }
693 
694         /*
695          * If PHB supports compound PE, to freeze all
696          * slave PEs for consistency.
697          *
698          * If the PE is switching to frozen state for the
699          * first time, to dump the PHB diag-data.
700          */
701         if (!(result & EEH_STATE_NOT_SUPPORT) &&
702             !(result & EEH_STATE_UNAVAILABLE) &&
703             !(result & EEH_STATE_MMIO_ACTIVE) &&
704             !(result & EEH_STATE_DMA_ACTIVE)  &&
705             !(pe->state & EEH_PE_ISOLATED)) {
706                 if (phb->freeze_pe)
707                         phb->freeze_pe(phb, pe->addr);
708 
709                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
710                 pnv_eeh_get_phb_diag(pe);
711 
712                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
713                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
714         }
715 
716         return result;
717 }
718 
719 /**
720  * pnv_eeh_get_state - Retrieve PE state
721  * @pe: EEH PE
722  * @delay: delay while PE state is temporarily unavailable
723  *
724  * Retrieve the state of the specified PE. For IODA-compitable
725  * platform, it should be retrieved from IODA table. Therefore,
726  * we prefer passing down to hardware implementation to handle
727  * it.
728  */
729 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
730 {
731         int ret;
732 
733         if (pe->type & EEH_PE_PHB)
734                 ret = pnv_eeh_get_phb_state(pe);
735         else
736                 ret = pnv_eeh_get_pe_state(pe);
737 
738         if (!delay)
739                 return ret;
740 
741         /*
742          * If the PE state is temporarily unavailable,
743          * to inform the EEH core delay for default
744          * period (1 second)
745          */
746         *delay = 0;
747         if (ret & EEH_STATE_UNAVAILABLE)
748                 *delay = 1000;
749 
750         return ret;
751 }
752 
753 static s64 pnv_eeh_poll(unsigned long id)
754 {
755         s64 rc = OPAL_HARDWARE;
756 
757         while (1) {
758                 rc = opal_pci_poll(id);
759                 if (rc <= 0)
760                         break;
761 
762                 if (system_state < SYSTEM_RUNNING)
763                         udelay(1000 * rc);
764                 else
765                         msleep(rc);
766         }
767 
768         return rc;
769 }
770 
771 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
772 {
773         struct pnv_phb *phb = hose->private_data;
774         s64 rc = OPAL_HARDWARE;
775 
776         pr_debug("%s: Reset PHB#%x, option=%d\n",
777                  __func__, hose->global_number, option);
778 
779         /* Issue PHB complete reset request */
780         if (option == EEH_RESET_FUNDAMENTAL ||
781             option == EEH_RESET_HOT)
782                 rc = opal_pci_reset(phb->opal_id,
783                                     OPAL_RESET_PHB_COMPLETE,
784                                     OPAL_ASSERT_RESET);
785         else if (option == EEH_RESET_DEACTIVATE)
786                 rc = opal_pci_reset(phb->opal_id,
787                                     OPAL_RESET_PHB_COMPLETE,
788                                     OPAL_DEASSERT_RESET);
789         if (rc < 0)
790                 goto out;
791 
792         /*
793          * Poll state of the PHB until the request is done
794          * successfully. The PHB reset is usually PHB complete
795          * reset followed by hot reset on root bus. So we also
796          * need the PCI bus settlement delay.
797          */
798         if (rc > 0)
799                 rc = pnv_eeh_poll(phb->opal_id);
800         if (option == EEH_RESET_DEACTIVATE) {
801                 if (system_state < SYSTEM_RUNNING)
802                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
803                 else
804                         msleep(EEH_PE_RST_SETTLE_TIME);
805         }
806 out:
807         if (rc != OPAL_SUCCESS)
808                 return -EIO;
809 
810         return 0;
811 }
812 
813 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
814 {
815         struct pnv_phb *phb = hose->private_data;
816         s64 rc = OPAL_HARDWARE;
817 
818         pr_debug("%s: Reset PHB#%x, option=%d\n",
819                  __func__, hose->global_number, option);
820 
821         /*
822          * During the reset deassert time, we needn't care
823          * the reset scope because the firmware does nothing
824          * for fundamental or hot reset during deassert phase.
825          */
826         if (option == EEH_RESET_FUNDAMENTAL)
827                 rc = opal_pci_reset(phb->opal_id,
828                                     OPAL_RESET_PCI_FUNDAMENTAL,
829                                     OPAL_ASSERT_RESET);
830         else if (option == EEH_RESET_HOT)
831                 rc = opal_pci_reset(phb->opal_id,
832                                     OPAL_RESET_PCI_HOT,
833                                     OPAL_ASSERT_RESET);
834         else if (option == EEH_RESET_DEACTIVATE)
835                 rc = opal_pci_reset(phb->opal_id,
836                                     OPAL_RESET_PCI_HOT,
837                                     OPAL_DEASSERT_RESET);
838         if (rc < 0)
839                 goto out;
840 
841         /* Poll state of the PHB until the request is done */
842         if (rc > 0)
843                 rc = pnv_eeh_poll(phb->opal_id);
844         if (option == EEH_RESET_DEACTIVATE)
845                 msleep(EEH_PE_RST_SETTLE_TIME);
846 out:
847         if (rc != OPAL_SUCCESS)
848                 return -EIO;
849 
850         return 0;
851 }
852 
853 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
854 {
855         struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
856         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
857         int aer = edev ? edev->aer_cap : 0;
858         u32 ctrl;
859 
860         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
861                  __func__, pci_domain_nr(dev->bus),
862                  dev->bus->number, option);
863 
864         switch (option) {
865         case EEH_RESET_FUNDAMENTAL:
866         case EEH_RESET_HOT:
867                 /* Don't report linkDown event */
868                 if (aer) {
869                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
870                                              4, &ctrl);
871                         ctrl |= PCI_ERR_UNC_SURPDN;
872                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
873                                               4, ctrl);
874                 }
875 
876                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
877                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
878                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
879 
880                 msleep(EEH_PE_RST_HOLD_TIME);
881                 break;
882         case EEH_RESET_DEACTIVATE:
883                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
884                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
885                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
886 
887                 msleep(EEH_PE_RST_SETTLE_TIME);
888 
889                 /* Continue reporting linkDown event */
890                 if (aer) {
891                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
892                                              4, &ctrl);
893                         ctrl &= ~PCI_ERR_UNC_SURPDN;
894                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
895                                               4, ctrl);
896                 }
897 
898                 break;
899         }
900 
901         return 0;
902 }
903 
904 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
905 {
906         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
907         struct pnv_phb *phb = hose->private_data;
908         struct device_node *dn = pci_device_to_OF_node(pdev);
909         uint64_t id = PCI_SLOT_ID(phb->opal_id,
910                                   (pdev->bus->number << 8) | pdev->devfn);
911         uint8_t scope;
912         int64_t rc;
913 
914         /* Hot reset to the bus if firmware cannot handle */
915         if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
916                 return __pnv_eeh_bridge_reset(pdev, option);
917 
918         switch (option) {
919         case EEH_RESET_FUNDAMENTAL:
920                 scope = OPAL_RESET_PCI_FUNDAMENTAL;
921                 break;
922         case EEH_RESET_HOT:
923                 scope = OPAL_RESET_PCI_HOT;
924                 break;
925         case EEH_RESET_DEACTIVATE:
926                 return 0;
927         default:
928                 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
929                         __func__, option);
930                 return -EINVAL;
931         }
932 
933         rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
934         if (rc <= OPAL_SUCCESS)
935                 goto out;
936 
937         rc = pnv_eeh_poll(id);
938 out:
939         return (rc == OPAL_SUCCESS) ? 0 : -EIO;
940 }
941 
942 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
943 {
944         struct pci_controller *hose;
945 
946         if (pci_is_root_bus(dev->bus)) {
947                 hose = pci_bus_to_host(dev->bus);
948                 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
949                 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
950         } else {
951                 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
952                 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
953         }
954 }
955 
956 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
957                                      int pos, u16 mask)
958 {
959         int i, status = 0;
960 
961         /* Wait for Transaction Pending bit to be cleared */
962         for (i = 0; i < 4; i++) {
963                 eeh_ops->read_config(pdn, pos, 2, &status);
964                 if (!(status & mask))
965                         return;
966 
967                 msleep((1 << i) * 100);
968         }
969 
970         pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
971                 __func__, type,
972                 pdn->phb->global_number, pdn->busno,
973                 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
974 }
975 
976 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
977 {
978         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
979         u32 reg = 0;
980 
981         if (WARN_ON(!edev->pcie_cap))
982                 return -ENOTTY;
983 
984         eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
985         if (!(reg & PCI_EXP_DEVCAP_FLR))
986                 return -ENOTTY;
987 
988         switch (option) {
989         case EEH_RESET_HOT:
990         case EEH_RESET_FUNDAMENTAL:
991                 pnv_eeh_wait_for_pending(pdn, "",
992                                          edev->pcie_cap + PCI_EXP_DEVSTA,
993                                          PCI_EXP_DEVSTA_TRPND);
994                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
995                                      4, &reg);
996                 reg |= PCI_EXP_DEVCTL_BCR_FLR;
997                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
998                                       4, reg);
999                 msleep(EEH_PE_RST_HOLD_TIME);
1000                 break;
1001         case EEH_RESET_DEACTIVATE:
1002                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1003                                      4, &reg);
1004                 reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
1005                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1006                                       4, reg);
1007                 msleep(EEH_PE_RST_SETTLE_TIME);
1008                 break;
1009         }
1010 
1011         return 0;
1012 }
1013 
1014 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
1015 {
1016         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1017         u32 cap = 0;
1018 
1019         if (WARN_ON(!edev->af_cap))
1020                 return -ENOTTY;
1021 
1022         eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
1023         if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
1024                 return -ENOTTY;
1025 
1026         switch (option) {
1027         case EEH_RESET_HOT:
1028         case EEH_RESET_FUNDAMENTAL:
1029                 /*
1030                  * Wait for Transaction Pending bit to clear. A word-aligned
1031                  * test is used, so we use the conrol offset rather than status
1032                  * and shift the test bit to match.
1033                  */
1034                 pnv_eeh_wait_for_pending(pdn, "AF",
1035                                          edev->af_cap + PCI_AF_CTRL,
1036                                          PCI_AF_STATUS_TP << 8);
1037                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
1038                                       1, PCI_AF_CTRL_FLR);
1039                 msleep(EEH_PE_RST_HOLD_TIME);
1040                 break;
1041         case EEH_RESET_DEACTIVATE:
1042                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
1043                 msleep(EEH_PE_RST_SETTLE_TIME);
1044                 break;
1045         }
1046 
1047         return 0;
1048 }
1049 
1050 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
1051 {
1052         struct eeh_dev *edev;
1053         struct pci_dn *pdn;
1054         int ret;
1055 
1056         /* The VF PE should have only one child device */
1057         edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
1058         pdn = eeh_dev_to_pdn(edev);
1059         if (!pdn)
1060                 return -ENXIO;
1061 
1062         ret = pnv_eeh_do_flr(pdn, option);
1063         if (!ret)
1064                 return ret;
1065 
1066         return pnv_eeh_do_af_flr(pdn, option);
1067 }
1068 
1069 /**
1070  * pnv_eeh_reset - Reset the specified PE
1071  * @pe: EEH PE
1072  * @option: reset option
1073  *
1074  * Do reset on the indicated PE. For PCI bus sensitive PE,
1075  * we need to reset the parent p2p bridge. The PHB has to
1076  * be reinitialized if the p2p bridge is root bridge. For
1077  * PCI device sensitive PE, we will try to reset the device
1078  * through FLR. For now, we don't have OPAL APIs to do HARD
1079  * reset yet, so all reset would be SOFT (HOT) reset.
1080  */
1081 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1082 {
1083         struct pci_controller *hose = pe->phb;
1084         struct pnv_phb *phb;
1085         struct pci_bus *bus;
1086         int64_t rc;
1087 
1088         /*
1089          * For PHB reset, we always have complete reset. For those PEs whose
1090          * primary bus derived from root complex (root bus) or root port
1091          * (usually bus#1), we apply hot or fundamental reset on the root port.
1092          * For other PEs, we always have hot reset on the PE primary bus.
1093          *
1094          * Here, we have different design to pHyp, which always clear the
1095          * frozen state during PE reset. However, the good idea here from
1096          * benh is to keep frozen state before we get PE reset done completely
1097          * (until BAR restore). With the frozen state, HW drops illegal IO
1098          * or MMIO access, which can incur recrusive frozen PE during PE
1099          * reset. The side effect is that EEH core has to clear the frozen
1100          * state explicitly after BAR restore.
1101          */
1102         if (pe->type & EEH_PE_PHB)
1103                 return pnv_eeh_phb_reset(hose, option);
1104 
1105         /*
1106          * The frozen PE might be caused by PAPR error injection
1107          * registers, which are expected to be cleared after hitting
1108          * frozen PE as stated in the hardware spec. Unfortunately,
1109          * that's not true on P7IOC. So we have to clear it manually
1110          * to avoid recursive EEH errors during recovery.
1111          */
1112         phb = hose->private_data;
1113         if (phb->model == PNV_PHB_MODEL_P7IOC &&
1114             (option == EEH_RESET_HOT ||
1115              option == EEH_RESET_FUNDAMENTAL)) {
1116                 rc = opal_pci_reset(phb->opal_id,
1117                                     OPAL_RESET_PHB_ERROR,
1118                                     OPAL_ASSERT_RESET);
1119                 if (rc != OPAL_SUCCESS) {
1120                         pr_warn("%s: Failure %lld clearing error injection registers\n",
1121                                 __func__, rc);
1122                         return -EIO;
1123                 }
1124         }
1125 
1126         if (pe->type & EEH_PE_VF)
1127                 return pnv_eeh_reset_vf_pe(pe, option);
1128 
1129         bus = eeh_pe_bus_get(pe);
1130         if (!bus) {
1131                 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n",
1132                         __func__, pe->phb->global_number, pe->addr);
1133                 return -EIO;
1134         }
1135 
1136         /*
1137          * If dealing with the root bus (or the bus underneath the
1138          * root port), we reset the bus underneath the root port.
1139          *
1140          * The cxl driver depends on this behaviour for bi-modal card
1141          * switching.
1142          */
1143         if (pci_is_root_bus(bus) ||
1144             pci_is_root_bus(bus->parent))
1145                 return pnv_eeh_root_reset(hose, option);
1146 
1147         return pnv_eeh_bridge_reset(bus->self, option);
1148 }
1149 
1150 /**
1151  * pnv_eeh_wait_state - Wait for PE state
1152  * @pe: EEH PE
1153  * @max_wait: maximal period in millisecond
1154  *
1155  * Wait for the state of associated PE. It might take some time
1156  * to retrieve the PE's state.
1157  */
1158 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
1159 {
1160         int ret;
1161         int mwait;
1162 
1163         while (1) {
1164                 ret = pnv_eeh_get_state(pe, &mwait);
1165 
1166                 /*
1167                  * If the PE's state is temporarily unavailable,
1168                  * we have to wait for the specified time. Otherwise,
1169                  * the PE's state will be returned immediately.
1170                  */
1171                 if (ret != EEH_STATE_UNAVAILABLE)
1172                         return ret;
1173 
1174                 if (max_wait <= 0) {
1175                         pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
1176                                 __func__, pe->addr, max_wait);
1177                         return EEH_STATE_NOT_SUPPORT;
1178                 }
1179 
1180                 max_wait -= mwait;
1181                 msleep(mwait);
1182         }
1183 
1184         return EEH_STATE_NOT_SUPPORT;
1185 }
1186 
1187 /**
1188  * pnv_eeh_get_log - Retrieve error log
1189  * @pe: EEH PE
1190  * @severity: temporary or permanent error log
1191  * @drv_log: driver log to be combined with retrieved error log
1192  * @len: length of driver log
1193  *
1194  * Retrieve the temporary or permanent error from the PE.
1195  */
1196 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1197                            char *drv_log, unsigned long len)
1198 {
1199         if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1200                 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1201 
1202         return 0;
1203 }
1204 
1205 /**
1206  * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1207  * @pe: EEH PE
1208  *
1209  * The function will be called to reconfigure the bridges included
1210  * in the specified PE so that the mulfunctional PE would be recovered
1211  * again.
1212  */
1213 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1214 {
1215         return 0;
1216 }
1217 
1218 /**
1219  * pnv_pe_err_inject - Inject specified error to the indicated PE
1220  * @pe: the indicated PE
1221  * @type: error type
1222  * @func: specific error type
1223  * @addr: address
1224  * @mask: address mask
1225  *
1226  * The routine is called to inject specified error, which is
1227  * determined by @type and @func, to the indicated PE for
1228  * testing purpose.
1229  */
1230 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1231                               unsigned long addr, unsigned long mask)
1232 {
1233         struct pci_controller *hose = pe->phb;
1234         struct pnv_phb *phb = hose->private_data;
1235         s64 rc;
1236 
1237         if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1238             type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1239                 pr_warn("%s: Invalid error type %d\n",
1240                         __func__, type);
1241                 return -ERANGE;
1242         }
1243 
1244         if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1245             func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1246                 pr_warn("%s: Invalid error function %d\n",
1247                         __func__, func);
1248                 return -ERANGE;
1249         }
1250 
1251         /* Firmware supports error injection ? */
1252         if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1253                 pr_warn("%s: Firmware doesn't support error injection\n",
1254                         __func__);
1255                 return -ENXIO;
1256         }
1257 
1258         /* Do error injection */
1259         rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1260                                  type, func, addr, mask);
1261         if (rc != OPAL_SUCCESS) {
1262                 pr_warn("%s: Failure %lld injecting error "
1263                         "%d-%d to PHB#%x-PE#%x\n",
1264                         __func__, rc, type, func,
1265                         hose->global_number, pe->addr);
1266                 return -EIO;
1267         }
1268 
1269         return 0;
1270 }
1271 
1272 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1273 {
1274         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1275 
1276         if (!edev || !edev->pe)
1277                 return false;
1278 
1279         /*
1280          * We will issue FLR or AF FLR to all VFs, which are contained
1281          * in VF PE. It relies on the EEH PCI config accessors. So we
1282          * can't block them during the window.
1283          */
1284         if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1285                 return false;
1286 
1287         if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1288                 return true;
1289 
1290         return false;
1291 }
1292 
1293 static int pnv_eeh_read_config(struct pci_dn *pdn,
1294                                int where, int size, u32 *val)
1295 {
1296         if (!pdn)
1297                 return PCIBIOS_DEVICE_NOT_FOUND;
1298 
1299         if (pnv_eeh_cfg_blocked(pdn)) {
1300                 *val = 0xFFFFFFFF;
1301                 return PCIBIOS_SET_FAILED;
1302         }
1303 
1304         return pnv_pci_cfg_read(pdn, where, size, val);
1305 }
1306 
1307 static int pnv_eeh_write_config(struct pci_dn *pdn,
1308                                 int where, int size, u32 val)
1309 {
1310         if (!pdn)
1311                 return PCIBIOS_DEVICE_NOT_FOUND;
1312 
1313         if (pnv_eeh_cfg_blocked(pdn))
1314                 return PCIBIOS_SET_FAILED;
1315 
1316         return pnv_pci_cfg_write(pdn, where, size, val);
1317 }
1318 
1319 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1320 {
1321         /* GEM */
1322         if (data->gemXfir || data->gemRfir ||
1323             data->gemRirqfir || data->gemMask || data->gemRwof)
1324                 pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1325                         be64_to_cpu(data->gemXfir),
1326                         be64_to_cpu(data->gemRfir),
1327                         be64_to_cpu(data->gemRirqfir),
1328                         be64_to_cpu(data->gemMask),
1329                         be64_to_cpu(data->gemRwof));
1330 
1331         /* LEM */
1332         if (data->lemFir || data->lemErrMask ||
1333             data->lemAction0 || data->lemAction1 || data->lemWof)
1334                 pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1335                         be64_to_cpu(data->lemFir),
1336                         be64_to_cpu(data->lemErrMask),
1337                         be64_to_cpu(data->lemAction0),
1338                         be64_to_cpu(data->lemAction1),
1339                         be64_to_cpu(data->lemWof));
1340 }
1341 
1342 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1343 {
1344         struct pnv_phb *phb = hose->private_data;
1345         struct OpalIoP7IOCErrorData *data =
1346                 (struct OpalIoP7IOCErrorData*)phb->diag_data;
1347         long rc;
1348 
1349         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1350         if (rc != OPAL_SUCCESS) {
1351                 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1352                         __func__, phb->hub_id, rc);
1353                 return;
1354         }
1355 
1356         switch (be16_to_cpu(data->type)) {
1357         case OPAL_P7IOC_DIAG_TYPE_RGC:
1358                 pr_info("P7IOC diag-data for RGC\n\n");
1359                 pnv_eeh_dump_hub_diag_common(data);
1360                 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1361                         pr_info("  RGC: %016llx %016llx\n",
1362                                 be64_to_cpu(data->rgc.rgcStatus),
1363                                 be64_to_cpu(data->rgc.rgcLdcp));
1364                 break;
1365         case OPAL_P7IOC_DIAG_TYPE_BI:
1366                 pr_info("P7IOC diag-data for BI %s\n\n",
1367                         data->bi.biDownbound ? "Downbound" : "Upbound");
1368                 pnv_eeh_dump_hub_diag_common(data);
1369                 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1370                     data->bi.biLdcp2 || data->bi.biFenceStatus)
1371                         pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1372                                 be64_to_cpu(data->bi.biLdcp0),
1373                                 be64_to_cpu(data->bi.biLdcp1),
1374                                 be64_to_cpu(data->bi.biLdcp2),
1375                                 be64_to_cpu(data->bi.biFenceStatus));
1376                 break;
1377         case OPAL_P7IOC_DIAG_TYPE_CI:
1378                 pr_info("P7IOC diag-data for CI Port %d\n\n",
1379                         data->ci.ciPort);
1380                 pnv_eeh_dump_hub_diag_common(data);
1381                 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1382                         pr_info("  CI:  %016llx %016llx\n",
1383                                 be64_to_cpu(data->ci.ciPortStatus),
1384                                 be64_to_cpu(data->ci.ciPortLdcp));
1385                 break;
1386         case OPAL_P7IOC_DIAG_TYPE_MISC:
1387                 pr_info("P7IOC diag-data for MISC\n\n");
1388                 pnv_eeh_dump_hub_diag_common(data);
1389                 break;
1390         case OPAL_P7IOC_DIAG_TYPE_I2C:
1391                 pr_info("P7IOC diag-data for I2C\n\n");
1392                 pnv_eeh_dump_hub_diag_common(data);
1393                 break;
1394         default:
1395                 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1396                         __func__, phb->hub_id, data->type);
1397         }
1398 }
1399 
1400 static int pnv_eeh_get_pe(struct pci_controller *hose,
1401                           u16 pe_no, struct eeh_pe **pe)
1402 {
1403         struct pnv_phb *phb = hose->private_data;
1404         struct pnv_ioda_pe *pnv_pe;
1405         struct eeh_pe *dev_pe;
1406 
1407         /*
1408          * If PHB supports compound PE, to fetch
1409          * the master PE because slave PE is invisible
1410          * to EEH core.
1411          */
1412         pnv_pe = &phb->ioda.pe_array[pe_no];
1413         if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1414                 pnv_pe = pnv_pe->master;
1415                 WARN_ON(!pnv_pe ||
1416                         !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1417                 pe_no = pnv_pe->pe_number;
1418         }
1419 
1420         /* Find the PE according to PE# */
1421         dev_pe = eeh_pe_get(hose, pe_no, 0);
1422         if (!dev_pe)
1423                 return -EEXIST;
1424 
1425         /* Freeze the (compound) PE */
1426         *pe = dev_pe;
1427         if (!(dev_pe->state & EEH_PE_ISOLATED))
1428                 phb->freeze_pe(phb, pe_no);
1429 
1430         /*
1431          * At this point, we're sure the (compound) PE should
1432          * have been frozen. However, we still need poke until
1433          * hitting the frozen PE on top level.
1434          */
1435         dev_pe = dev_pe->parent;
1436         while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1437                 int ret;
1438                 ret = eeh_ops->get_state(dev_pe, NULL);
1439                 if (ret <= 0 || eeh_state_active(ret)) {
1440                         dev_pe = dev_pe->parent;
1441                         continue;
1442                 }
1443 
1444                 /* Frozen parent PE */
1445                 *pe = dev_pe;
1446                 if (!(dev_pe->state & EEH_PE_ISOLATED))
1447                         phb->freeze_pe(phb, dev_pe->addr);
1448 
1449                 /* Next one */
1450                 dev_pe = dev_pe->parent;
1451         }
1452 
1453         return 0;
1454 }
1455 
1456 /**
1457  * pnv_eeh_next_error - Retrieve next EEH error to handle
1458  * @pe: Affected PE
1459  *
1460  * The function is expected to be called by EEH core while it gets
1461  * special EEH event (without binding PE). The function calls to
1462  * OPAL APIs for next error to handle. The informational error is
1463  * handled internally by platform. However, the dead IOC, dead PHB,
1464  * fenced PHB and frozen PE should be handled by EEH core eventually.
1465  */
1466 static int pnv_eeh_next_error(struct eeh_pe **pe)
1467 {
1468         struct pci_controller *hose;
1469         struct pnv_phb *phb;
1470         struct eeh_pe *phb_pe, *parent_pe;
1471         __be64 frozen_pe_no;
1472         __be16 err_type, severity;
1473         long rc;
1474         int state, ret = EEH_NEXT_ERR_NONE;
1475 
1476         /*
1477          * While running here, it's safe to purge the event queue. The
1478          * event should still be masked.
1479          */
1480         eeh_remove_event(NULL, false);
1481 
1482         list_for_each_entry(hose, &hose_list, list_node) {
1483                 /*
1484                  * If the subordinate PCI buses of the PHB has been
1485                  * removed or is exactly under error recovery, we
1486                  * needn't take care of it any more.
1487                  */
1488                 phb = hose->private_data;
1489                 phb_pe = eeh_phb_pe_get(hose);
1490                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1491                         continue;
1492 
1493                 rc = opal_pci_next_error(phb->opal_id,
1494                                          &frozen_pe_no, &err_type, &severity);
1495                 if (rc != OPAL_SUCCESS) {
1496                         pr_devel("%s: Invalid return value on "
1497                                  "PHB#%x (0x%lx) from opal_pci_next_error",
1498                                  __func__, hose->global_number, rc);
1499                         continue;
1500                 }
1501 
1502                 /* If the PHB doesn't have error, stop processing */
1503                 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1504                     be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1505                         pr_devel("%s: No error found on PHB#%x\n",
1506                                  __func__, hose->global_number);
1507                         continue;
1508                 }
1509 
1510                 /*
1511                  * Processing the error. We're expecting the error with
1512                  * highest priority reported upon multiple errors on the
1513                  * specific PHB.
1514                  */
1515                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1516                         __func__, be16_to_cpu(err_type),
1517                         be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1518                         hose->global_number);
1519                 switch (be16_to_cpu(err_type)) {
1520                 case OPAL_EEH_IOC_ERROR:
1521                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1522                                 pr_err("EEH: dead IOC detected\n");
1523                                 ret = EEH_NEXT_ERR_DEAD_IOC;
1524                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1525                                 pr_info("EEH: IOC informative error "
1526                                         "detected\n");
1527                                 pnv_eeh_get_and_dump_hub_diag(hose);
1528                                 ret = EEH_NEXT_ERR_NONE;
1529                         }
1530 
1531                         break;
1532                 case OPAL_EEH_PHB_ERROR:
1533                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1534                                 *pe = phb_pe;
1535                                 pr_err("EEH: dead PHB#%x detected, "
1536                                        "location: %s\n",
1537                                         hose->global_number,
1538                                         eeh_pe_loc_get(phb_pe));
1539                                 ret = EEH_NEXT_ERR_DEAD_PHB;
1540                         } else if (be16_to_cpu(severity) ==
1541                                    OPAL_EEH_SEV_PHB_FENCED) {
1542                                 *pe = phb_pe;
1543                                 pr_err("EEH: Fenced PHB#%x detected, "
1544                                        "location: %s\n",
1545                                         hose->global_number,
1546                                         eeh_pe_loc_get(phb_pe));
1547                                 ret = EEH_NEXT_ERR_FENCED_PHB;
1548                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1549                                 pr_info("EEH: PHB#%x informative error "
1550                                         "detected, location: %s\n",
1551                                         hose->global_number,
1552                                         eeh_pe_loc_get(phb_pe));
1553                                 pnv_eeh_get_phb_diag(phb_pe);
1554                                 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1555                                 ret = EEH_NEXT_ERR_NONE;
1556                         }
1557 
1558                         break;
1559                 case OPAL_EEH_PE_ERROR:
1560                         /*
1561                          * If we can't find the corresponding PE, we
1562                          * just try to unfreeze.
1563                          */
1564                         if (pnv_eeh_get_pe(hose,
1565                                 be64_to_cpu(frozen_pe_no), pe)) {
1566                                 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1567                                         hose->global_number, be64_to_cpu(frozen_pe_no));
1568                                 pr_info("EEH: PHB location: %s\n",
1569                                         eeh_pe_loc_get(phb_pe));
1570 
1571                                 /* Dump PHB diag-data */
1572                                 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1573                                         phb->diag_data, phb->diag_data_size);
1574                                 if (rc == OPAL_SUCCESS)
1575                                         pnv_pci_dump_phb_diag_data(hose,
1576                                                         phb->diag_data);
1577 
1578                                 /* Try best to clear it */
1579                                 opal_pci_eeh_freeze_clear(phb->opal_id,
1580                                         be64_to_cpu(frozen_pe_no),
1581                                         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1582                                 ret = EEH_NEXT_ERR_NONE;
1583                         } else if ((*pe)->state & EEH_PE_ISOLATED ||
1584                                    eeh_pe_passed(*pe)) {
1585                                 ret = EEH_NEXT_ERR_NONE;
1586                         } else {
1587                                 pr_err("EEH: Frozen PE#%x "
1588                                        "on PHB#%x detected\n",
1589                                        (*pe)->addr,
1590                                         (*pe)->phb->global_number);
1591                                 pr_err("EEH: PE location: %s, "
1592                                        "PHB location: %s\n",
1593                                        eeh_pe_loc_get(*pe),
1594                                        eeh_pe_loc_get(phb_pe));
1595                                 ret = EEH_NEXT_ERR_FROZEN_PE;
1596                         }
1597 
1598                         break;
1599                 default:
1600                         pr_warn("%s: Unexpected error type %d\n",
1601                                 __func__, be16_to_cpu(err_type));
1602                 }
1603 
1604                 /*
1605                  * EEH core will try recover from fenced PHB or
1606                  * frozen PE. In the time for frozen PE, EEH core
1607                  * enable IO path for that before collecting logs,
1608                  * but it ruins the site. So we have to dump the
1609                  * log in advance here.
1610                  */
1611                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1612                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
1613                     !((*pe)->state & EEH_PE_ISOLATED)) {
1614                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1615                         pnv_eeh_get_phb_diag(*pe);
1616 
1617                         if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1618                                 pnv_pci_dump_phb_diag_data((*pe)->phb,
1619                                                            (*pe)->data);
1620                 }
1621 
1622                 /*
1623                  * We probably have the frozen parent PE out there and
1624                  * we need have to handle frozen parent PE firstly.
1625                  */
1626                 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1627                         parent_pe = (*pe)->parent;
1628                         while (parent_pe) {
1629                                 /* Hit the ceiling ? */
1630                                 if (parent_pe->type & EEH_PE_PHB)
1631                                         break;
1632 
1633                                 /* Frozen parent PE ? */
1634                                 state = eeh_ops->get_state(parent_pe, NULL);
1635                                 if (state > 0 && !eeh_state_active(state))
1636                                         *pe = parent_pe;
1637 
1638                                 /* Next parent level */
1639                                 parent_pe = parent_pe->parent;
1640                         }
1641 
1642                         /* We possibly migrate to another PE */
1643                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1644                 }
1645 
1646                 /*
1647                  * If we have no errors on the specific PHB or only
1648                  * informative error there, we continue poking it.
1649                  * Otherwise, we need actions to be taken by upper
1650                  * layer.
1651                  */
1652                 if (ret > EEH_NEXT_ERR_INF)
1653                         break;
1654         }
1655 
1656         /* Unmask the event */
1657         if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1658                 enable_irq(eeh_event_irq);
1659 
1660         return ret;
1661 }
1662 
1663 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1664 {
1665         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1666         struct pnv_phb *phb;
1667         s64 ret = 0;
1668         int config_addr = (pdn->busno << 8) | (pdn->devfn);
1669 
1670         if (!edev)
1671                 return -EEXIST;
1672 
1673         /*
1674          * We have to restore the PCI config space after reset since the
1675          * firmware can't see SRIOV VFs.
1676          *
1677          * FIXME: The MPS, error routing rules, timeout setting are worthy
1678          * to be exported by firmware in extendible way.
1679          */
1680         if (edev->physfn) {
1681                 ret = eeh_restore_vf_config(pdn);
1682         } else {
1683                 phb = pdn->phb->private_data;
1684                 ret = opal_pci_reinit(phb->opal_id,
1685                                       OPAL_REINIT_PCI_DEV, config_addr);
1686         }
1687 
1688         if (ret) {
1689                 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1690                         __func__, config_addr, ret);
1691                 return -EIO;
1692         }
1693 
1694         return ret;
1695 }
1696 
1697 static struct eeh_ops pnv_eeh_ops = {
1698         .name                   = "powernv",
1699         .init                   = pnv_eeh_init,
1700         .probe                  = pnv_eeh_probe,
1701         .set_option             = pnv_eeh_set_option,
1702         .get_pe_addr            = pnv_eeh_get_pe_addr,
1703         .get_state              = pnv_eeh_get_state,
1704         .reset                  = pnv_eeh_reset,
1705         .wait_state             = pnv_eeh_wait_state,
1706         .get_log                = pnv_eeh_get_log,
1707         .configure_bridge       = pnv_eeh_configure_bridge,
1708         .err_inject             = pnv_eeh_err_inject,
1709         .read_config            = pnv_eeh_read_config,
1710         .write_config           = pnv_eeh_write_config,
1711         .next_error             = pnv_eeh_next_error,
1712         .restore_config         = pnv_eeh_restore_config,
1713         .notify_resume          = NULL
1714 };
1715 
1716 #ifdef CONFIG_PCI_IOV
1717 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
1718 {
1719         struct pci_dn *pdn = pci_get_pdn(pdev);
1720         int parent_mps;
1721 
1722         if (!pdev->is_virtfn)
1723                 return;
1724 
1725         /* Synchronize MPS for VF and PF */
1726         parent_mps = pcie_get_mps(pdev->physfn);
1727         if ((128 << pdev->pcie_mpss) >= parent_mps)
1728                 pcie_set_mps(pdev, parent_mps);
1729         pdn->mps = pcie_get_mps(pdev);
1730 }
1731 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
1732 #endif /* CONFIG_PCI_IOV */
1733 
1734 /**
1735  * eeh_powernv_init - Register platform dependent EEH operations
1736  *
1737  * EEH initialization on powernv platform. This function should be
1738  * called before any EEH related functions.
1739  */
1740 static int __init eeh_powernv_init(void)
1741 {
1742         int ret = -EINVAL;
1743 
1744         ret = eeh_ops_register(&pnv_eeh_ops);
1745         if (!ret)
1746                 pr_info("EEH: PowerNV platform initialized\n");
1747         else
1748                 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1749 
1750         return ret;
1751 }
1752 machine_early_initcall(powernv, eeh_powernv_init);
1753 

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