~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/powerpc/platforms/powernv/eeh-powernv.c

Version: ~ [ linux-5.12-rc1 ] ~ [ linux-5.11.2 ] ~ [ linux-5.10.19 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.101 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.177 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.222 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.258 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.258 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.18.140 ] ~ [ linux-3.16.85 ] ~ [ linux-3.14.79 ] ~ [ linux-3.12.74 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * The file intends to implement the platform dependent EEH operations on
  3  * powernv platform. Actually, the powernv was created in order to fully
  4  * hypervisor support.
  5  *
  6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  */
 13 
 14 #include <linux/atomic.h>
 15 #include <linux/debugfs.h>
 16 #include <linux/delay.h>
 17 #include <linux/export.h>
 18 #include <linux/init.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/list.h>
 21 #include <linux/msi.h>
 22 #include <linux/of.h>
 23 #include <linux/pci.h>
 24 #include <linux/proc_fs.h>
 25 #include <linux/rbtree.h>
 26 #include <linux/sched.h>
 27 #include <linux/seq_file.h>
 28 #include <linux/spinlock.h>
 29 
 30 #include <asm/eeh.h>
 31 #include <asm/eeh_event.h>
 32 #include <asm/firmware.h>
 33 #include <asm/io.h>
 34 #include <asm/iommu.h>
 35 #include <asm/machdep.h>
 36 #include <asm/msi_bitmap.h>
 37 #include <asm/opal.h>
 38 #include <asm/ppc-pci.h>
 39 #include <asm/pnv-pci.h>
 40 
 41 #include "powernv.h"
 42 #include "pci.h"
 43 
 44 static bool pnv_eeh_nb_init = false;
 45 static int eeh_event_irq = -EINVAL;
 46 
 47 static int pnv_eeh_init(void)
 48 {
 49         struct pci_controller *hose;
 50         struct pnv_phb *phb;
 51 
 52         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 53                 pr_warn("%s: OPAL is required !\n",
 54                         __func__);
 55                 return -EINVAL;
 56         }
 57 
 58         /* Set probe mode */
 59         eeh_add_flag(EEH_PROBE_MODE_DEV);
 60 
 61         /*
 62          * P7IOC blocks PCI config access to frozen PE, but PHB3
 63          * doesn't do that. So we have to selectively enable I/O
 64          * prior to collecting error log.
 65          */
 66         list_for_each_entry(hose, &hose_list, list_node) {
 67                 phb = hose->private_data;
 68 
 69                 if (phb->model == PNV_PHB_MODEL_P7IOC)
 70                         eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
 71 
 72                 /*
 73                  * PE#0 should be regarded as valid by EEH core
 74                  * if it's not the reserved one. Currently, we
 75                  * have the reserved PE#255 and PE#127 for PHB3
 76                  * and P7IOC separately. So we should regard
 77                  * PE#0 as valid for PHB3 and P7IOC.
 78                  */
 79                 if (phb->ioda.reserved_pe_idx != 0)
 80                         eeh_add_flag(EEH_VALID_PE_ZERO);
 81 
 82                 break;
 83         }
 84 
 85         return 0;
 86 }
 87 
 88 static irqreturn_t pnv_eeh_event(int irq, void *data)
 89 {
 90         /*
 91          * We simply send a special EEH event if EEH has been
 92          * enabled. We don't care about EEH events until we've
 93          * finished processing the outstanding ones. Event processing
 94          * gets unmasked in next_error() if EEH is enabled.
 95          */
 96         disable_irq_nosync(irq);
 97 
 98         if (eeh_enabled())
 99                 eeh_send_failure_event(NULL);
100 
101         return IRQ_HANDLED;
102 }
103 
104 #ifdef CONFIG_DEBUG_FS
105 static ssize_t pnv_eeh_ei_write(struct file *filp,
106                                 const char __user *user_buf,
107                                 size_t count, loff_t *ppos)
108 {
109         struct pci_controller *hose = filp->private_data;
110         struct eeh_dev *edev;
111         struct eeh_pe *pe;
112         int pe_no, type, func;
113         unsigned long addr, mask;
114         char buf[50];
115         int ret;
116 
117         if (!eeh_ops || !eeh_ops->err_inject)
118                 return -ENXIO;
119 
120         /* Copy over argument buffer */
121         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
122         if (!ret)
123                 return -EFAULT;
124 
125         /* Retrieve parameters */
126         ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
127                      &pe_no, &type, &func, &addr, &mask);
128         if (ret != 5)
129                 return -EINVAL;
130 
131         /* Retrieve PE */
132         edev = kzalloc(sizeof(*edev), GFP_KERNEL);
133         if (!edev)
134                 return -ENOMEM;
135         edev->phb = hose;
136         edev->pe_config_addr = pe_no;
137         pe = eeh_pe_get(edev);
138         kfree(edev);
139         if (!pe)
140                 return -ENODEV;
141 
142         /* Do error injection */
143         ret = eeh_ops->err_inject(pe, type, func, addr, mask);
144         return ret < 0 ? ret : count;
145 }
146 
147 static const struct file_operations pnv_eeh_ei_fops = {
148         .open   = simple_open,
149         .llseek = no_llseek,
150         .write  = pnv_eeh_ei_write,
151 };
152 
153 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
154 {
155         struct pci_controller *hose = data;
156         struct pnv_phb *phb = hose->private_data;
157 
158         out_be64(phb->regs + offset, val);
159         return 0;
160 }
161 
162 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
163 {
164         struct pci_controller *hose = data;
165         struct pnv_phb *phb = hose->private_data;
166 
167         *val = in_be64(phb->regs + offset);
168         return 0;
169 }
170 
171 #define PNV_EEH_DBGFS_ENTRY(name, reg)                          \
172 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val)        \
173 {                                                               \
174         return pnv_eeh_dbgfs_set(data, reg, val);               \
175 }                                                               \
176                                                                 \
177 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val)       \
178 {                                                               \
179         return pnv_eeh_dbgfs_get(data, reg, val);               \
180 }                                                               \
181                                                                 \
182 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name,               \
183                         pnv_eeh_dbgfs_get_##name,               \
184                         pnv_eeh_dbgfs_set_##name,               \
185                         "0x%llx\n")
186 
187 PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
188 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
189 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
190 
191 #endif /* CONFIG_DEBUG_FS */
192 
193 /**
194  * pnv_eeh_post_init - EEH platform dependent post initialization
195  *
196  * EEH platform dependent post initialization on powernv. When
197  * the function is called, the EEH PEs and devices should have
198  * been built. If the I/O cache staff has been built, EEH is
199  * ready to supply service.
200  */
201 static int pnv_eeh_post_init(void)
202 {
203         struct pci_controller *hose;
204         struct pnv_phb *phb;
205         int ret = 0;
206 
207         /* Register OPAL event notifier */
208         if (!pnv_eeh_nb_init) {
209                 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
210                 if (eeh_event_irq < 0) {
211                         pr_err("%s: Can't register OPAL event interrupt (%d)\n",
212                                __func__, eeh_event_irq);
213                         return eeh_event_irq;
214                 }
215 
216                 ret = request_irq(eeh_event_irq, pnv_eeh_event,
217                                 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
218                 if (ret < 0) {
219                         irq_dispose_mapping(eeh_event_irq);
220                         pr_err("%s: Can't request OPAL event interrupt (%d)\n",
221                                __func__, eeh_event_irq);
222                         return ret;
223                 }
224 
225                 pnv_eeh_nb_init = true;
226         }
227 
228         if (!eeh_enabled())
229                 disable_irq(eeh_event_irq);
230 
231         list_for_each_entry(hose, &hose_list, list_node) {
232                 phb = hose->private_data;
233 
234                 /*
235                  * If EEH is enabled, we're going to rely on that.
236                  * Otherwise, we restore to conventional mechanism
237                  * to clear frozen PE during PCI config access.
238                  */
239                 if (eeh_enabled())
240                         phb->flags |= PNV_PHB_FLAG_EEH;
241                 else
242                         phb->flags &= ~PNV_PHB_FLAG_EEH;
243 
244                 /* Create debugfs entries */
245 #ifdef CONFIG_DEBUG_FS
246                 if (phb->has_dbgfs || !phb->dbgfs)
247                         continue;
248 
249                 phb->has_dbgfs = 1;
250                 debugfs_create_file("err_injct", 0200,
251                                     phb->dbgfs, hose,
252                                     &pnv_eeh_ei_fops);
253 
254                 debugfs_create_file("err_injct_outbound", 0600,
255                                     phb->dbgfs, hose,
256                                     &pnv_eeh_dbgfs_ops_outb);
257                 debugfs_create_file("err_injct_inboundA", 0600,
258                                     phb->dbgfs, hose,
259                                     &pnv_eeh_dbgfs_ops_inbA);
260                 debugfs_create_file("err_injct_inboundB", 0600,
261                                     phb->dbgfs, hose,
262                                     &pnv_eeh_dbgfs_ops_inbB);
263 #endif /* CONFIG_DEBUG_FS */
264         }
265 
266         return ret;
267 }
268 
269 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
270 {
271         int pos = PCI_CAPABILITY_LIST;
272         int cnt = 48;   /* Maximal number of capabilities */
273         u32 status, id;
274 
275         if (!pdn)
276                 return 0;
277 
278         /* Check if the device supports capabilities */
279         pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
280         if (!(status & PCI_STATUS_CAP_LIST))
281                 return 0;
282 
283         while (cnt--) {
284                 pnv_pci_cfg_read(pdn, pos, 1, &pos);
285                 if (pos < 0x40)
286                         break;
287 
288                 pos &= ~3;
289                 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
290                 if (id == 0xff)
291                         break;
292 
293                 /* Found */
294                 if (id == cap)
295                         return pos;
296 
297                 /* Next one */
298                 pos += PCI_CAP_LIST_NEXT;
299         }
300 
301         return 0;
302 }
303 
304 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
305 {
306         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
307         u32 header;
308         int pos = 256, ttl = (4096 - 256) / 8;
309 
310         if (!edev || !edev->pcie_cap)
311                 return 0;
312         if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
313                 return 0;
314         else if (!header)
315                 return 0;
316 
317         while (ttl-- > 0) {
318                 if (PCI_EXT_CAP_ID(header) == cap && pos)
319                         return pos;
320 
321                 pos = PCI_EXT_CAP_NEXT(header);
322                 if (pos < 256)
323                         break;
324 
325                 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
326                         break;
327         }
328 
329         return 0;
330 }
331 
332 /**
333  * pnv_eeh_probe - Do probe on PCI device
334  * @pdn: PCI device node
335  * @data: unused
336  *
337  * When EEH module is installed during system boot, all PCI devices
338  * are checked one by one to see if it supports EEH. The function
339  * is introduced for the purpose. By default, EEH has been enabled
340  * on all PCI devices. That's to say, we only need do necessary
341  * initialization on the corresponding eeh device and create PE
342  * accordingly.
343  *
344  * It's notable that's unsafe to retrieve the EEH device through
345  * the corresponding PCI device. During the PCI device hotplug, which
346  * was possiblly triggered by EEH core, the binding between EEH device
347  * and the PCI device isn't built yet.
348  */
349 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
350 {
351         struct pci_controller *hose = pdn->phb;
352         struct pnv_phb *phb = hose->private_data;
353         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
354         uint32_t pcie_flags;
355         int ret;
356 
357         /*
358          * When probing the root bridge, which doesn't have any
359          * subordinate PCI devices. We don't have OF node for
360          * the root bridge. So it's not reasonable to continue
361          * the probing.
362          */
363         if (!edev || edev->pe)
364                 return NULL;
365 
366         /* Skip for PCI-ISA bridge */
367         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
368                 return NULL;
369 
370         /* Initialize eeh device */
371         edev->class_code = pdn->class_code;
372         edev->mode      &= 0xFFFFFF00;
373         edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
374         edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
375         edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
376         edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
377         if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
378                 edev->mode |= EEH_DEV_BRIDGE;
379                 if (edev->pcie_cap) {
380                         pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
381                                          2, &pcie_flags);
382                         pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
383                         if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
384                                 edev->mode |= EEH_DEV_ROOT_PORT;
385                         else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
386                                 edev->mode |= EEH_DEV_DS_PORT;
387                 }
388         }
389 
390         edev->config_addr    = (pdn->busno << 8) | (pdn->devfn);
391         edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr];
392 
393         /* Create PE */
394         ret = eeh_add_to_parent_pe(edev);
395         if (ret) {
396                 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n",
397                         __func__, hose->global_number, pdn->busno,
398                         PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
399                 return NULL;
400         }
401 
402         /*
403          * If the PE contains any one of following adapters, the
404          * PCI config space can't be accessed when dumping EEH log.
405          * Otherwise, we will run into fenced PHB caused by shortage
406          * of outbound credits in the adapter. The PCI config access
407          * should be blocked until PE reset. MMIO access is dropped
408          * by hardware certainly. In order to drop PCI config requests,
409          * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
410          * will be checked in the backend for PE state retrival. If
411          * the PE becomes frozen for the first time and the flag has
412          * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
413          * that PE to block its config space.
414          *
415          * Broadcom Austin 4-ports NICs (14e4:1657)
416          * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
417          * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
418          */
419         if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
420              pdn->device_id == 0x1657) ||
421             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
422              pdn->device_id == 0x168a) ||
423             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
424              pdn->device_id == 0x168e))
425                 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
426 
427         /*
428          * Cache the PE primary bus, which can't be fetched when
429          * full hotplug is in progress. In that case, all child
430          * PCI devices of the PE are expected to be removed prior
431          * to PE reset.
432          */
433         if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
434                 edev->pe->bus = pci_find_bus(hose->global_number,
435                                              pdn->busno);
436                 if (edev->pe->bus)
437                         edev->pe->state |= EEH_PE_PRI_BUS;
438         }
439 
440         /*
441          * Enable EEH explicitly so that we will do EEH check
442          * while accessing I/O stuff
443          */
444         eeh_add_flag(EEH_ENABLED);
445 
446         /* Save memory bars */
447         eeh_save_bars(edev);
448 
449         return NULL;
450 }
451 
452 /**
453  * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
454  * @pe: EEH PE
455  * @option: operation to be issued
456  *
457  * The function is used to control the EEH functionality globally.
458  * Currently, following options are support according to PAPR:
459  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
460  */
461 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
462 {
463         struct pci_controller *hose = pe->phb;
464         struct pnv_phb *phb = hose->private_data;
465         bool freeze_pe = false;
466         int opt;
467         s64 rc;
468 
469         switch (option) {
470         case EEH_OPT_DISABLE:
471                 return -EPERM;
472         case EEH_OPT_ENABLE:
473                 return 0;
474         case EEH_OPT_THAW_MMIO:
475                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
476                 break;
477         case EEH_OPT_THAW_DMA:
478                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
479                 break;
480         case EEH_OPT_FREEZE_PE:
481                 freeze_pe = true;
482                 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
483                 break;
484         default:
485                 pr_warn("%s: Invalid option %d\n", __func__, option);
486                 return -EINVAL;
487         }
488 
489         /* Freeze master and slave PEs if PHB supports compound PEs */
490         if (freeze_pe) {
491                 if (phb->freeze_pe) {
492                         phb->freeze_pe(phb, pe->addr);
493                         return 0;
494                 }
495 
496                 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
497                 if (rc != OPAL_SUCCESS) {
498                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
499                                 __func__, rc, phb->hose->global_number,
500                                 pe->addr);
501                         return -EIO;
502                 }
503 
504                 return 0;
505         }
506 
507         /* Unfreeze master and slave PEs if PHB supports */
508         if (phb->unfreeze_pe)
509                 return phb->unfreeze_pe(phb, pe->addr, opt);
510 
511         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
512         if (rc != OPAL_SUCCESS) {
513                 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
514                         __func__, rc, option, phb->hose->global_number,
515                         pe->addr);
516                 return -EIO;
517         }
518 
519         return 0;
520 }
521 
522 /**
523  * pnv_eeh_get_pe_addr - Retrieve PE address
524  * @pe: EEH PE
525  *
526  * Retrieve the PE address according to the given tranditional
527  * PCI BDF (Bus/Device/Function) address.
528  */
529 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
530 {
531         return pe->addr;
532 }
533 
534 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
535 {
536         struct pnv_phb *phb = pe->phb->private_data;
537         s64 rc;
538 
539         rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
540                                          PNV_PCI_DIAG_BUF_SIZE);
541         if (rc != OPAL_SUCCESS)
542                 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
543                         __func__, rc, pe->phb->global_number);
544 }
545 
546 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
547 {
548         struct pnv_phb *phb = pe->phb->private_data;
549         u8 fstate;
550         __be16 pcierr;
551         s64 rc;
552         int result = 0;
553 
554         rc = opal_pci_eeh_freeze_status(phb->opal_id,
555                                         pe->addr,
556                                         &fstate,
557                                         &pcierr,
558                                         NULL);
559         if (rc != OPAL_SUCCESS) {
560                 pr_warn("%s: Failure %lld getting PHB#%x state\n",
561                         __func__, rc, phb->hose->global_number);
562                 return EEH_STATE_NOT_SUPPORT;
563         }
564 
565         /*
566          * Check PHB state. If the PHB is frozen for the
567          * first time, to dump the PHB diag-data.
568          */
569         if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
570                 result = (EEH_STATE_MMIO_ACTIVE  |
571                           EEH_STATE_DMA_ACTIVE   |
572                           EEH_STATE_MMIO_ENABLED |
573                           EEH_STATE_DMA_ENABLED);
574         } else if (!(pe->state & EEH_PE_ISOLATED)) {
575                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
576                 pnv_eeh_get_phb_diag(pe);
577 
578                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
579                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
580         }
581 
582         return result;
583 }
584 
585 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
586 {
587         struct pnv_phb *phb = pe->phb->private_data;
588         u8 fstate;
589         __be16 pcierr;
590         s64 rc;
591         int result;
592 
593         /*
594          * We don't clobber hardware frozen state until PE
595          * reset is completed. In order to keep EEH core
596          * moving forward, we have to return operational
597          * state during PE reset.
598          */
599         if (pe->state & EEH_PE_RESET) {
600                 result = (EEH_STATE_MMIO_ACTIVE  |
601                           EEH_STATE_DMA_ACTIVE   |
602                           EEH_STATE_MMIO_ENABLED |
603                           EEH_STATE_DMA_ENABLED);
604                 return result;
605         }
606 
607         /*
608          * Fetch PE state from hardware. If the PHB
609          * supports compound PE, let it handle that.
610          */
611         if (phb->get_pe_state) {
612                 fstate = phb->get_pe_state(phb, pe->addr);
613         } else {
614                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
615                                                 pe->addr,
616                                                 &fstate,
617                                                 &pcierr,
618                                                 NULL);
619                 if (rc != OPAL_SUCCESS) {
620                         pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
621                                 __func__, rc, phb->hose->global_number,
622                                 pe->addr);
623                         return EEH_STATE_NOT_SUPPORT;
624                 }
625         }
626 
627         /* Figure out state */
628         switch (fstate) {
629         case OPAL_EEH_STOPPED_NOT_FROZEN:
630                 result = (EEH_STATE_MMIO_ACTIVE  |
631                           EEH_STATE_DMA_ACTIVE   |
632                           EEH_STATE_MMIO_ENABLED |
633                           EEH_STATE_DMA_ENABLED);
634                 break;
635         case OPAL_EEH_STOPPED_MMIO_FREEZE:
636                 result = (EEH_STATE_DMA_ACTIVE |
637                           EEH_STATE_DMA_ENABLED);
638                 break;
639         case OPAL_EEH_STOPPED_DMA_FREEZE:
640                 result = (EEH_STATE_MMIO_ACTIVE |
641                           EEH_STATE_MMIO_ENABLED);
642                 break;
643         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
644                 result = 0;
645                 break;
646         case OPAL_EEH_STOPPED_RESET:
647                 result = EEH_STATE_RESET_ACTIVE;
648                 break;
649         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
650                 result = EEH_STATE_UNAVAILABLE;
651                 break;
652         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
653                 result = EEH_STATE_NOT_SUPPORT;
654                 break;
655         default:
656                 result = EEH_STATE_NOT_SUPPORT;
657                 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
658                         __func__, phb->hose->global_number,
659                         pe->addr, fstate);
660         }
661 
662         /*
663          * If PHB supports compound PE, to freeze all
664          * slave PEs for consistency.
665          *
666          * If the PE is switching to frozen state for the
667          * first time, to dump the PHB diag-data.
668          */
669         if (!(result & EEH_STATE_NOT_SUPPORT) &&
670             !(result & EEH_STATE_UNAVAILABLE) &&
671             !(result & EEH_STATE_MMIO_ACTIVE) &&
672             !(result & EEH_STATE_DMA_ACTIVE)  &&
673             !(pe->state & EEH_PE_ISOLATED)) {
674                 if (phb->freeze_pe)
675                         phb->freeze_pe(phb, pe->addr);
676 
677                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
678                 pnv_eeh_get_phb_diag(pe);
679 
680                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
681                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
682         }
683 
684         return result;
685 }
686 
687 /**
688  * pnv_eeh_get_state - Retrieve PE state
689  * @pe: EEH PE
690  * @delay: delay while PE state is temporarily unavailable
691  *
692  * Retrieve the state of the specified PE. For IODA-compitable
693  * platform, it should be retrieved from IODA table. Therefore,
694  * we prefer passing down to hardware implementation to handle
695  * it.
696  */
697 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
698 {
699         int ret;
700 
701         if (pe->type & EEH_PE_PHB)
702                 ret = pnv_eeh_get_phb_state(pe);
703         else
704                 ret = pnv_eeh_get_pe_state(pe);
705 
706         if (!delay)
707                 return ret;
708 
709         /*
710          * If the PE state is temporarily unavailable,
711          * to inform the EEH core delay for default
712          * period (1 second)
713          */
714         *delay = 0;
715         if (ret & EEH_STATE_UNAVAILABLE)
716                 *delay = 1000;
717 
718         return ret;
719 }
720 
721 static s64 pnv_eeh_poll(unsigned long id)
722 {
723         s64 rc = OPAL_HARDWARE;
724 
725         while (1) {
726                 rc = opal_pci_poll(id);
727                 if (rc <= 0)
728                         break;
729 
730                 if (system_state < SYSTEM_RUNNING)
731                         udelay(1000 * rc);
732                 else
733                         msleep(rc);
734         }
735 
736         return rc;
737 }
738 
739 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
740 {
741         struct pnv_phb *phb = hose->private_data;
742         s64 rc = OPAL_HARDWARE;
743 
744         pr_debug("%s: Reset PHB#%x, option=%d\n",
745                  __func__, hose->global_number, option);
746 
747         /* Issue PHB complete reset request */
748         if (option == EEH_RESET_FUNDAMENTAL ||
749             option == EEH_RESET_HOT)
750                 rc = opal_pci_reset(phb->opal_id,
751                                     OPAL_RESET_PHB_COMPLETE,
752                                     OPAL_ASSERT_RESET);
753         else if (option == EEH_RESET_DEACTIVATE)
754                 rc = opal_pci_reset(phb->opal_id,
755                                     OPAL_RESET_PHB_COMPLETE,
756                                     OPAL_DEASSERT_RESET);
757         if (rc < 0)
758                 goto out;
759 
760         /*
761          * Poll state of the PHB until the request is done
762          * successfully. The PHB reset is usually PHB complete
763          * reset followed by hot reset on root bus. So we also
764          * need the PCI bus settlement delay.
765          */
766         rc = pnv_eeh_poll(phb->opal_id);
767         if (option == EEH_RESET_DEACTIVATE) {
768                 if (system_state < SYSTEM_RUNNING)
769                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
770                 else
771                         msleep(EEH_PE_RST_SETTLE_TIME);
772         }
773 out:
774         if (rc != OPAL_SUCCESS)
775                 return -EIO;
776 
777         return 0;
778 }
779 
780 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
781 {
782         struct pnv_phb *phb = hose->private_data;
783         s64 rc = OPAL_HARDWARE;
784 
785         pr_debug("%s: Reset PHB#%x, option=%d\n",
786                  __func__, hose->global_number, option);
787 
788         /*
789          * During the reset deassert time, we needn't care
790          * the reset scope because the firmware does nothing
791          * for fundamental or hot reset during deassert phase.
792          */
793         if (option == EEH_RESET_FUNDAMENTAL)
794                 rc = opal_pci_reset(phb->opal_id,
795                                     OPAL_RESET_PCI_FUNDAMENTAL,
796                                     OPAL_ASSERT_RESET);
797         else if (option == EEH_RESET_HOT)
798                 rc = opal_pci_reset(phb->opal_id,
799                                     OPAL_RESET_PCI_HOT,
800                                     OPAL_ASSERT_RESET);
801         else if (option == EEH_RESET_DEACTIVATE)
802                 rc = opal_pci_reset(phb->opal_id,
803                                     OPAL_RESET_PCI_HOT,
804                                     OPAL_DEASSERT_RESET);
805         if (rc < 0)
806                 goto out;
807 
808         /* Poll state of the PHB until the request is done */
809         rc = pnv_eeh_poll(phb->opal_id);
810         if (option == EEH_RESET_DEACTIVATE)
811                 msleep(EEH_PE_RST_SETTLE_TIME);
812 out:
813         if (rc != OPAL_SUCCESS)
814                 return -EIO;
815 
816         return 0;
817 }
818 
819 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
820 {
821         struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
822         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
823         int aer = edev ? edev->aer_cap : 0;
824         u32 ctrl;
825 
826         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
827                  __func__, pci_domain_nr(dev->bus),
828                  dev->bus->number, option);
829 
830         switch (option) {
831         case EEH_RESET_FUNDAMENTAL:
832         case EEH_RESET_HOT:
833                 /* Don't report linkDown event */
834                 if (aer) {
835                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
836                                              4, &ctrl);
837                         ctrl |= PCI_ERR_UNC_SURPDN;
838                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
839                                               4, ctrl);
840                 }
841 
842                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
843                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
844                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
845 
846                 msleep(EEH_PE_RST_HOLD_TIME);
847                 break;
848         case EEH_RESET_DEACTIVATE:
849                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
850                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
851                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
852 
853                 msleep(EEH_PE_RST_SETTLE_TIME);
854 
855                 /* Continue reporting linkDown event */
856                 if (aer) {
857                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
858                                              4, &ctrl);
859                         ctrl &= ~PCI_ERR_UNC_SURPDN;
860                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
861                                               4, ctrl);
862                 }
863 
864                 break;
865         }
866 
867         return 0;
868 }
869 
870 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
871 {
872         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
873         struct pnv_phb *phb = hose->private_data;
874         struct device_node *dn = pci_device_to_OF_node(pdev);
875         uint64_t id = PCI_SLOT_ID(phb->opal_id,
876                                   (pdev->bus->number << 8) | pdev->devfn);
877         uint8_t scope;
878         int64_t rc;
879 
880         /* Hot reset to the bus if firmware cannot handle */
881         if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
882                 return __pnv_eeh_bridge_reset(pdev, option);
883 
884         switch (option) {
885         case EEH_RESET_FUNDAMENTAL:
886                 scope = OPAL_RESET_PCI_FUNDAMENTAL;
887                 break;
888         case EEH_RESET_HOT:
889                 scope = OPAL_RESET_PCI_HOT;
890                 break;
891         case EEH_RESET_DEACTIVATE:
892                 return 0;
893         default:
894                 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
895                         __func__, option);
896                 return -EINVAL;
897         }
898 
899         rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
900         if (rc <= OPAL_SUCCESS)
901                 goto out;
902 
903         rc = pnv_eeh_poll(id);
904 out:
905         return (rc == OPAL_SUCCESS) ? 0 : -EIO;
906 }
907 
908 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
909 {
910         struct pci_controller *hose;
911 
912         if (pci_is_root_bus(dev->bus)) {
913                 hose = pci_bus_to_host(dev->bus);
914                 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
915                 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
916         } else {
917                 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
918                 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
919         }
920 }
921 
922 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
923                                      int pos, u16 mask)
924 {
925         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
926         int i, status = 0;
927 
928         /* Wait for Transaction Pending bit to be cleared */
929         for (i = 0; i < 4; i++) {
930                 eeh_ops->read_config(pdn, pos, 2, &status);
931                 if (!(status & mask))
932                         return;
933 
934                 msleep((1 << i) * 100);
935         }
936 
937         pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
938                 __func__, type,
939                 edev->phb->global_number, pdn->busno,
940                 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
941 }
942 
943 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
944 {
945         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
946         u32 reg = 0;
947 
948         if (WARN_ON(!edev->pcie_cap))
949                 return -ENOTTY;
950 
951         eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
952         if (!(reg & PCI_EXP_DEVCAP_FLR))
953                 return -ENOTTY;
954 
955         switch (option) {
956         case EEH_RESET_HOT:
957         case EEH_RESET_FUNDAMENTAL:
958                 pnv_eeh_wait_for_pending(pdn, "",
959                                          edev->pcie_cap + PCI_EXP_DEVSTA,
960                                          PCI_EXP_DEVSTA_TRPND);
961                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
962                                      4, &reg);
963                 reg |= PCI_EXP_DEVCTL_BCR_FLR;
964                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
965                                       4, reg);
966                 msleep(EEH_PE_RST_HOLD_TIME);
967                 break;
968         case EEH_RESET_DEACTIVATE:
969                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
970                                      4, &reg);
971                 reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
972                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
973                                       4, reg);
974                 msleep(EEH_PE_RST_SETTLE_TIME);
975                 break;
976         }
977 
978         return 0;
979 }
980 
981 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
982 {
983         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
984         u32 cap = 0;
985 
986         if (WARN_ON(!edev->af_cap))
987                 return -ENOTTY;
988 
989         eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
990         if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
991                 return -ENOTTY;
992 
993         switch (option) {
994         case EEH_RESET_HOT:
995         case EEH_RESET_FUNDAMENTAL:
996                 /*
997                  * Wait for Transaction Pending bit to clear. A word-aligned
998                  * test is used, so we use the conrol offset rather than status
999                  * and shift the test bit to match.
1000                  */
1001                 pnv_eeh_wait_for_pending(pdn, "AF",
1002                                          edev->af_cap + PCI_AF_CTRL,
1003                                          PCI_AF_STATUS_TP << 8);
1004                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
1005                                       1, PCI_AF_CTRL_FLR);
1006                 msleep(EEH_PE_RST_HOLD_TIME);
1007                 break;
1008         case EEH_RESET_DEACTIVATE:
1009                 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
1010                 msleep(EEH_PE_RST_SETTLE_TIME);
1011                 break;
1012         }
1013 
1014         return 0;
1015 }
1016 
1017 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
1018 {
1019         struct eeh_dev *edev;
1020         struct pci_dn *pdn;
1021         int ret;
1022 
1023         /* The VF PE should have only one child device */
1024         edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
1025         pdn = eeh_dev_to_pdn(edev);
1026         if (!pdn)
1027                 return -ENXIO;
1028 
1029         ret = pnv_eeh_do_flr(pdn, option);
1030         if (!ret)
1031                 return ret;
1032 
1033         return pnv_eeh_do_af_flr(pdn, option);
1034 }
1035 
1036 /**
1037  * pnv_eeh_reset - Reset the specified PE
1038  * @pe: EEH PE
1039  * @option: reset option
1040  *
1041  * Do reset on the indicated PE. For PCI bus sensitive PE,
1042  * we need to reset the parent p2p bridge. The PHB has to
1043  * be reinitialized if the p2p bridge is root bridge. For
1044  * PCI device sensitive PE, we will try to reset the device
1045  * through FLR. For now, we don't have OPAL APIs to do HARD
1046  * reset yet, so all reset would be SOFT (HOT) reset.
1047  */
1048 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1049 {
1050         struct pci_controller *hose = pe->phb;
1051         struct pnv_phb *phb;
1052         struct pci_bus *bus;
1053         int64_t rc;
1054 
1055         /*
1056          * For PHB reset, we always have complete reset. For those PEs whose
1057          * primary bus derived from root complex (root bus) or root port
1058          * (usually bus#1), we apply hot or fundamental reset on the root port.
1059          * For other PEs, we always have hot reset on the PE primary bus.
1060          *
1061          * Here, we have different design to pHyp, which always clear the
1062          * frozen state during PE reset. However, the good idea here from
1063          * benh is to keep frozen state before we get PE reset done completely
1064          * (until BAR restore). With the frozen state, HW drops illegal IO
1065          * or MMIO access, which can incur recrusive frozen PE during PE
1066          * reset. The side effect is that EEH core has to clear the frozen
1067          * state explicitly after BAR restore.
1068          */
1069         if (pe->type & EEH_PE_PHB)
1070                 return pnv_eeh_phb_reset(hose, option);
1071 
1072         /*
1073          * The frozen PE might be caused by PAPR error injection
1074          * registers, which are expected to be cleared after hitting
1075          * frozen PE as stated in the hardware spec. Unfortunately,
1076          * that's not true on P7IOC. So we have to clear it manually
1077          * to avoid recursive EEH errors during recovery.
1078          */
1079         phb = hose->private_data;
1080         if (phb->model == PNV_PHB_MODEL_P7IOC &&
1081             (option == EEH_RESET_HOT ||
1082              option == EEH_RESET_FUNDAMENTAL)) {
1083                 rc = opal_pci_reset(phb->opal_id,
1084                                     OPAL_RESET_PHB_ERROR,
1085                                     OPAL_ASSERT_RESET);
1086                 if (rc != OPAL_SUCCESS) {
1087                         pr_warn("%s: Failure %lld clearing error injection registers\n",
1088                                 __func__, rc);
1089                         return -EIO;
1090                 }
1091         }
1092 
1093         bus = eeh_pe_bus_get(pe);
1094         if (!bus) {
1095                 pr_err("%s: Cannot find PCI bus for PHB#%d-PE#%x\n",
1096                         __func__, pe->phb->global_number, pe->addr);
1097                 return -EIO;
1098         }
1099         if (pe->type & EEH_PE_VF)
1100                 return pnv_eeh_reset_vf_pe(pe, option);
1101 
1102         if (pci_is_root_bus(bus) ||
1103             pci_is_root_bus(bus->parent))
1104                 return pnv_eeh_root_reset(hose, option);
1105 
1106         return pnv_eeh_bridge_reset(bus->self, option);
1107 }
1108 
1109 /**
1110  * pnv_eeh_wait_state - Wait for PE state
1111  * @pe: EEH PE
1112  * @max_wait: maximal period in millisecond
1113  *
1114  * Wait for the state of associated PE. It might take some time
1115  * to retrieve the PE's state.
1116  */
1117 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
1118 {
1119         int ret;
1120         int mwait;
1121 
1122         while (1) {
1123                 ret = pnv_eeh_get_state(pe, &mwait);
1124 
1125                 /*
1126                  * If the PE's state is temporarily unavailable,
1127                  * we have to wait for the specified time. Otherwise,
1128                  * the PE's state will be returned immediately.
1129                  */
1130                 if (ret != EEH_STATE_UNAVAILABLE)
1131                         return ret;
1132 
1133                 if (max_wait <= 0) {
1134                         pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
1135                                 __func__, pe->addr, max_wait);
1136                         return EEH_STATE_NOT_SUPPORT;
1137                 }
1138 
1139                 max_wait -= mwait;
1140                 msleep(mwait);
1141         }
1142 
1143         return EEH_STATE_NOT_SUPPORT;
1144 }
1145 
1146 /**
1147  * pnv_eeh_get_log - Retrieve error log
1148  * @pe: EEH PE
1149  * @severity: temporary or permanent error log
1150  * @drv_log: driver log to be combined with retrieved error log
1151  * @len: length of driver log
1152  *
1153  * Retrieve the temporary or permanent error from the PE.
1154  */
1155 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1156                            char *drv_log, unsigned long len)
1157 {
1158         if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1159                 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1160 
1161         return 0;
1162 }
1163 
1164 /**
1165  * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1166  * @pe: EEH PE
1167  *
1168  * The function will be called to reconfigure the bridges included
1169  * in the specified PE so that the mulfunctional PE would be recovered
1170  * again.
1171  */
1172 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1173 {
1174         return 0;
1175 }
1176 
1177 /**
1178  * pnv_pe_err_inject - Inject specified error to the indicated PE
1179  * @pe: the indicated PE
1180  * @type: error type
1181  * @func: specific error type
1182  * @addr: address
1183  * @mask: address mask
1184  *
1185  * The routine is called to inject specified error, which is
1186  * determined by @type and @func, to the indicated PE for
1187  * testing purpose.
1188  */
1189 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1190                               unsigned long addr, unsigned long mask)
1191 {
1192         struct pci_controller *hose = pe->phb;
1193         struct pnv_phb *phb = hose->private_data;
1194         s64 rc;
1195 
1196         if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1197             type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1198                 pr_warn("%s: Invalid error type %d\n",
1199                         __func__, type);
1200                 return -ERANGE;
1201         }
1202 
1203         if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1204             func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1205                 pr_warn("%s: Invalid error function %d\n",
1206                         __func__, func);
1207                 return -ERANGE;
1208         }
1209 
1210         /* Firmware supports error injection ? */
1211         if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1212                 pr_warn("%s: Firmware doesn't support error injection\n",
1213                         __func__);
1214                 return -ENXIO;
1215         }
1216 
1217         /* Do error injection */
1218         rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1219                                  type, func, addr, mask);
1220         if (rc != OPAL_SUCCESS) {
1221                 pr_warn("%s: Failure %lld injecting error "
1222                         "%d-%d to PHB#%x-PE#%x\n",
1223                         __func__, rc, type, func,
1224                         hose->global_number, pe->addr);
1225                 return -EIO;
1226         }
1227 
1228         return 0;
1229 }
1230 
1231 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1232 {
1233         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1234 
1235         if (!edev || !edev->pe)
1236                 return false;
1237 
1238         /*
1239          * We will issue FLR or AF FLR to all VFs, which are contained
1240          * in VF PE. It relies on the EEH PCI config accessors. So we
1241          * can't block them during the window.
1242          */
1243         if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1244                 return false;
1245 
1246         if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1247                 return true;
1248 
1249         return false;
1250 }
1251 
1252 static int pnv_eeh_read_config(struct pci_dn *pdn,
1253                                int where, int size, u32 *val)
1254 {
1255         if (!pdn)
1256                 return PCIBIOS_DEVICE_NOT_FOUND;
1257 
1258         if (pnv_eeh_cfg_blocked(pdn)) {
1259                 *val = 0xFFFFFFFF;
1260                 return PCIBIOS_SET_FAILED;
1261         }
1262 
1263         return pnv_pci_cfg_read(pdn, where, size, val);
1264 }
1265 
1266 static int pnv_eeh_write_config(struct pci_dn *pdn,
1267                                 int where, int size, u32 val)
1268 {
1269         if (!pdn)
1270                 return PCIBIOS_DEVICE_NOT_FOUND;
1271 
1272         if (pnv_eeh_cfg_blocked(pdn))
1273                 return PCIBIOS_SET_FAILED;
1274 
1275         return pnv_pci_cfg_write(pdn, where, size, val);
1276 }
1277 
1278 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1279 {
1280         /* GEM */
1281         if (data->gemXfir || data->gemRfir ||
1282             data->gemRirqfir || data->gemMask || data->gemRwof)
1283                 pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1284                         be64_to_cpu(data->gemXfir),
1285                         be64_to_cpu(data->gemRfir),
1286                         be64_to_cpu(data->gemRirqfir),
1287                         be64_to_cpu(data->gemMask),
1288                         be64_to_cpu(data->gemRwof));
1289 
1290         /* LEM */
1291         if (data->lemFir || data->lemErrMask ||
1292             data->lemAction0 || data->lemAction1 || data->lemWof)
1293                 pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1294                         be64_to_cpu(data->lemFir),
1295                         be64_to_cpu(data->lemErrMask),
1296                         be64_to_cpu(data->lemAction0),
1297                         be64_to_cpu(data->lemAction1),
1298                         be64_to_cpu(data->lemWof));
1299 }
1300 
1301 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1302 {
1303         struct pnv_phb *phb = hose->private_data;
1304         struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
1305         long rc;
1306 
1307         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1308         if (rc != OPAL_SUCCESS) {
1309                 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1310                         __func__, phb->hub_id, rc);
1311                 return;
1312         }
1313 
1314         switch (be16_to_cpu(data->type)) {
1315         case OPAL_P7IOC_DIAG_TYPE_RGC:
1316                 pr_info("P7IOC diag-data for RGC\n\n");
1317                 pnv_eeh_dump_hub_diag_common(data);
1318                 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1319                         pr_info("  RGC: %016llx %016llx\n",
1320                                 be64_to_cpu(data->rgc.rgcStatus),
1321                                 be64_to_cpu(data->rgc.rgcLdcp));
1322                 break;
1323         case OPAL_P7IOC_DIAG_TYPE_BI:
1324                 pr_info("P7IOC diag-data for BI %s\n\n",
1325                         data->bi.biDownbound ? "Downbound" : "Upbound");
1326                 pnv_eeh_dump_hub_diag_common(data);
1327                 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1328                     data->bi.biLdcp2 || data->bi.biFenceStatus)
1329                         pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1330                                 be64_to_cpu(data->bi.biLdcp0),
1331                                 be64_to_cpu(data->bi.biLdcp1),
1332                                 be64_to_cpu(data->bi.biLdcp2),
1333                                 be64_to_cpu(data->bi.biFenceStatus));
1334                 break;
1335         case OPAL_P7IOC_DIAG_TYPE_CI:
1336                 pr_info("P7IOC diag-data for CI Port %d\n\n",
1337                         data->ci.ciPort);
1338                 pnv_eeh_dump_hub_diag_common(data);
1339                 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1340                         pr_info("  CI:  %016llx %016llx\n",
1341                                 be64_to_cpu(data->ci.ciPortStatus),
1342                                 be64_to_cpu(data->ci.ciPortLdcp));
1343                 break;
1344         case OPAL_P7IOC_DIAG_TYPE_MISC:
1345                 pr_info("P7IOC diag-data for MISC\n\n");
1346                 pnv_eeh_dump_hub_diag_common(data);
1347                 break;
1348         case OPAL_P7IOC_DIAG_TYPE_I2C:
1349                 pr_info("P7IOC diag-data for I2C\n\n");
1350                 pnv_eeh_dump_hub_diag_common(data);
1351                 break;
1352         default:
1353                 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1354                         __func__, phb->hub_id, data->type);
1355         }
1356 }
1357 
1358 static int pnv_eeh_get_pe(struct pci_controller *hose,
1359                           u16 pe_no, struct eeh_pe **pe)
1360 {
1361         struct pnv_phb *phb = hose->private_data;
1362         struct pnv_ioda_pe *pnv_pe;
1363         struct eeh_pe *dev_pe;
1364         struct eeh_dev edev;
1365 
1366         /*
1367          * If PHB supports compound PE, to fetch
1368          * the master PE because slave PE is invisible
1369          * to EEH core.
1370          */
1371         pnv_pe = &phb->ioda.pe_array[pe_no];
1372         if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1373                 pnv_pe = pnv_pe->master;
1374                 WARN_ON(!pnv_pe ||
1375                         !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1376                 pe_no = pnv_pe->pe_number;
1377         }
1378 
1379         /* Find the PE according to PE# */
1380         memset(&edev, 0, sizeof(struct eeh_dev));
1381         edev.phb = hose;
1382         edev.pe_config_addr = pe_no;
1383         dev_pe = eeh_pe_get(&edev);
1384         if (!dev_pe)
1385                 return -EEXIST;
1386 
1387         /* Freeze the (compound) PE */
1388         *pe = dev_pe;
1389         if (!(dev_pe->state & EEH_PE_ISOLATED))
1390                 phb->freeze_pe(phb, pe_no);
1391 
1392         /*
1393          * At this point, we're sure the (compound) PE should
1394          * have been frozen. However, we still need poke until
1395          * hitting the frozen PE on top level.
1396          */
1397         dev_pe = dev_pe->parent;
1398         while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1399                 int ret;
1400                 int active_flags = (EEH_STATE_MMIO_ACTIVE |
1401                                     EEH_STATE_DMA_ACTIVE);
1402 
1403                 ret = eeh_ops->get_state(dev_pe, NULL);
1404                 if (ret <= 0 || (ret & active_flags) == active_flags) {
1405                         dev_pe = dev_pe->parent;
1406                         continue;
1407                 }
1408 
1409                 /* Frozen parent PE */
1410                 *pe = dev_pe;
1411                 if (!(dev_pe->state & EEH_PE_ISOLATED))
1412                         phb->freeze_pe(phb, dev_pe->addr);
1413 
1414                 /* Next one */
1415                 dev_pe = dev_pe->parent;
1416         }
1417 
1418         return 0;
1419 }
1420 
1421 /**
1422  * pnv_eeh_next_error - Retrieve next EEH error to handle
1423  * @pe: Affected PE
1424  *
1425  * The function is expected to be called by EEH core while it gets
1426  * special EEH event (without binding PE). The function calls to
1427  * OPAL APIs for next error to handle. The informational error is
1428  * handled internally by platform. However, the dead IOC, dead PHB,
1429  * fenced PHB and frozen PE should be handled by EEH core eventually.
1430  */
1431 static int pnv_eeh_next_error(struct eeh_pe **pe)
1432 {
1433         struct pci_controller *hose;
1434         struct pnv_phb *phb;
1435         struct eeh_pe *phb_pe, *parent_pe;
1436         __be64 frozen_pe_no;
1437         __be16 err_type, severity;
1438         int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1439         long rc;
1440         int state, ret = EEH_NEXT_ERR_NONE;
1441 
1442         /*
1443          * While running here, it's safe to purge the event queue. The
1444          * event should still be masked.
1445          */
1446         eeh_remove_event(NULL, false);
1447 
1448         list_for_each_entry(hose, &hose_list, list_node) {
1449                 /*
1450                  * If the subordinate PCI buses of the PHB has been
1451                  * removed or is exactly under error recovery, we
1452                  * needn't take care of it any more.
1453                  */
1454                 phb = hose->private_data;
1455                 phb_pe = eeh_phb_pe_get(hose);
1456                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1457                         continue;
1458 
1459                 rc = opal_pci_next_error(phb->opal_id,
1460                                          &frozen_pe_no, &err_type, &severity);
1461                 if (rc != OPAL_SUCCESS) {
1462                         pr_devel("%s: Invalid return value on "
1463                                  "PHB#%x (0x%lx) from opal_pci_next_error",
1464                                  __func__, hose->global_number, rc);
1465                         continue;
1466                 }
1467 
1468                 /* If the PHB doesn't have error, stop processing */
1469                 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1470                     be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1471                         pr_devel("%s: No error found on PHB#%x\n",
1472                                  __func__, hose->global_number);
1473                         continue;
1474                 }
1475 
1476                 /*
1477                  * Processing the error. We're expecting the error with
1478                  * highest priority reported upon multiple errors on the
1479                  * specific PHB.
1480                  */
1481                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1482                         __func__, be16_to_cpu(err_type),
1483                         be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1484                         hose->global_number);
1485                 switch (be16_to_cpu(err_type)) {
1486                 case OPAL_EEH_IOC_ERROR:
1487                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1488                                 pr_err("EEH: dead IOC detected\n");
1489                                 ret = EEH_NEXT_ERR_DEAD_IOC;
1490                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1491                                 pr_info("EEH: IOC informative error "
1492                                         "detected\n");
1493                                 pnv_eeh_get_and_dump_hub_diag(hose);
1494                                 ret = EEH_NEXT_ERR_NONE;
1495                         }
1496 
1497                         break;
1498                 case OPAL_EEH_PHB_ERROR:
1499                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1500                                 *pe = phb_pe;
1501                                 pr_err("EEH: dead PHB#%x detected, "
1502                                        "location: %s\n",
1503                                         hose->global_number,
1504                                         eeh_pe_loc_get(phb_pe));
1505                                 ret = EEH_NEXT_ERR_DEAD_PHB;
1506                         } else if (be16_to_cpu(severity) ==
1507                                    OPAL_EEH_SEV_PHB_FENCED) {
1508                                 *pe = phb_pe;
1509                                 pr_err("EEH: Fenced PHB#%x detected, "
1510                                        "location: %s\n",
1511                                         hose->global_number,
1512                                         eeh_pe_loc_get(phb_pe));
1513                                 ret = EEH_NEXT_ERR_FENCED_PHB;
1514                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1515                                 pr_info("EEH: PHB#%x informative error "
1516                                         "detected, location: %s\n",
1517                                         hose->global_number,
1518                                         eeh_pe_loc_get(phb_pe));
1519                                 pnv_eeh_get_phb_diag(phb_pe);
1520                                 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1521                                 ret = EEH_NEXT_ERR_NONE;
1522                         }
1523 
1524                         break;
1525                 case OPAL_EEH_PE_ERROR:
1526                         /*
1527                          * If we can't find the corresponding PE, we
1528                          * just try to unfreeze.
1529                          */
1530                         if (pnv_eeh_get_pe(hose,
1531                                 be64_to_cpu(frozen_pe_no), pe)) {
1532                                 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1533                                         hose->global_number, be64_to_cpu(frozen_pe_no));
1534                                 pr_info("EEH: PHB location: %s\n",
1535                                         eeh_pe_loc_get(phb_pe));
1536 
1537                                 /* Dump PHB diag-data */
1538                                 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1539                                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
1540                                 if (rc == OPAL_SUCCESS)
1541                                         pnv_pci_dump_phb_diag_data(hose,
1542                                                         phb->diag.blob);
1543 
1544                                 /* Try best to clear it */
1545                                 opal_pci_eeh_freeze_clear(phb->opal_id,
1546                                         be64_to_cpu(frozen_pe_no),
1547                                         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1548                                 ret = EEH_NEXT_ERR_NONE;
1549                         } else if ((*pe)->state & EEH_PE_ISOLATED ||
1550                                    eeh_pe_passed(*pe)) {
1551                                 ret = EEH_NEXT_ERR_NONE;
1552                         } else {
1553                                 pr_err("EEH: Frozen PE#%x "
1554                                        "on PHB#%x detected\n",
1555                                        (*pe)->addr,
1556                                         (*pe)->phb->global_number);
1557                                 pr_err("EEH: PE location: %s, "
1558                                        "PHB location: %s\n",
1559                                        eeh_pe_loc_get(*pe),
1560                                        eeh_pe_loc_get(phb_pe));
1561                                 ret = EEH_NEXT_ERR_FROZEN_PE;
1562                         }
1563 
1564                         break;
1565                 default:
1566                         pr_warn("%s: Unexpected error type %d\n",
1567                                 __func__, be16_to_cpu(err_type));
1568                 }
1569 
1570                 /*
1571                  * EEH core will try recover from fenced PHB or
1572                  * frozen PE. In the time for frozen PE, EEH core
1573                  * enable IO path for that before collecting logs,
1574                  * but it ruins the site. So we have to dump the
1575                  * log in advance here.
1576                  */
1577                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1578                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
1579                     !((*pe)->state & EEH_PE_ISOLATED)) {
1580                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1581                         pnv_eeh_get_phb_diag(*pe);
1582 
1583                         if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1584                                 pnv_pci_dump_phb_diag_data((*pe)->phb,
1585                                                            (*pe)->data);
1586                 }
1587 
1588                 /*
1589                  * We probably have the frozen parent PE out there and
1590                  * we need have to handle frozen parent PE firstly.
1591                  */
1592                 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1593                         parent_pe = (*pe)->parent;
1594                         while (parent_pe) {
1595                                 /* Hit the ceiling ? */
1596                                 if (parent_pe->type & EEH_PE_PHB)
1597                                         break;
1598 
1599                                 /* Frozen parent PE ? */
1600                                 state = eeh_ops->get_state(parent_pe, NULL);
1601                                 if (state > 0 &&
1602                                     (state & active_flags) != active_flags)
1603                                         *pe = parent_pe;
1604 
1605                                 /* Next parent level */
1606                                 parent_pe = parent_pe->parent;
1607                         }
1608 
1609                         /* We possibly migrate to another PE */
1610                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1611                 }
1612 
1613                 /*
1614                  * If we have no errors on the specific PHB or only
1615                  * informative error there, we continue poking it.
1616                  * Otherwise, we need actions to be taken by upper
1617                  * layer.
1618                  */
1619                 if (ret > EEH_NEXT_ERR_INF)
1620                         break;
1621         }
1622 
1623         /* Unmask the event */
1624         if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1625                 enable_irq(eeh_event_irq);
1626 
1627         return ret;
1628 }
1629 
1630 static int pnv_eeh_restore_vf_config(struct pci_dn *pdn)
1631 {
1632         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1633         u32 devctl, cmd, cap2, aer_capctl;
1634         int old_mps;
1635 
1636         if (edev->pcie_cap) {
1637                 /* Restore MPS */
1638                 old_mps = (ffs(pdn->mps) - 8) << 5;
1639                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1640                                      2, &devctl);
1641                 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
1642                 devctl |= old_mps;
1643                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1644                                       2, devctl);
1645 
1646                 /* Disable Completion Timeout */
1647                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
1648                                      4, &cap2);
1649                 if (cap2 & 0x10) {
1650                         eeh_ops->read_config(pdn,
1651                                              edev->pcie_cap + PCI_EXP_DEVCTL2,
1652                                              4, &cap2);
1653                         cap2 |= 0x10;
1654                         eeh_ops->write_config(pdn,
1655                                               edev->pcie_cap + PCI_EXP_DEVCTL2,
1656                                               4, cap2);
1657                 }
1658         }
1659 
1660         /* Enable SERR and parity checking */
1661         eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
1662         cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1663         eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
1664 
1665         /* Enable report various errors */
1666         if (edev->pcie_cap) {
1667                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1668                                      2, &devctl);
1669                 devctl &= ~PCI_EXP_DEVCTL_CERE;
1670                 devctl |= (PCI_EXP_DEVCTL_NFERE |
1671                            PCI_EXP_DEVCTL_FERE |
1672                            PCI_EXP_DEVCTL_URRE);
1673                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1674                                       2, devctl);
1675         }
1676 
1677         /* Enable ECRC generation and check */
1678         if (edev->pcie_cap && edev->aer_cap) {
1679                 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
1680                                      4, &aer_capctl);
1681                 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
1682                 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
1683                                       4, aer_capctl);
1684         }
1685 
1686         return 0;
1687 }
1688 
1689 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1690 {
1691         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1692         struct pnv_phb *phb;
1693         s64 ret;
1694 
1695         if (!edev)
1696                 return -EEXIST;
1697 
1698         /*
1699          * We have to restore the PCI config space after reset since the
1700          * firmware can't see SRIOV VFs.
1701          *
1702          * FIXME: The MPS, error routing rules, timeout setting are worthy
1703          * to be exported by firmware in extendible way.
1704          */
1705         if (edev->physfn) {
1706                 ret = pnv_eeh_restore_vf_config(pdn);
1707         } else {
1708                 phb = edev->phb->private_data;
1709                 ret = opal_pci_reinit(phb->opal_id,
1710                                       OPAL_REINIT_PCI_DEV, edev->config_addr);
1711         }
1712 
1713         if (ret) {
1714                 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1715                         __func__, edev->config_addr, ret);
1716                 return -EIO;
1717         }
1718 
1719         return 0;
1720 }
1721 
1722 static struct eeh_ops pnv_eeh_ops = {
1723         .name                   = "powernv",
1724         .init                   = pnv_eeh_init,
1725         .post_init              = pnv_eeh_post_init,
1726         .probe                  = pnv_eeh_probe,
1727         .set_option             = pnv_eeh_set_option,
1728         .get_pe_addr            = pnv_eeh_get_pe_addr,
1729         .get_state              = pnv_eeh_get_state,
1730         .reset                  = pnv_eeh_reset,
1731         .wait_state             = pnv_eeh_wait_state,
1732         .get_log                = pnv_eeh_get_log,
1733         .configure_bridge       = pnv_eeh_configure_bridge,
1734         .err_inject             = pnv_eeh_err_inject,
1735         .read_config            = pnv_eeh_read_config,
1736         .write_config           = pnv_eeh_write_config,
1737         .next_error             = pnv_eeh_next_error,
1738         .restore_config         = pnv_eeh_restore_config
1739 };
1740 
1741 void pcibios_bus_add_device(struct pci_dev *pdev)
1742 {
1743         struct pci_dn *pdn = pci_get_pdn(pdev);
1744 
1745         if (!pdev->is_virtfn)
1746                 return;
1747 
1748         /*
1749          * The following operations will fail if VF's sysfs files
1750          * aren't created or its resources aren't finalized.
1751          */
1752         eeh_add_device_early(pdn);
1753         eeh_add_device_late(pdev);
1754         eeh_sysfs_add_device(pdev);
1755 }
1756 
1757 #ifdef CONFIG_PCI_IOV
1758 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
1759 {
1760         struct pci_dn *pdn = pci_get_pdn(pdev);
1761         int parent_mps;
1762 
1763         if (!pdev->is_virtfn)
1764                 return;
1765 
1766         /* Synchronize MPS for VF and PF */
1767         parent_mps = pcie_get_mps(pdev->physfn);
1768         if ((128 << pdev->pcie_mpss) >= parent_mps)
1769                 pcie_set_mps(pdev, parent_mps);
1770         pdn->mps = pcie_get_mps(pdev);
1771 }
1772 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
1773 #endif /* CONFIG_PCI_IOV */
1774 
1775 /**
1776  * eeh_powernv_init - Register platform dependent EEH operations
1777  *
1778  * EEH initialization on powernv platform. This function should be
1779  * called before any EEH related functions.
1780  */
1781 static int __init eeh_powernv_init(void)
1782 {
1783         int ret = -EINVAL;
1784 
1785         eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
1786         ret = eeh_ops_register(&pnv_eeh_ops);
1787         if (!ret)
1788                 pr_info("EEH: PowerNV platform initialized\n");
1789         else
1790                 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1791 
1792         return ret;
1793 }
1794 machine_early_initcall(powernv, eeh_powernv_init);
1795 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp