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TOMOYO Linux Cross Reference
Linux/arch/powerpc/platforms/powernv/pci-ioda.c

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  1 /*
  2  * Support PCI/PCIe on PowerNV platforms
  3  *
  4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version
  9  * 2 of the License, or (at your option) any later version.
 10  */
 11 
 12 #undef DEBUG
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/pci.h>
 16 #include <linux/crash_dump.h>
 17 #include <linux/delay.h>
 18 #include <linux/string.h>
 19 #include <linux/init.h>
 20 #include <linux/bootmem.h>
 21 #include <linux/irq.h>
 22 #include <linux/io.h>
 23 #include <linux/msi.h>
 24 #include <linux/memblock.h>
 25 #include <linux/iommu.h>
 26 #include <linux/rculist.h>
 27 #include <linux/sizes.h>
 28 
 29 #include <asm/sections.h>
 30 #include <asm/io.h>
 31 #include <asm/prom.h>
 32 #include <asm/pci-bridge.h>
 33 #include <asm/machdep.h>
 34 #include <asm/msi_bitmap.h>
 35 #include <asm/ppc-pci.h>
 36 #include <asm/opal.h>
 37 #include <asm/iommu.h>
 38 #include <asm/tce.h>
 39 #include <asm/xics.h>
 40 #include <asm/debugfs.h>
 41 #include <asm/firmware.h>
 42 #include <asm/pnv-pci.h>
 43 #include <asm/mmzone.h>
 44 
 45 #include <misc/cxl-base.h>
 46 
 47 #include "powernv.h"
 48 #include "pci.h"
 49 
 50 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
 51 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
 52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
 53 
 54 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
 55 #define POWERNV_IOMMU_MAX_LEVELS        5
 56 
 57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
 58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
 59 
 60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
 61                             const char *fmt, ...)
 62 {
 63         struct va_format vaf;
 64         va_list args;
 65         char pfix[32];
 66 
 67         va_start(args, fmt);
 68 
 69         vaf.fmt = fmt;
 70         vaf.va = &args;
 71 
 72         if (pe->flags & PNV_IODA_PE_DEV)
 73                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
 74         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
 75                 sprintf(pfix, "%04x:%02x     ",
 76                         pci_domain_nr(pe->pbus), pe->pbus->number);
 77 #ifdef CONFIG_PCI_IOV
 78         else if (pe->flags & PNV_IODA_PE_VF)
 79                 sprintf(pfix, "%04x:%02x:%2x.%d",
 80                         pci_domain_nr(pe->parent_dev->bus),
 81                         (pe->rid & 0xff00) >> 8,
 82                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
 83 #endif /* CONFIG_PCI_IOV*/
 84 
 85         printk("%spci %s: [PE# %.2x] %pV",
 86                level, pfix, pe->pe_number, &vaf);
 87 
 88         va_end(args);
 89 }
 90 
 91 static bool pnv_iommu_bypass_disabled __read_mostly;
 92 
 93 static int __init iommu_setup(char *str)
 94 {
 95         if (!str)
 96                 return -EINVAL;
 97 
 98         while (*str) {
 99                 if (!strncmp(str, "nobypass", 8)) {
100                         pnv_iommu_bypass_disabled = true;
101                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
102                         break;
103                 }
104                 str += strcspn(str, ",");
105                 if (*str == ',')
106                         str++;
107         }
108 
109         return 0;
110 }
111 early_param("iommu", iommu_setup);
112 
113 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
114 {
115         /*
116          * WARNING: We cannot rely on the resource flags. The Linux PCI
117          * allocation code sometimes decides to put a 64-bit prefetchable
118          * BAR in the 32-bit window, so we have to compare the addresses.
119          *
120          * For simplicity we only test resource start.
121          */
122         return (r->start >= phb->ioda.m64_base &&
123                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
124 }
125 
126 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
127 {
128         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
129 
130         return (resource_flags & flags) == flags;
131 }
132 
133 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
134 {
135         s64 rc;
136 
137         phb->ioda.pe_array[pe_no].phb = phb;
138         phb->ioda.pe_array[pe_no].pe_number = pe_no;
139 
140         /*
141          * Clear the PE frozen state as it might be put into frozen state
142          * in the last PCI remove path. It's not harmful to do so when the
143          * PE is already in unfrozen state.
144          */
145         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
146                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
147         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
148                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
149                         __func__, rc, phb->hose->global_number, pe_no);
150 
151         return &phb->ioda.pe_array[pe_no];
152 }
153 
154 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
155 {
156         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
157                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
158                         __func__, pe_no, phb->hose->global_number);
159                 return;
160         }
161 
162         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
163                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
164                          __func__, pe_no, phb->hose->global_number);
165 
166         pnv_ioda_init_pe(phb, pe_no);
167 }
168 
169 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
170 {
171         long pe;
172 
173         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
174                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
175                         return pnv_ioda_init_pe(phb, pe);
176         }
177 
178         return NULL;
179 }
180 
181 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
182 {
183         struct pnv_phb *phb = pe->phb;
184         unsigned int pe_num = pe->pe_number;
185 
186         WARN_ON(pe->pdev);
187 
188         memset(pe, 0, sizeof(struct pnv_ioda_pe));
189         clear_bit(pe_num, phb->ioda.pe_alloc);
190 }
191 
192 /* The default M64 BAR is shared by all PEs */
193 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
194 {
195         const char *desc;
196         struct resource *r;
197         s64 rc;
198 
199         /* Configure the default M64 BAR */
200         rc = opal_pci_set_phb_mem_window(phb->opal_id,
201                                          OPAL_M64_WINDOW_TYPE,
202                                          phb->ioda.m64_bar_idx,
203                                          phb->ioda.m64_base,
204                                          0, /* unused */
205                                          phb->ioda.m64_size);
206         if (rc != OPAL_SUCCESS) {
207                 desc = "configuring";
208                 goto fail;
209         }
210 
211         /* Enable the default M64 BAR */
212         rc = opal_pci_phb_mmio_enable(phb->opal_id,
213                                       OPAL_M64_WINDOW_TYPE,
214                                       phb->ioda.m64_bar_idx,
215                                       OPAL_ENABLE_M64_SPLIT);
216         if (rc != OPAL_SUCCESS) {
217                 desc = "enabling";
218                 goto fail;
219         }
220 
221         /*
222          * Exclude the segments for reserved and root bus PE, which
223          * are first or last two PEs.
224          */
225         r = &phb->hose->mem_resources[1];
226         if (phb->ioda.reserved_pe_idx == 0)
227                 r->start += (2 * phb->ioda.m64_segsize);
228         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
229                 r->end -= (2 * phb->ioda.m64_segsize);
230         else
231                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
232                         phb->ioda.reserved_pe_idx);
233 
234         return 0;
235 
236 fail:
237         pr_warn("  Failure %lld %s M64 BAR#%d\n",
238                 rc, desc, phb->ioda.m64_bar_idx);
239         opal_pci_phb_mmio_enable(phb->opal_id,
240                                  OPAL_M64_WINDOW_TYPE,
241                                  phb->ioda.m64_bar_idx,
242                                  OPAL_DISABLE_M64);
243         return -EIO;
244 }
245 
246 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
247                                          unsigned long *pe_bitmap)
248 {
249         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
250         struct pnv_phb *phb = hose->private_data;
251         struct resource *r;
252         resource_size_t base, sgsz, start, end;
253         int segno, i;
254 
255         base = phb->ioda.m64_base;
256         sgsz = phb->ioda.m64_segsize;
257         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
258                 r = &pdev->resource[i];
259                 if (!r->parent || !pnv_pci_is_m64(phb, r))
260                         continue;
261 
262                 start = _ALIGN_DOWN(r->start - base, sgsz);
263                 end = _ALIGN_UP(r->end - base, sgsz);
264                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
265                         if (pe_bitmap)
266                                 set_bit(segno, pe_bitmap);
267                         else
268                                 pnv_ioda_reserve_pe(phb, segno);
269                 }
270         }
271 }
272 
273 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
274 {
275         struct resource *r;
276         int index;
277 
278         /*
279          * There are 16 M64 BARs, each of which has 8 segments. So
280          * there are as many M64 segments as the maximum number of
281          * PEs, which is 128.
282          */
283         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
284                 unsigned long base, segsz = phb->ioda.m64_segsize;
285                 int64_t rc;
286 
287                 base = phb->ioda.m64_base +
288                        index * PNV_IODA1_M64_SEGS * segsz;
289                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
290                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
291                                 PNV_IODA1_M64_SEGS * segsz);
292                 if (rc != OPAL_SUCCESS) {
293                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
294                                 rc, phb->hose->global_number, index);
295                         goto fail;
296                 }
297 
298                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
299                                 OPAL_M64_WINDOW_TYPE, index,
300                                 OPAL_ENABLE_M64_SPLIT);
301                 if (rc != OPAL_SUCCESS) {
302                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
303                                 rc, phb->hose->global_number, index);
304                         goto fail;
305                 }
306         }
307 
308         /*
309          * Exclude the segments for reserved and root bus PE, which
310          * are first or last two PEs.
311          */
312         r = &phb->hose->mem_resources[1];
313         if (phb->ioda.reserved_pe_idx == 0)
314                 r->start += (2 * phb->ioda.m64_segsize);
315         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
316                 r->end -= (2 * phb->ioda.m64_segsize);
317         else
318                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
319                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
320 
321         return 0;
322 
323 fail:
324         for ( ; index >= 0; index--)
325                 opal_pci_phb_mmio_enable(phb->opal_id,
326                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
327 
328         return -EIO;
329 }
330 
331 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
332                                     unsigned long *pe_bitmap,
333                                     bool all)
334 {
335         struct pci_dev *pdev;
336 
337         list_for_each_entry(pdev, &bus->devices, bus_list) {
338                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
339 
340                 if (all && pdev->subordinate)
341                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
342                                                 pe_bitmap, all);
343         }
344 }
345 
346 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
347 {
348         struct pci_controller *hose = pci_bus_to_host(bus);
349         struct pnv_phb *phb = hose->private_data;
350         struct pnv_ioda_pe *master_pe, *pe;
351         unsigned long size, *pe_alloc;
352         int i;
353 
354         /* Root bus shouldn't use M64 */
355         if (pci_is_root_bus(bus))
356                 return NULL;
357 
358         /* Allocate bitmap */
359         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
360         pe_alloc = kzalloc(size, GFP_KERNEL);
361         if (!pe_alloc) {
362                 pr_warn("%s: Out of memory !\n",
363                         __func__);
364                 return NULL;
365         }
366 
367         /* Figure out reserved PE numbers by the PE */
368         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
369 
370         /*
371          * the current bus might not own M64 window and that's all
372          * contributed by its child buses. For the case, we needn't
373          * pick M64 dependent PE#.
374          */
375         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
376                 kfree(pe_alloc);
377                 return NULL;
378         }
379 
380         /*
381          * Figure out the master PE and put all slave PEs to master
382          * PE's list to form compound PE.
383          */
384         master_pe = NULL;
385         i = -1;
386         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
387                 phb->ioda.total_pe_num) {
388                 pe = &phb->ioda.pe_array[i];
389 
390                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
391                 if (!master_pe) {
392                         pe->flags |= PNV_IODA_PE_MASTER;
393                         INIT_LIST_HEAD(&pe->slaves);
394                         master_pe = pe;
395                 } else {
396                         pe->flags |= PNV_IODA_PE_SLAVE;
397                         pe->master = master_pe;
398                         list_add_tail(&pe->list, &master_pe->slaves);
399                 }
400 
401                 /*
402                  * P7IOC supports M64DT, which helps mapping M64 segment
403                  * to one particular PE#. However, PHB3 has fixed mapping
404                  * between M64 segment and PE#. In order to have same logic
405                  * for P7IOC and PHB3, we enforce fixed mapping between M64
406                  * segment and PE# on P7IOC.
407                  */
408                 if (phb->type == PNV_PHB_IODA1) {
409                         int64_t rc;
410 
411                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
412                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
413                                         pe->pe_number / PNV_IODA1_M64_SEGS,
414                                         pe->pe_number % PNV_IODA1_M64_SEGS);
415                         if (rc != OPAL_SUCCESS)
416                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
417                                         __func__, rc, phb->hose->global_number,
418                                         pe->pe_number);
419                 }
420         }
421 
422         kfree(pe_alloc);
423         return master_pe;
424 }
425 
426 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
427 {
428         struct pci_controller *hose = phb->hose;
429         struct device_node *dn = hose->dn;
430         struct resource *res;
431         u32 m64_range[2], i;
432         const __be32 *r;
433         u64 pci_addr;
434 
435         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
436                 pr_info("  Not support M64 window\n");
437                 return;
438         }
439 
440         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
441                 pr_info("  Firmware too old to support M64 window\n");
442                 return;
443         }
444 
445         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
446         if (!r) {
447                 pr_info("  No <ibm,opal-m64-window> on %s\n",
448                         dn->full_name);
449                 return;
450         }
451 
452         /*
453          * Find the available M64 BAR range and pickup the last one for
454          * covering the whole 64-bits space. We support only one range.
455          */
456         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
457                                        m64_range, 2)) {
458                 /* In absence of the property, assume 0..15 */
459                 m64_range[0] = 0;
460                 m64_range[1] = 16;
461         }
462         /* We only support 64 bits in our allocator */
463         if (m64_range[1] > 63) {
464                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
465                         __func__, m64_range[1], phb->hose->global_number);
466                 m64_range[1] = 63;
467         }
468         /* Empty range, no m64 */
469         if (m64_range[1] <= m64_range[0]) {
470                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
471                         __func__, phb->hose->global_number);
472                 return;
473         }
474 
475         /* Configure M64 informations */
476         res = &hose->mem_resources[1];
477         res->name = dn->full_name;
478         res->start = of_translate_address(dn, r + 2);
479         res->end = res->start + of_read_number(r + 4, 2) - 1;
480         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
481         pci_addr = of_read_number(r, 2);
482         hose->mem_offset[1] = res->start - pci_addr;
483 
484         phb->ioda.m64_size = resource_size(res);
485         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
486         phb->ioda.m64_base = pci_addr;
487 
488         /* This lines up nicely with the display from processing OF ranges */
489         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
490                 res->start, res->end, pci_addr, m64_range[0],
491                 m64_range[0] + m64_range[1] - 1);
492 
493         /* Mark all M64 used up by default */
494         phb->ioda.m64_bar_alloc = (unsigned long)-1;
495 
496         /* Use last M64 BAR to cover M64 window */
497         m64_range[1]--;
498         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
499 
500         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
501 
502         /* Mark remaining ones free */
503         for (i = m64_range[0]; i < m64_range[1]; i++)
504                 clear_bit(i, &phb->ioda.m64_bar_alloc);
505 
506         /*
507          * Setup init functions for M64 based on IODA version, IODA3 uses
508          * the IODA2 code.
509          */
510         if (phb->type == PNV_PHB_IODA1)
511                 phb->init_m64 = pnv_ioda1_init_m64;
512         else
513                 phb->init_m64 = pnv_ioda2_init_m64;
514         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
515         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
516 }
517 
518 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
519 {
520         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
521         struct pnv_ioda_pe *slave;
522         s64 rc;
523 
524         /* Fetch master PE */
525         if (pe->flags & PNV_IODA_PE_SLAVE) {
526                 pe = pe->master;
527                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
528                         return;
529 
530                 pe_no = pe->pe_number;
531         }
532 
533         /* Freeze master PE */
534         rc = opal_pci_eeh_freeze_set(phb->opal_id,
535                                      pe_no,
536                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
537         if (rc != OPAL_SUCCESS) {
538                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
539                         __func__, rc, phb->hose->global_number, pe_no);
540                 return;
541         }
542 
543         /* Freeze slave PEs */
544         if (!(pe->flags & PNV_IODA_PE_MASTER))
545                 return;
546 
547         list_for_each_entry(slave, &pe->slaves, list) {
548                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
549                                              slave->pe_number,
550                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
551                 if (rc != OPAL_SUCCESS)
552                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
553                                 __func__, rc, phb->hose->global_number,
554                                 slave->pe_number);
555         }
556 }
557 
558 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
559 {
560         struct pnv_ioda_pe *pe, *slave;
561         s64 rc;
562 
563         /* Find master PE */
564         pe = &phb->ioda.pe_array[pe_no];
565         if (pe->flags & PNV_IODA_PE_SLAVE) {
566                 pe = pe->master;
567                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
568                 pe_no = pe->pe_number;
569         }
570 
571         /* Clear frozen state for master PE */
572         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
573         if (rc != OPAL_SUCCESS) {
574                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
575                         __func__, rc, opt, phb->hose->global_number, pe_no);
576                 return -EIO;
577         }
578 
579         if (!(pe->flags & PNV_IODA_PE_MASTER))
580                 return 0;
581 
582         /* Clear frozen state for slave PEs */
583         list_for_each_entry(slave, &pe->slaves, list) {
584                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
585                                              slave->pe_number,
586                                              opt);
587                 if (rc != OPAL_SUCCESS) {
588                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
589                                 __func__, rc, opt, phb->hose->global_number,
590                                 slave->pe_number);
591                         return -EIO;
592                 }
593         }
594 
595         return 0;
596 }
597 
598 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
599 {
600         struct pnv_ioda_pe *slave, *pe;
601         u8 fstate, state;
602         __be16 pcierr;
603         s64 rc;
604 
605         /* Sanity check on PE number */
606         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
607                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
608 
609         /*
610          * Fetch the master PE and the PE instance might be
611          * not initialized yet.
612          */
613         pe = &phb->ioda.pe_array[pe_no];
614         if (pe->flags & PNV_IODA_PE_SLAVE) {
615                 pe = pe->master;
616                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
617                 pe_no = pe->pe_number;
618         }
619 
620         /* Check the master PE */
621         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
622                                         &state, &pcierr, NULL);
623         if (rc != OPAL_SUCCESS) {
624                 pr_warn("%s: Failure %lld getting "
625                         "PHB#%x-PE#%x state\n",
626                         __func__, rc,
627                         phb->hose->global_number, pe_no);
628                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
629         }
630 
631         /* Check the slave PE */
632         if (!(pe->flags & PNV_IODA_PE_MASTER))
633                 return state;
634 
635         list_for_each_entry(slave, &pe->slaves, list) {
636                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
637                                                 slave->pe_number,
638                                                 &fstate,
639                                                 &pcierr,
640                                                 NULL);
641                 if (rc != OPAL_SUCCESS) {
642                         pr_warn("%s: Failure %lld getting "
643                                 "PHB#%x-PE#%x state\n",
644                                 __func__, rc,
645                                 phb->hose->global_number, slave->pe_number);
646                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
647                 }
648 
649                 /*
650                  * Override the result based on the ascending
651                  * priority.
652                  */
653                 if (fstate > state)
654                         state = fstate;
655         }
656 
657         return state;
658 }
659 
660 /* Currently those 2 are only used when MSIs are enabled, this will change
661  * but in the meantime, we need to protect them to avoid warnings
662  */
663 #ifdef CONFIG_PCI_MSI
664 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
665 {
666         struct pci_controller *hose = pci_bus_to_host(dev->bus);
667         struct pnv_phb *phb = hose->private_data;
668         struct pci_dn *pdn = pci_get_pdn(dev);
669 
670         if (!pdn)
671                 return NULL;
672         if (pdn->pe_number == IODA_INVALID_PE)
673                 return NULL;
674         return &phb->ioda.pe_array[pdn->pe_number];
675 }
676 #endif /* CONFIG_PCI_MSI */
677 
678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
679                                   struct pnv_ioda_pe *parent,
680                                   struct pnv_ioda_pe *child,
681                                   bool is_add)
682 {
683         const char *desc = is_add ? "adding" : "removing";
684         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
685                               OPAL_REMOVE_PE_FROM_DOMAIN;
686         struct pnv_ioda_pe *slave;
687         long rc;
688 
689         /* Parent PE affects child PE */
690         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
691                                 child->pe_number, op);
692         if (rc != OPAL_SUCCESS) {
693                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
694                         rc, desc);
695                 return -ENXIO;
696         }
697 
698         if (!(child->flags & PNV_IODA_PE_MASTER))
699                 return 0;
700 
701         /* Compound case: parent PE affects slave PEs */
702         list_for_each_entry(slave, &child->slaves, list) {
703                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704                                         slave->pe_number, op);
705                 if (rc != OPAL_SUCCESS) {
706                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
707                                 rc, desc);
708                         return -ENXIO;
709                 }
710         }
711 
712         return 0;
713 }
714 
715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
716                               struct pnv_ioda_pe *pe,
717                               bool is_add)
718 {
719         struct pnv_ioda_pe *slave;
720         struct pci_dev *pdev = NULL;
721         int ret;
722 
723         /*
724          * Clear PE frozen state. If it's master PE, we need
725          * clear slave PE frozen state as well.
726          */
727         if (is_add) {
728                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
729                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
730                 if (pe->flags & PNV_IODA_PE_MASTER) {
731                         list_for_each_entry(slave, &pe->slaves, list)
732                                 opal_pci_eeh_freeze_clear(phb->opal_id,
733                                                           slave->pe_number,
734                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
735                 }
736         }
737 
738         /*
739          * Associate PE in PELT. We need add the PE into the
740          * corresponding PELT-V as well. Otherwise, the error
741          * originated from the PE might contribute to other
742          * PEs.
743          */
744         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
745         if (ret)
746                 return ret;
747 
748         /* For compound PEs, any one affects all of them */
749         if (pe->flags & PNV_IODA_PE_MASTER) {
750                 list_for_each_entry(slave, &pe->slaves, list) {
751                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
752                         if (ret)
753                                 return ret;
754                 }
755         }
756 
757         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
758                 pdev = pe->pbus->self;
759         else if (pe->flags & PNV_IODA_PE_DEV)
760                 pdev = pe->pdev->bus->self;
761 #ifdef CONFIG_PCI_IOV
762         else if (pe->flags & PNV_IODA_PE_VF)
763                 pdev = pe->parent_dev;
764 #endif /* CONFIG_PCI_IOV */
765         while (pdev) {
766                 struct pci_dn *pdn = pci_get_pdn(pdev);
767                 struct pnv_ioda_pe *parent;
768 
769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770                         parent = &phb->ioda.pe_array[pdn->pe_number];
771                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
772                         if (ret)
773                                 return ret;
774                 }
775 
776                 pdev = pdev->bus->self;
777         }
778 
779         return 0;
780 }
781 
782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
783 {
784         struct pci_dev *parent;
785         uint8_t bcomp, dcomp, fcomp;
786         int64_t rc;
787         long rid_end, rid;
788 
789         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
790         if (pe->pbus) {
791                 int count;
792 
793                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
794                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
795                 parent = pe->pbus->self;
796                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
797                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
798                 else
799                         count = 1;
800 
801                 switch(count) {
802                 case  1: bcomp = OpalPciBusAll;         break;
803                 case  2: bcomp = OpalPciBus7Bits;       break;
804                 case  4: bcomp = OpalPciBus6Bits;       break;
805                 case  8: bcomp = OpalPciBus5Bits;       break;
806                 case 16: bcomp = OpalPciBus4Bits;       break;
807                 case 32: bcomp = OpalPciBus3Bits;       break;
808                 default:
809                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
810                                 count);
811                         /* Do an exact match only */
812                         bcomp = OpalPciBusAll;
813                 }
814                 rid_end = pe->rid + (count << 8);
815         } else {
816 #ifdef CONFIG_PCI_IOV
817                 if (pe->flags & PNV_IODA_PE_VF)
818                         parent = pe->parent_dev;
819                 else
820 #endif
821                         parent = pe->pdev->bus->self;
822                 bcomp = OpalPciBusAll;
823                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
824                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
825                 rid_end = pe->rid + 1;
826         }
827 
828         /* Clear the reverse map */
829         for (rid = pe->rid; rid < rid_end; rid++)
830                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
831 
832         /* Release from all parents PELT-V */
833         while (parent) {
834                 struct pci_dn *pdn = pci_get_pdn(parent);
835                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
836                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
837                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
838                         /* XXX What to do in case of error ? */
839                 }
840                 parent = parent->bus->self;
841         }
842 
843         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
844                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
845 
846         /* Disassociate PE in PELT */
847         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
848                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
849         if (rc)
850                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
851         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
853         if (rc)
854                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
855 
856         pe->pbus = NULL;
857         pe->pdev = NULL;
858 #ifdef CONFIG_PCI_IOV
859         pe->parent_dev = NULL;
860 #endif
861 
862         return 0;
863 }
864 
865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
866 {
867         struct pci_dev *parent;
868         uint8_t bcomp, dcomp, fcomp;
869         long rc, rid_end, rid;
870 
871         /* Bus validation ? */
872         if (pe->pbus) {
873                 int count;
874 
875                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
876                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
877                 parent = pe->pbus->self;
878                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
879                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
880                 else
881                         count = 1;
882 
883                 switch(count) {
884                 case  1: bcomp = OpalPciBusAll;         break;
885                 case  2: bcomp = OpalPciBus7Bits;       break;
886                 case  4: bcomp = OpalPciBus6Bits;       break;
887                 case  8: bcomp = OpalPciBus5Bits;       break;
888                 case 16: bcomp = OpalPciBus4Bits;       break;
889                 case 32: bcomp = OpalPciBus3Bits;       break;
890                 default:
891                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
892                                 count);
893                         /* Do an exact match only */
894                         bcomp = OpalPciBusAll;
895                 }
896                 rid_end = pe->rid + (count << 8);
897         } else {
898 #ifdef CONFIG_PCI_IOV
899                 if (pe->flags & PNV_IODA_PE_VF)
900                         parent = pe->parent_dev;
901                 else
902 #endif /* CONFIG_PCI_IOV */
903                         parent = pe->pdev->bus->self;
904                 bcomp = OpalPciBusAll;
905                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
906                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
907                 rid_end = pe->rid + 1;
908         }
909 
910         /*
911          * Associate PE in PELT. We need add the PE into the
912          * corresponding PELT-V as well. Otherwise, the error
913          * originated from the PE might contribute to other
914          * PEs.
915          */
916         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
917                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
918         if (rc) {
919                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
920                 return -ENXIO;
921         }
922 
923         /*
924          * Configure PELTV. NPUs don't have a PELTV table so skip
925          * configuration on them.
926          */
927         if (phb->type != PNV_PHB_NPU)
928                 pnv_ioda_set_peltv(phb, pe, true);
929 
930         /* Setup reverse map */
931         for (rid = pe->rid; rid < rid_end; rid++)
932                 phb->ioda.pe_rmap[rid] = pe->pe_number;
933 
934         /* Setup one MVTs on IODA1 */
935         if (phb->type != PNV_PHB_IODA1) {
936                 pe->mve_number = 0;
937                 goto out;
938         }
939 
940         pe->mve_number = pe->pe_number;
941         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
942         if (rc != OPAL_SUCCESS) {
943                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
944                        rc, pe->mve_number);
945                 pe->mve_number = -1;
946         } else {
947                 rc = opal_pci_set_mve_enable(phb->opal_id,
948                                              pe->mve_number, OPAL_ENABLE_MVE);
949                 if (rc) {
950                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
951                                rc, pe->mve_number);
952                         pe->mve_number = -1;
953                 }
954         }
955 
956 out:
957         return 0;
958 }
959 
960 #ifdef CONFIG_PCI_IOV
961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
962 {
963         struct pci_dn *pdn = pci_get_pdn(dev);
964         int i;
965         struct resource *res, res2;
966         resource_size_t size;
967         u16 num_vfs;
968 
969         if (!dev->is_physfn)
970                 return -EINVAL;
971 
972         /*
973          * "offset" is in VFs.  The M64 windows are sized so that when they
974          * are segmented, each segment is the same size as the IOV BAR.
975          * Each segment is in a separate PE, and the high order bits of the
976          * address are the PE number.  Therefore, each VF's BAR is in a
977          * separate PE, and changing the IOV BAR start address changes the
978          * range of PEs the VFs are in.
979          */
980         num_vfs = pdn->num_vfs;
981         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
982                 res = &dev->resource[i + PCI_IOV_RESOURCES];
983                 if (!res->flags || !res->parent)
984                         continue;
985 
986                 /*
987                  * The actual IOV BAR range is determined by the start address
988                  * and the actual size for num_vfs VFs BAR.  This check is to
989                  * make sure that after shifting, the range will not overlap
990                  * with another device.
991                  */
992                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
993                 res2.flags = res->flags;
994                 res2.start = res->start + (size * offset);
995                 res2.end = res2.start + (size * num_vfs) - 1;
996 
997                 if (res2.end > res->end) {
998                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999                                 i, &res2, res, num_vfs, offset);
1000                         return -EBUSY;
1001                 }
1002         }
1003 
1004         /*
1005          * After doing so, there would be a "hole" in the /proc/iomem when
1006          * offset is a positive value. It looks like the device return some
1007          * mmio back to the system, which actually no one could use it.
1008          */
1009         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1010                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1011                 if (!res->flags || !res->parent)
1012                         continue;
1013 
1014                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1015                 res2 = *res;
1016                 res->start += size * offset;
1017 
1018                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1019                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1020                          num_vfs, offset);
1021                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1022         }
1023         return 0;
1024 }
1025 #endif /* CONFIG_PCI_IOV */
1026 
1027 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1028 {
1029         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1030         struct pnv_phb *phb = hose->private_data;
1031         struct pci_dn *pdn = pci_get_pdn(dev);
1032         struct pnv_ioda_pe *pe;
1033 
1034         if (!pdn) {
1035                 pr_err("%s: Device tree node not associated properly\n",
1036                            pci_name(dev));
1037                 return NULL;
1038         }
1039         if (pdn->pe_number != IODA_INVALID_PE)
1040                 return NULL;
1041 
1042         pe = pnv_ioda_alloc_pe(phb);
1043         if (!pe) {
1044                 pr_warning("%s: Not enough PE# available, disabling device\n",
1045                            pci_name(dev));
1046                 return NULL;
1047         }
1048 
1049         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1050          * pointer in the PE data structure, both should be destroyed at the
1051          * same time. However, this needs to be looked at more closely again
1052          * once we actually start removing things (Hotplug, SR-IOV, ...)
1053          *
1054          * At some point we want to remove the PDN completely anyways
1055          */
1056         pci_dev_get(dev);
1057         pdn->pcidev = dev;
1058         pdn->pe_number = pe->pe_number;
1059         pe->flags = PNV_IODA_PE_DEV;
1060         pe->pdev = dev;
1061         pe->pbus = NULL;
1062         pe->mve_number = -1;
1063         pe->rid = dev->bus->number << 8 | pdn->devfn;
1064 
1065         pe_info(pe, "Associated device to PE\n");
1066 
1067         if (pnv_ioda_configure_pe(phb, pe)) {
1068                 /* XXX What do we do here ? */
1069                 pnv_ioda_free_pe(pe);
1070                 pdn->pe_number = IODA_INVALID_PE;
1071                 pe->pdev = NULL;
1072                 pci_dev_put(dev);
1073                 return NULL;
1074         }
1075 
1076         /* Put PE to the list */
1077         list_add_tail(&pe->list, &phb->ioda.pe_list);
1078 
1079         return pe;
1080 }
1081 
1082 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1083 {
1084         struct pci_dev *dev;
1085 
1086         list_for_each_entry(dev, &bus->devices, bus_list) {
1087                 struct pci_dn *pdn = pci_get_pdn(dev);
1088 
1089                 if (pdn == NULL) {
1090                         pr_warn("%s: No device node associated with device !\n",
1091                                 pci_name(dev));
1092                         continue;
1093                 }
1094 
1095                 /*
1096                  * In partial hotplug case, the PCI device might be still
1097                  * associated with the PE and needn't attach it to the PE
1098                  * again.
1099                  */
1100                 if (pdn->pe_number != IODA_INVALID_PE)
1101                         continue;
1102 
1103                 pe->device_count++;
1104                 pdn->pcidev = dev;
1105                 pdn->pe_number = pe->pe_number;
1106                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1107                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1108         }
1109 }
1110 
1111 /*
1112  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1113  * single PCI bus. Another one that contains the primary PCI bus and its
1114  * subordinate PCI devices and buses. The second type of PE is normally
1115  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1116  */
1117 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1118 {
1119         struct pci_controller *hose = pci_bus_to_host(bus);
1120         struct pnv_phb *phb = hose->private_data;
1121         struct pnv_ioda_pe *pe = NULL;
1122         unsigned int pe_num;
1123 
1124         /*
1125          * In partial hotplug case, the PE instance might be still alive.
1126          * We should reuse it instead of allocating a new one.
1127          */
1128         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1129         if (pe_num != IODA_INVALID_PE) {
1130                 pe = &phb->ioda.pe_array[pe_num];
1131                 pnv_ioda_setup_same_PE(bus, pe);
1132                 return NULL;
1133         }
1134 
1135         /* PE number for root bus should have been reserved */
1136         if (pci_is_root_bus(bus) &&
1137             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1138                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1139 
1140         /* Check if PE is determined by M64 */
1141         if (!pe && phb->pick_m64_pe)
1142                 pe = phb->pick_m64_pe(bus, all);
1143 
1144         /* The PE number isn't pinned by M64 */
1145         if (!pe)
1146                 pe = pnv_ioda_alloc_pe(phb);
1147 
1148         if (!pe) {
1149                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1150                         __func__, pci_domain_nr(bus), bus->number);
1151                 return NULL;
1152         }
1153 
1154         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1155         pe->pbus = bus;
1156         pe->pdev = NULL;
1157         pe->mve_number = -1;
1158         pe->rid = bus->busn_res.start << 8;
1159 
1160         if (all)
1161                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1162                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1163         else
1164                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1165                         bus->busn_res.start, pe->pe_number);
1166 
1167         if (pnv_ioda_configure_pe(phb, pe)) {
1168                 /* XXX What do we do here ? */
1169                 pnv_ioda_free_pe(pe);
1170                 pe->pbus = NULL;
1171                 return NULL;
1172         }
1173 
1174         /* Associate it with all child devices */
1175         pnv_ioda_setup_same_PE(bus, pe);
1176 
1177         /* Put PE to the list */
1178         list_add_tail(&pe->list, &phb->ioda.pe_list);
1179 
1180         return pe;
1181 }
1182 
1183 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1184 {
1185         int pe_num, found_pe = false, rc;
1186         long rid;
1187         struct pnv_ioda_pe *pe;
1188         struct pci_dev *gpu_pdev;
1189         struct pci_dn *npu_pdn;
1190         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1191         struct pnv_phb *phb = hose->private_data;
1192 
1193         /*
1194          * Due to a hardware errata PE#0 on the NPU is reserved for
1195          * error handling. This means we only have three PEs remaining
1196          * which need to be assigned to four links, implying some
1197          * links must share PEs.
1198          *
1199          * To achieve this we assign PEs such that NPUs linking the
1200          * same GPU get assigned the same PE.
1201          */
1202         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1203         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1204                 pe = &phb->ioda.pe_array[pe_num];
1205                 if (!pe->pdev)
1206                         continue;
1207 
1208                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1209                         /*
1210                          * This device has the same peer GPU so should
1211                          * be assigned the same PE as the existing
1212                          * peer NPU.
1213                          */
1214                         dev_info(&npu_pdev->dev,
1215                                 "Associating to existing PE %x\n", pe_num);
1216                         pci_dev_get(npu_pdev);
1217                         npu_pdn = pci_get_pdn(npu_pdev);
1218                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1219                         npu_pdn->pcidev = npu_pdev;
1220                         npu_pdn->pe_number = pe_num;
1221                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1222 
1223                         /* Map the PE to this link */
1224                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1225                                         OpalPciBusAll,
1226                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1227                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1228                                         OPAL_MAP_PE);
1229                         WARN_ON(rc != OPAL_SUCCESS);
1230                         found_pe = true;
1231                         break;
1232                 }
1233         }
1234 
1235         if (!found_pe)
1236                 /*
1237                  * Could not find an existing PE so allocate a new
1238                  * one.
1239                  */
1240                 return pnv_ioda_setup_dev_PE(npu_pdev);
1241         else
1242                 return pe;
1243 }
1244 
1245 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1246 {
1247         struct pci_dev *pdev;
1248 
1249         list_for_each_entry(pdev, &bus->devices, bus_list)
1250                 pnv_ioda_setup_npu_PE(pdev);
1251 }
1252 
1253 static void pnv_pci_ioda_setup_PEs(void)
1254 {
1255         struct pci_controller *hose, *tmp;
1256         struct pnv_phb *phb;
1257 
1258         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1259                 phb = hose->private_data;
1260                 if (phb->type == PNV_PHB_NPU) {
1261                         /* PE#0 is needed for error reporting */
1262                         pnv_ioda_reserve_pe(phb, 0);
1263                         pnv_ioda_setup_npu_PEs(hose->bus);
1264                         if (phb->model == PNV_PHB_MODEL_NPU2)
1265                                 pnv_npu2_init(phb);
1266                 }
1267         }
1268 }
1269 
1270 #ifdef CONFIG_PCI_IOV
1271 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1272 {
1273         struct pci_bus        *bus;
1274         struct pci_controller *hose;
1275         struct pnv_phb        *phb;
1276         struct pci_dn         *pdn;
1277         int                    i, j;
1278         int                    m64_bars;
1279 
1280         bus = pdev->bus;
1281         hose = pci_bus_to_host(bus);
1282         phb = hose->private_data;
1283         pdn = pci_get_pdn(pdev);
1284 
1285         if (pdn->m64_single_mode)
1286                 m64_bars = num_vfs;
1287         else
1288                 m64_bars = 1;
1289 
1290         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1291                 for (j = 0; j < m64_bars; j++) {
1292                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1293                                 continue;
1294                         opal_pci_phb_mmio_enable(phb->opal_id,
1295                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1296                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1297                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1298                 }
1299 
1300         kfree(pdn->m64_map);
1301         return 0;
1302 }
1303 
1304 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1305 {
1306         struct pci_bus        *bus;
1307         struct pci_controller *hose;
1308         struct pnv_phb        *phb;
1309         struct pci_dn         *pdn;
1310         unsigned int           win;
1311         struct resource       *res;
1312         int                    i, j;
1313         int64_t                rc;
1314         int                    total_vfs;
1315         resource_size_t        size, start;
1316         int                    pe_num;
1317         int                    m64_bars;
1318 
1319         bus = pdev->bus;
1320         hose = pci_bus_to_host(bus);
1321         phb = hose->private_data;
1322         pdn = pci_get_pdn(pdev);
1323         total_vfs = pci_sriov_get_totalvfs(pdev);
1324 
1325         if (pdn->m64_single_mode)
1326                 m64_bars = num_vfs;
1327         else
1328                 m64_bars = 1;
1329 
1330         pdn->m64_map = kmalloc_array(m64_bars,
1331                                      sizeof(*pdn->m64_map),
1332                                      GFP_KERNEL);
1333         if (!pdn->m64_map)
1334                 return -ENOMEM;
1335         /* Initialize the m64_map to IODA_INVALID_M64 */
1336         for (i = 0; i < m64_bars ; i++)
1337                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1338                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1339 
1340 
1341         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1342                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1343                 if (!res->flags || !res->parent)
1344                         continue;
1345 
1346                 for (j = 0; j < m64_bars; j++) {
1347                         do {
1348                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1349                                                 phb->ioda.m64_bar_idx + 1, 0);
1350 
1351                                 if (win >= phb->ioda.m64_bar_idx + 1)
1352                                         goto m64_failed;
1353                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1354 
1355                         pdn->m64_map[j][i] = win;
1356 
1357                         if (pdn->m64_single_mode) {
1358                                 size = pci_iov_resource_size(pdev,
1359                                                         PCI_IOV_RESOURCES + i);
1360                                 start = res->start + size * j;
1361                         } else {
1362                                 size = resource_size(res);
1363                                 start = res->start;
1364                         }
1365 
1366                         /* Map the M64 here */
1367                         if (pdn->m64_single_mode) {
1368                                 pe_num = pdn->pe_num_map[j];
1369                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1370                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1371                                                 pdn->m64_map[j][i], 0);
1372                         }
1373 
1374                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1375                                                  OPAL_M64_WINDOW_TYPE,
1376                                                  pdn->m64_map[j][i],
1377                                                  start,
1378                                                  0, /* unused */
1379                                                  size);
1380 
1381 
1382                         if (rc != OPAL_SUCCESS) {
1383                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1384                                         win, rc);
1385                                 goto m64_failed;
1386                         }
1387 
1388                         if (pdn->m64_single_mode)
1389                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1390                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1391                         else
1392                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1393                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1394 
1395                         if (rc != OPAL_SUCCESS) {
1396                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1397                                         win, rc);
1398                                 goto m64_failed;
1399                         }
1400                 }
1401         }
1402         return 0;
1403 
1404 m64_failed:
1405         pnv_pci_vf_release_m64(pdev, num_vfs);
1406         return -EBUSY;
1407 }
1408 
1409 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1410                 int num);
1411 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1412 
1413 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1414 {
1415         struct iommu_table    *tbl;
1416         int64_t               rc;
1417 
1418         tbl = pe->table_group.tables[0];
1419         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1420         if (rc)
1421                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1422 
1423         pnv_pci_ioda2_set_bypass(pe, false);
1424         if (pe->table_group.group) {
1425                 iommu_group_put(pe->table_group.group);
1426                 BUG_ON(pe->table_group.group);
1427         }
1428         iommu_tce_table_put(tbl);
1429 }
1430 
1431 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1432 {
1433         struct pci_bus        *bus;
1434         struct pci_controller *hose;
1435         struct pnv_phb        *phb;
1436         struct pnv_ioda_pe    *pe, *pe_n;
1437         struct pci_dn         *pdn;
1438 
1439         bus = pdev->bus;
1440         hose = pci_bus_to_host(bus);
1441         phb = hose->private_data;
1442         pdn = pci_get_pdn(pdev);
1443 
1444         if (!pdev->is_physfn)
1445                 return;
1446 
1447         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1448                 if (pe->parent_dev != pdev)
1449                         continue;
1450 
1451                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1452 
1453                 /* Remove from list */
1454                 mutex_lock(&phb->ioda.pe_list_mutex);
1455                 list_del(&pe->list);
1456                 mutex_unlock(&phb->ioda.pe_list_mutex);
1457 
1458                 pnv_ioda_deconfigure_pe(phb, pe);
1459 
1460                 pnv_ioda_free_pe(pe);
1461         }
1462 }
1463 
1464 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1465 {
1466         struct pci_bus        *bus;
1467         struct pci_controller *hose;
1468         struct pnv_phb        *phb;
1469         struct pnv_ioda_pe    *pe;
1470         struct pci_dn         *pdn;
1471         u16                    num_vfs, i;
1472 
1473         bus = pdev->bus;
1474         hose = pci_bus_to_host(bus);
1475         phb = hose->private_data;
1476         pdn = pci_get_pdn(pdev);
1477         num_vfs = pdn->num_vfs;
1478 
1479         /* Release VF PEs */
1480         pnv_ioda_release_vf_PE(pdev);
1481 
1482         if (phb->type == PNV_PHB_IODA2) {
1483                 if (!pdn->m64_single_mode)
1484                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1485 
1486                 /* Release M64 windows */
1487                 pnv_pci_vf_release_m64(pdev, num_vfs);
1488 
1489                 /* Release PE numbers */
1490                 if (pdn->m64_single_mode) {
1491                         for (i = 0; i < num_vfs; i++) {
1492                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1493                                         continue;
1494 
1495                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1496                                 pnv_ioda_free_pe(pe);
1497                         }
1498                 } else
1499                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1500                 /* Releasing pe_num_map */
1501                 kfree(pdn->pe_num_map);
1502         }
1503 }
1504 
1505 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1506                                        struct pnv_ioda_pe *pe);
1507 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1508 {
1509         struct pci_bus        *bus;
1510         struct pci_controller *hose;
1511         struct pnv_phb        *phb;
1512         struct pnv_ioda_pe    *pe;
1513         int                    pe_num;
1514         u16                    vf_index;
1515         struct pci_dn         *pdn;
1516 
1517         bus = pdev->bus;
1518         hose = pci_bus_to_host(bus);
1519         phb = hose->private_data;
1520         pdn = pci_get_pdn(pdev);
1521 
1522         if (!pdev->is_physfn)
1523                 return;
1524 
1525         /* Reserve PE for each VF */
1526         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1527                 if (pdn->m64_single_mode)
1528                         pe_num = pdn->pe_num_map[vf_index];
1529                 else
1530                         pe_num = *pdn->pe_num_map + vf_index;
1531 
1532                 pe = &phb->ioda.pe_array[pe_num];
1533                 pe->pe_number = pe_num;
1534                 pe->phb = phb;
1535                 pe->flags = PNV_IODA_PE_VF;
1536                 pe->pbus = NULL;
1537                 pe->parent_dev = pdev;
1538                 pe->mve_number = -1;
1539                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1540                            pci_iov_virtfn_devfn(pdev, vf_index);
1541 
1542                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1543                         hose->global_number, pdev->bus->number,
1544                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1545                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1546 
1547                 if (pnv_ioda_configure_pe(phb, pe)) {
1548                         /* XXX What do we do here ? */
1549                         pnv_ioda_free_pe(pe);
1550                         pe->pdev = NULL;
1551                         continue;
1552                 }
1553 
1554                 /* Put PE to the list */
1555                 mutex_lock(&phb->ioda.pe_list_mutex);
1556                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1557                 mutex_unlock(&phb->ioda.pe_list_mutex);
1558 
1559                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1560         }
1561 }
1562 
1563 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1564 {
1565         struct pci_bus        *bus;
1566         struct pci_controller *hose;
1567         struct pnv_phb        *phb;
1568         struct pnv_ioda_pe    *pe;
1569         struct pci_dn         *pdn;
1570         int                    ret;
1571         u16                    i;
1572 
1573         bus = pdev->bus;
1574         hose = pci_bus_to_host(bus);
1575         phb = hose->private_data;
1576         pdn = pci_get_pdn(pdev);
1577 
1578         if (phb->type == PNV_PHB_IODA2) {
1579                 if (!pdn->vfs_expanded) {
1580                         dev_info(&pdev->dev, "don't support this SRIOV device"
1581                                 " with non 64bit-prefetchable IOV BAR\n");
1582                         return -ENOSPC;
1583                 }
1584 
1585                 /*
1586                  * When M64 BARs functions in Single PE mode, the number of VFs
1587                  * could be enabled must be less than the number of M64 BARs.
1588                  */
1589                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1590                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1591                         return -EBUSY;
1592                 }
1593 
1594                 /* Allocating pe_num_map */
1595                 if (pdn->m64_single_mode)
1596                         pdn->pe_num_map = kmalloc_array(num_vfs,
1597                                                         sizeof(*pdn->pe_num_map),
1598                                                         GFP_KERNEL);
1599                 else
1600                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1601 
1602                 if (!pdn->pe_num_map)
1603                         return -ENOMEM;
1604 
1605                 if (pdn->m64_single_mode)
1606                         for (i = 0; i < num_vfs; i++)
1607                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1608 
1609                 /* Calculate available PE for required VFs */
1610                 if (pdn->m64_single_mode) {
1611                         for (i = 0; i < num_vfs; i++) {
1612                                 pe = pnv_ioda_alloc_pe(phb);
1613                                 if (!pe) {
1614                                         ret = -EBUSY;
1615                                         goto m64_failed;
1616                                 }
1617 
1618                                 pdn->pe_num_map[i] = pe->pe_number;
1619                         }
1620                 } else {
1621                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1622                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1623                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1624                                 0, num_vfs, 0);
1625                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1626                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1627                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1628                                 kfree(pdn->pe_num_map);
1629                                 return -EBUSY;
1630                         }
1631                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1632                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1633                 }
1634                 pdn->num_vfs = num_vfs;
1635 
1636                 /* Assign M64 window accordingly */
1637                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1638                 if (ret) {
1639                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1640                         goto m64_failed;
1641                 }
1642 
1643                 /*
1644                  * When using one M64 BAR to map one IOV BAR, we need to shift
1645                  * the IOV BAR according to the PE# allocated to the VFs.
1646                  * Otherwise, the PE# for the VF will conflict with others.
1647                  */
1648                 if (!pdn->m64_single_mode) {
1649                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1650                         if (ret)
1651                                 goto m64_failed;
1652                 }
1653         }
1654 
1655         /* Setup VF PEs */
1656         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1657 
1658         return 0;
1659 
1660 m64_failed:
1661         if (pdn->m64_single_mode) {
1662                 for (i = 0; i < num_vfs; i++) {
1663                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1664                                 continue;
1665 
1666                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1667                         pnv_ioda_free_pe(pe);
1668                 }
1669         } else
1670                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1671 
1672         /* Releasing pe_num_map */
1673         kfree(pdn->pe_num_map);
1674 
1675         return ret;
1676 }
1677 
1678 int pcibios_sriov_disable(struct pci_dev *pdev)
1679 {
1680         pnv_pci_sriov_disable(pdev);
1681 
1682         /* Release PCI data */
1683         remove_dev_pci_data(pdev);
1684         return 0;
1685 }
1686 
1687 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1688 {
1689         /* Allocate PCI data */
1690         add_dev_pci_data(pdev);
1691 
1692         return pnv_pci_sriov_enable(pdev, num_vfs);
1693 }
1694 #endif /* CONFIG_PCI_IOV */
1695 
1696 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1697 {
1698         struct pci_dn *pdn = pci_get_pdn(pdev);
1699         struct pnv_ioda_pe *pe;
1700 
1701         /*
1702          * The function can be called while the PE#
1703          * hasn't been assigned. Do nothing for the
1704          * case.
1705          */
1706         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1707                 return;
1708 
1709         pe = &phb->ioda.pe_array[pdn->pe_number];
1710         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1711         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1712         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1713         /*
1714          * Note: iommu_add_device() will fail here as
1715          * for physical PE: the device is already added by now;
1716          * for virtual PE: sysfs entries are not ready yet and
1717          * tce_iommu_bus_notifier will add the device to a group later.
1718          */
1719 }
1720 
1721 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1722 {
1723         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1724         struct pnv_phb *phb = hose->private_data;
1725         struct pci_dn *pdn = pci_get_pdn(pdev);
1726         struct pnv_ioda_pe *pe;
1727         uint64_t top;
1728         bool bypass = false;
1729 
1730         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1731                 return -ENODEV;;
1732 
1733         pe = &phb->ioda.pe_array[pdn->pe_number];
1734         if (pe->tce_bypass_enabled) {
1735                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1736                 bypass = (dma_mask >= top);
1737         }
1738 
1739         if (bypass) {
1740                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1741                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1742         } else {
1743                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1744                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1745         }
1746         *pdev->dev.dma_mask = dma_mask;
1747 
1748         /* Update peer npu devices */
1749         pnv_npu_try_dma_set_bypass(pdev, bypass);
1750 
1751         return 0;
1752 }
1753 
1754 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1755 {
1756         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1757         struct pnv_phb *phb = hose->private_data;
1758         struct pci_dn *pdn = pci_get_pdn(pdev);
1759         struct pnv_ioda_pe *pe;
1760         u64 end, mask;
1761 
1762         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1763                 return 0;
1764 
1765         pe = &phb->ioda.pe_array[pdn->pe_number];
1766         if (!pe->tce_bypass_enabled)
1767                 return __dma_get_required_mask(&pdev->dev);
1768 
1769 
1770         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1771         mask = 1ULL << (fls64(end) - 1);
1772         mask += mask - 1;
1773 
1774         return mask;
1775 }
1776 
1777 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1778                                    struct pci_bus *bus,
1779                                    bool add_to_group)
1780 {
1781         struct pci_dev *dev;
1782 
1783         list_for_each_entry(dev, &bus->devices, bus_list) {
1784                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1785                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1786                 if (add_to_group)
1787                         iommu_add_device(&dev->dev);
1788 
1789                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1790                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1791                                         add_to_group);
1792         }
1793 }
1794 
1795 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1796                                                      bool real_mode)
1797 {
1798         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1799                 (phb->regs + 0x210);
1800 }
1801 
1802 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1803                 unsigned long index, unsigned long npages, bool rm)
1804 {
1805         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1806                         &tbl->it_group_list, struct iommu_table_group_link,
1807                         next);
1808         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1809                         struct pnv_ioda_pe, table_group);
1810         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1811         unsigned long start, end, inc;
1812 
1813         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1814         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1815                         npages - 1);
1816 
1817         /* p7ioc-style invalidation, 2 TCEs per write */
1818         start |= (1ull << 63);
1819         end |= (1ull << 63);
1820         inc = 16;
1821         end |= inc - 1; /* round up end to be different than start */
1822 
1823         mb(); /* Ensure above stores are visible */
1824         while (start <= end) {
1825                 if (rm)
1826                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1827                 else
1828                         __raw_writeq(cpu_to_be64(start), invalidate);
1829                 start += inc;
1830         }
1831 
1832         /*
1833          * The iommu layer will do another mb() for us on build()
1834          * and we don't care on free()
1835          */
1836 }
1837 
1838 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1839                 long npages, unsigned long uaddr,
1840                 enum dma_data_direction direction,
1841                 unsigned long attrs)
1842 {
1843         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1844                         attrs);
1845 
1846         if (!ret)
1847                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1848 
1849         return ret;
1850 }
1851 
1852 #ifdef CONFIG_IOMMU_API
1853 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1854                 unsigned long *hpa, enum dma_data_direction *direction)
1855 {
1856         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1857 
1858         if (!ret)
1859                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1860 
1861         return ret;
1862 }
1863 
1864 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1865                 unsigned long *hpa, enum dma_data_direction *direction)
1866 {
1867         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1868 
1869         if (!ret)
1870                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
1871 
1872         return ret;
1873 }
1874 #endif
1875 
1876 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1877                 long npages)
1878 {
1879         pnv_tce_free(tbl, index, npages);
1880 
1881         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1882 }
1883 
1884 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1885         .set = pnv_ioda1_tce_build,
1886 #ifdef CONFIG_IOMMU_API
1887         .exchange = pnv_ioda1_tce_xchg,
1888         .exchange_rm = pnv_ioda1_tce_xchg_rm,
1889 #endif
1890         .clear = pnv_ioda1_tce_free,
1891         .get = pnv_tce_get,
1892 };
1893 
1894 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1895 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1896 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1897 
1898 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1899 {
1900         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1901         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1902 
1903         mb(); /* Ensure previous TCE table stores are visible */
1904         if (rm)
1905                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1906         else
1907                 __raw_writeq(cpu_to_be64(val), invalidate);
1908 }
1909 
1910 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1911 {
1912         /* 01xb - invalidate TCEs that match the specified PE# */
1913         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1914         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1915 
1916         mb(); /* Ensure above stores are visible */
1917         __raw_writeq(cpu_to_be64(val), invalidate);
1918 }
1919 
1920 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1921                                         unsigned shift, unsigned long index,
1922                                         unsigned long npages)
1923 {
1924         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1925         unsigned long start, end, inc;
1926 
1927         /* We'll invalidate DMA address in PE scope */
1928         start = PHB3_TCE_KILL_INVAL_ONE;
1929         start |= (pe->pe_number & 0xFF);
1930         end = start;
1931 
1932         /* Figure out the start, end and step */
1933         start |= (index << shift);
1934         end |= ((index + npages - 1) << shift);
1935         inc = (0x1ull << shift);
1936         mb();
1937 
1938         while (start <= end) {
1939                 if (rm)
1940                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1941                 else
1942                         __raw_writeq(cpu_to_be64(start), invalidate);
1943                 start += inc;
1944         }
1945 }
1946 
1947 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1948 {
1949         struct pnv_phb *phb = pe->phb;
1950 
1951         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1952                 pnv_pci_phb3_tce_invalidate_pe(pe);
1953         else
1954                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1955                                   pe->pe_number, 0, 0, 0);
1956 }
1957 
1958 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1959                 unsigned long index, unsigned long npages, bool rm)
1960 {
1961         struct iommu_table_group_link *tgl;
1962 
1963         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
1964                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1965                                 struct pnv_ioda_pe, table_group);
1966                 struct pnv_phb *phb = pe->phb;
1967                 unsigned int shift = tbl->it_page_shift;
1968 
1969                 /*
1970                  * NVLink1 can use the TCE kill register directly as
1971                  * it's the same as PHB3. NVLink2 is different and
1972                  * should go via the OPAL call.
1973                  */
1974                 if (phb->model == PNV_PHB_MODEL_NPU) {
1975                         /*
1976                          * The NVLink hardware does not support TCE kill
1977                          * per TCE entry so we have to invalidate
1978                          * the entire cache for it.
1979                          */
1980                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1981                         continue;
1982                 }
1983                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1984                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1985                                                     index, npages);
1986                 else
1987                         opal_pci_tce_kill(phb->opal_id,
1988                                           OPAL_PCI_TCE_KILL_PAGES,
1989                                           pe->pe_number, 1u << shift,
1990                                           index << shift, npages);
1991         }
1992 }
1993 
1994 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1995 {
1996         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
1997                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1998         else
1999                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2000 }
2001 
2002 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2003                 long npages, unsigned long uaddr,
2004                 enum dma_data_direction direction,
2005                 unsigned long attrs)
2006 {
2007         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2008                         attrs);
2009 
2010         if (!ret)
2011                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2012 
2013         return ret;
2014 }
2015 
2016 #ifdef CONFIG_IOMMU_API
2017 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2018                 unsigned long *hpa, enum dma_data_direction *direction)
2019 {
2020         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2021 
2022         if (!ret)
2023                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2024 
2025         return ret;
2026 }
2027 
2028 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2029                 unsigned long *hpa, enum dma_data_direction *direction)
2030 {
2031         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2032 
2033         if (!ret)
2034                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2035 
2036         return ret;
2037 }
2038 #endif
2039 
2040 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2041                 long npages)
2042 {
2043         pnv_tce_free(tbl, index, npages);
2044 
2045         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2046 }
2047 
2048 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2049 {
2050         pnv_pci_ioda2_table_free_pages(tbl);
2051 }
2052 
2053 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2054         .set = pnv_ioda2_tce_build,
2055 #ifdef CONFIG_IOMMU_API
2056         .exchange = pnv_ioda2_tce_xchg,
2057         .exchange_rm = pnv_ioda2_tce_xchg_rm,
2058 #endif
2059         .clear = pnv_ioda2_tce_free,
2060         .get = pnv_tce_get,
2061         .free = pnv_ioda2_table_free,
2062 };
2063 
2064 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2065 {
2066         unsigned int *weight = (unsigned int *)data;
2067 
2068         /* This is quite simplistic. The "base" weight of a device
2069          * is 10. 0 means no DMA is to be accounted for it.
2070          */
2071         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2072                 return 0;
2073 
2074         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2075             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2076             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2077                 *weight += 3;
2078         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2079                 *weight += 15;
2080         else
2081                 *weight += 10;
2082 
2083         return 0;
2084 }
2085 
2086 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2087 {
2088         unsigned int weight = 0;
2089 
2090         /* SRIOV VF has same DMA32 weight as its PF */
2091 #ifdef CONFIG_PCI_IOV
2092         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2093                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2094                 return weight;
2095         }
2096 #endif
2097 
2098         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2099                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2100         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2101                 struct pci_dev *pdev;
2102 
2103                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2104                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2105         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2106                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2107         }
2108 
2109         return weight;
2110 }
2111 
2112 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2113                                        struct pnv_ioda_pe *pe)
2114 {
2115 
2116         struct page *tce_mem = NULL;
2117         struct iommu_table *tbl;
2118         unsigned int weight, total_weight = 0;
2119         unsigned int tce32_segsz, base, segs, avail, i;
2120         int64_t rc;
2121         void *addr;
2122 
2123         /* XXX FIXME: Handle 64-bit only DMA devices */
2124         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2125         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2126         weight = pnv_pci_ioda_pe_dma_weight(pe);
2127         if (!weight)
2128                 return;
2129 
2130         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2131                      &total_weight);
2132         segs = (weight * phb->ioda.dma32_count) / total_weight;
2133         if (!segs)
2134                 segs = 1;
2135 
2136         /*
2137          * Allocate contiguous DMA32 segments. We begin with the expected
2138          * number of segments. With one more attempt, the number of DMA32
2139          * segments to be allocated is decreased by one until one segment
2140          * is allocated successfully.
2141          */
2142         do {
2143                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2144                         for (avail = 0, i = base; i < base + segs; i++) {
2145                                 if (phb->ioda.dma32_segmap[i] ==
2146                                     IODA_INVALID_PE)
2147                                         avail++;
2148                         }
2149 
2150                         if (avail == segs)
2151                                 goto found;
2152                 }
2153         } while (--segs);
2154 
2155         if (!segs) {
2156                 pe_warn(pe, "No available DMA32 segments\n");
2157                 return;
2158         }
2159 
2160 found:
2161         tbl = pnv_pci_table_alloc(phb->hose->node);
2162         if (WARN_ON(!tbl))
2163                 return;
2164 
2165         iommu_register_group(&pe->table_group, phb->hose->global_number,
2166                         pe->pe_number);
2167         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2168 
2169         /* Grab a 32-bit TCE table */
2170         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2171                 weight, total_weight, base, segs);
2172         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2173                 base * PNV_IODA1_DMA32_SEGSIZE,
2174                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2175 
2176         /* XXX Currently, we allocate one big contiguous table for the
2177          * TCEs. We only really need one chunk per 256M of TCE space
2178          * (ie per segment) but that's an optimization for later, it
2179          * requires some added smarts with our get/put_tce implementation
2180          *
2181          * Each TCE page is 4KB in size and each TCE entry occupies 8
2182          * bytes
2183          */
2184         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2185         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2186                                    get_order(tce32_segsz * segs));
2187         if (!tce_mem) {
2188                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2189                 goto fail;
2190         }
2191         addr = page_address(tce_mem);
2192         memset(addr, 0, tce32_segsz * segs);
2193 
2194         /* Configure HW */
2195         for (i = 0; i < segs; i++) {
2196                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2197                                               pe->pe_number,
2198                                               base + i, 1,
2199                                               __pa(addr) + tce32_segsz * i,
2200                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2201                 if (rc) {
2202                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2203                                " err %ld\n", rc);
2204                         goto fail;
2205                 }
2206         }
2207 
2208         /* Setup DMA32 segment mapping */
2209         for (i = base; i < base + segs; i++)
2210                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2211 
2212         /* Setup linux iommu table */
2213         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2214                                   base * PNV_IODA1_DMA32_SEGSIZE,
2215                                   IOMMU_PAGE_SHIFT_4K);
2216 
2217         tbl->it_ops = &pnv_ioda1_iommu_ops;
2218         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2219         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2220         iommu_init_table(tbl, phb->hose->node);
2221 
2222         if (pe->flags & PNV_IODA_PE_DEV) {
2223                 /*
2224                  * Setting table base here only for carrying iommu_group
2225                  * further down to let iommu_add_device() do the job.
2226                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2227                  */
2228                 set_iommu_table_base(&pe->pdev->dev, tbl);
2229                 iommu_add_device(&pe->pdev->dev);
2230         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2231                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2232 
2233         return;
2234  fail:
2235         /* XXX Failure: Try to fallback to 64-bit only ? */
2236         if (tce_mem)
2237                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2238         if (tbl) {
2239                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2240                 iommu_tce_table_put(tbl);
2241         }
2242 }
2243 
2244 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2245                 int num, struct iommu_table *tbl)
2246 {
2247         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2248                         table_group);
2249         struct pnv_phb *phb = pe->phb;
2250         int64_t rc;
2251         const unsigned long size = tbl->it_indirect_levels ?
2252                         tbl->it_level_size : tbl->it_size;
2253         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2254         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2255 
2256         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2257                         start_addr, start_addr + win_size - 1,
2258                         IOMMU_PAGE_SIZE(tbl));
2259 
2260         /*
2261          * Map TCE table through TVT. The TVE index is the PE number
2262          * shifted by 1 bit for 32-bits DMA space.
2263          */
2264         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2265                         pe->pe_number,
2266                         (pe->pe_number << 1) + num,
2267                         tbl->it_indirect_levels + 1,
2268                         __pa(tbl->it_base),
2269                         size << 3,
2270                         IOMMU_PAGE_SIZE(tbl));
2271         if (rc) {
2272                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2273                 return rc;
2274         }
2275 
2276         pnv_pci_link_table_and_group(phb->hose->node, num,
2277                         tbl, &pe->table_group);
2278         pnv_pci_ioda2_tce_invalidate_pe(pe);
2279 
2280         return 0;
2281 }
2282 
2283 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2284 {
2285         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2286         int64_t rc;
2287 
2288         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2289         if (enable) {
2290                 phys_addr_t top = memblock_end_of_DRAM();
2291 
2292                 top = roundup_pow_of_two(top);
2293                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2294                                                      pe->pe_number,
2295                                                      window_id,
2296                                                      pe->tce_bypass_base,
2297                                                      top);
2298         } else {
2299                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2300                                                      pe->pe_number,
2301                                                      window_id,
2302                                                      pe->tce_bypass_base,
2303                                                      0);
2304         }
2305         if (rc)
2306                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2307         else
2308                 pe->tce_bypass_enabled = enable;
2309 }
2310 
2311 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2312                 __u32 page_shift, __u64 window_size, __u32 levels,
2313                 struct iommu_table *tbl);
2314 
2315 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2316                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2317                 struct iommu_table **ptbl)
2318 {
2319         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2320                         table_group);
2321         int nid = pe->phb->hose->node;
2322         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2323         long ret;
2324         struct iommu_table *tbl;
2325 
2326         tbl = pnv_pci_table_alloc(nid);
2327         if (!tbl)
2328                 return -ENOMEM;
2329 
2330         tbl->it_ops = &pnv_ioda2_iommu_ops;
2331 
2332         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2333                         bus_offset, page_shift, window_size,
2334                         levels, tbl);
2335         if (ret) {
2336                 iommu_tce_table_put(tbl);
2337                 return ret;
2338         }
2339 
2340         *ptbl = tbl;
2341 
2342         return 0;
2343 }
2344 
2345 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2346 {
2347         struct iommu_table *tbl = NULL;
2348         long rc;
2349 
2350         /*
2351          * crashkernel= specifies the kdump kernel's maximum memory at
2352          * some offset and there is no guaranteed the result is a power
2353          * of 2, which will cause errors later.
2354          */
2355         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2356 
2357         /*
2358          * In memory constrained environments, e.g. kdump kernel, the
2359          * DMA window can be larger than available memory, which will
2360          * cause errors later.
2361          */
2362         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2363 
2364         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2365                         IOMMU_PAGE_SHIFT_4K,
2366                         window_size,
2367                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2368         if (rc) {
2369                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2370                                 rc);
2371                 return rc;
2372         }
2373 
2374         iommu_init_table(tbl, pe->phb->hose->node);
2375 
2376         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2377         if (rc) {
2378                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2379                                 rc);
2380                 iommu_tce_table_put(tbl);
2381                 return rc;
2382         }
2383 
2384         if (!pnv_iommu_bypass_disabled)
2385                 pnv_pci_ioda2_set_bypass(pe, true);
2386 
2387         /*
2388          * Setting table base here only for carrying iommu_group
2389          * further down to let iommu_add_device() do the job.
2390          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2391          */
2392         if (pe->flags & PNV_IODA_PE_DEV)
2393                 set_iommu_table_base(&pe->pdev->dev, tbl);
2394 
2395         return 0;
2396 }
2397 
2398 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2399 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2400                 int num)
2401 {
2402         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2403                         table_group);
2404         struct pnv_phb *phb = pe->phb;
2405         long ret;
2406 
2407         pe_info(pe, "Removing DMA window #%d\n", num);
2408 
2409         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2410                         (pe->pe_number << 1) + num,
2411                         0/* levels */, 0/* table address */,
2412                         0/* table size */, 0/* page size */);
2413         if (ret)
2414                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2415         else
2416                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2417 
2418         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2419 
2420         return ret;
2421 }
2422 #endif
2423 
2424 #ifdef CONFIG_IOMMU_API
2425 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2426                 __u64 window_size, __u32 levels)
2427 {
2428         unsigned long bytes = 0;
2429         const unsigned window_shift = ilog2(window_size);
2430         unsigned entries_shift = window_shift - page_shift;
2431         unsigned table_shift = entries_shift + 3;
2432         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2433         unsigned long direct_table_size;
2434 
2435         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2436                         (window_size > memory_hotplug_max()) ||
2437                         !is_power_of_2(window_size))
2438                 return 0;
2439 
2440         /* Calculate a direct table size from window_size and levels */
2441         entries_shift = (entries_shift + levels - 1) / levels;
2442         table_shift = entries_shift + 3;
2443         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2444         direct_table_size =  1UL << table_shift;
2445 
2446         for ( ; levels; --levels) {
2447                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2448 
2449                 tce_table_size /= direct_table_size;
2450                 tce_table_size <<= 3;
2451                 tce_table_size = max_t(unsigned long,
2452                                 tce_table_size, direct_table_size);
2453         }
2454 
2455         return bytes;
2456 }
2457 
2458 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2459 {
2460         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2461                                                 table_group);
2462         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2463         struct iommu_table *tbl = pe->table_group.tables[0];
2464 
2465         pnv_pci_ioda2_set_bypass(pe, false);
2466         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2467         if (pe->pbus)
2468                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2469         iommu_tce_table_put(tbl);
2470 }
2471 
2472 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2473 {
2474         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2475                                                 table_group);
2476 
2477         pnv_pci_ioda2_setup_default_config(pe);
2478         if (pe->pbus)
2479                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2480 }
2481 
2482 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2483         .get_table_size = pnv_pci_ioda2_get_table_size,
2484         .create_table = pnv_pci_ioda2_create_table,
2485         .set_window = pnv_pci_ioda2_set_window,
2486         .unset_window = pnv_pci_ioda2_unset_window,
2487         .take_ownership = pnv_ioda2_take_ownership,
2488         .release_ownership = pnv_ioda2_release_ownership,
2489 };
2490 
2491 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2492 {
2493         struct pci_controller *hose;
2494         struct pnv_phb *phb;
2495         struct pnv_ioda_pe **ptmppe = opaque;
2496         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2497         struct pci_dn *pdn = pci_get_pdn(pdev);
2498 
2499         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2500                 return 0;
2501 
2502         hose = pci_bus_to_host(pdev->bus);
2503         phb = hose->private_data;
2504         if (phb->type != PNV_PHB_NPU)
2505                 return 0;
2506 
2507         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2508 
2509         return 1;
2510 }
2511 
2512 /*
2513  * This returns PE of associated NPU.
2514  * This assumes that NPU is in the same IOMMU group with GPU and there is
2515  * no other PEs.
2516  */
2517 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2518                 struct iommu_table_group *table_group)
2519 {
2520         struct pnv_ioda_pe *npe = NULL;
2521         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2522                         gpe_table_group_to_npe_cb);
2523 
2524         BUG_ON(!ret || !npe);
2525 
2526         return npe;
2527 }
2528 
2529 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2530                 int num, struct iommu_table *tbl)
2531 {
2532         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2533 
2534         if (ret)
2535                 return ret;
2536 
2537         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2538         if (ret)
2539                 pnv_pci_ioda2_unset_window(table_group, num);
2540 
2541         return ret;
2542 }
2543 
2544 static long pnv_pci_ioda2_npu_unset_window(
2545                 struct iommu_table_group *table_group,
2546                 int num)
2547 {
2548         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2549 
2550         if (ret)
2551                 return ret;
2552 
2553         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2554 }
2555 
2556 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2557 {
2558         /*
2559          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2560          * the iommu_table if 32bit DMA is enabled.
2561          */
2562         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2563         pnv_ioda2_take_ownership(table_group);
2564 }
2565 
2566 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2567         .get_table_size = pnv_pci_ioda2_get_table_size,
2568         .create_table = pnv_pci_ioda2_create_table,
2569         .set_window = pnv_pci_ioda2_npu_set_window,
2570         .unset_window = pnv_pci_ioda2_npu_unset_window,
2571         .take_ownership = pnv_ioda2_npu_take_ownership,
2572         .release_ownership = pnv_ioda2_release_ownership,
2573 };
2574 
2575 static void pnv_pci_ioda_setup_iommu_api(void)
2576 {
2577         struct pci_controller *hose, *tmp;
2578         struct pnv_phb *phb;
2579         struct pnv_ioda_pe *pe, *gpe;
2580 
2581         /*
2582          * Now we have all PHBs discovered, time to add NPU devices to
2583          * the corresponding IOMMU groups.
2584          */
2585         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2586                 phb = hose->private_data;
2587 
2588                 if (phb->type != PNV_PHB_NPU)
2589                         continue;
2590 
2591                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2592                         gpe = pnv_pci_npu_setup_iommu(pe);
2593                         if (gpe)
2594                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2595                 }
2596         }
2597 }
2598 #else /* !CONFIG_IOMMU_API */
2599 static void pnv_pci_ioda_setup_iommu_api(void) { };
2600 #endif
2601 
2602 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2603                 unsigned levels, unsigned long limit,
2604                 unsigned long *current_offset, unsigned long *total_allocated)
2605 {
2606         struct page *tce_mem = NULL;
2607         __be64 *addr, *tmp;
2608         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2609         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2610         unsigned entries = 1UL << (shift - 3);
2611         long i;
2612 
2613         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2614         if (!tce_mem) {
2615                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2616                 return NULL;
2617         }
2618         addr = page_address(tce_mem);
2619         memset(addr, 0, allocated);
2620         *total_allocated += allocated;
2621 
2622         --levels;
2623         if (!levels) {
2624                 *current_offset += allocated;
2625                 return addr;
2626         }
2627 
2628         for (i = 0; i < entries; ++i) {
2629                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2630                                 levels, limit, current_offset, total_allocated);
2631                 if (!tmp)
2632                         break;
2633 
2634                 addr[i] = cpu_to_be64(__pa(tmp) |
2635                                 TCE_PCI_READ | TCE_PCI_WRITE);
2636 
2637                 if (*current_offset >= limit)
2638                         break;
2639         }
2640 
2641         return addr;
2642 }
2643 
2644 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2645                 unsigned long size, unsigned level);
2646 
2647 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2648                 __u32 page_shift, __u64 window_size, __u32 levels,
2649                 struct iommu_table *tbl)
2650 {
2651         void *addr;
2652         unsigned long offset = 0, level_shift, total_allocated = 0;
2653         const unsigned window_shift = ilog2(window_size);
2654         unsigned entries_shift = window_shift - page_shift;
2655         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2656         const unsigned long tce_table_size = 1UL << table_shift;
2657 
2658         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2659                 return -EINVAL;
2660 
2661         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2662                 return -EINVAL;
2663 
2664         /* Adjust direct table size from window_size and levels */
2665         entries_shift = (entries_shift + levels - 1) / levels;
2666         level_shift = entries_shift + 3;
2667         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2668 
2669         if ((level_shift - 3) * levels + page_shift >= 60)
2670                 return -EINVAL;
2671 
2672         /* Allocate TCE table */
2673         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2674                         levels, tce_table_size, &offset, &total_allocated);
2675 
2676         /* addr==NULL means that the first level allocation failed */
2677         if (!addr)
2678                 return -ENOMEM;
2679 
2680         /*
2681          * First level was allocated but some lower level failed as
2682          * we did not allocate as much as we wanted,
2683          * release partially allocated table.
2684          */
2685         if (offset < tce_table_size) {
2686                 pnv_pci_ioda2_table_do_free_pages(addr,
2687                                 1ULL << (level_shift - 3), levels - 1);
2688                 return -ENOMEM;
2689         }
2690 
2691         /* Setup linux iommu table */
2692         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2693                         page_shift);
2694         tbl->it_level_size = 1ULL << (level_shift - 3);
2695         tbl->it_indirect_levels = levels - 1;
2696         tbl->it_allocated_size = total_allocated;
2697 
2698         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2699                         window_size, tce_table_size, bus_offset);
2700 
2701         return 0;
2702 }
2703 
2704 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2705                 unsigned long size, unsigned level)
2706 {
2707         const unsigned long addr_ul = (unsigned long) addr &
2708                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2709 
2710         if (level) {
2711                 long i;
2712                 u64 *tmp = (u64 *) addr_ul;
2713 
2714                 for (i = 0; i < size; ++i) {
2715                         unsigned long hpa = be64_to_cpu(tmp[i]);
2716 
2717                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2718                                 continue;
2719 
2720                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2721                                         level - 1);
2722                 }
2723         }
2724 
2725         free_pages(addr_ul, get_order(size << 3));
2726 }
2727 
2728 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2729 {
2730         const unsigned long size = tbl->it_indirect_levels ?
2731                         tbl->it_level_size : tbl->it_size;
2732 
2733         if (!tbl->it_size)
2734                 return;
2735 
2736         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2737                         tbl->it_indirect_levels);
2738 }
2739 
2740 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2741                                        struct pnv_ioda_pe *pe)
2742 {
2743         int64_t rc;
2744 
2745         if (!pnv_pci_ioda_pe_dma_weight(pe))
2746                 return;
2747 
2748         /* TVE #1 is selected by PCI address bit 59 */
2749         pe->tce_bypass_base = 1ull << 59;
2750 
2751         iommu_register_group(&pe->table_group, phb->hose->global_number,
2752                         pe->pe_number);
2753 
2754         /* The PE will reserve all possible 32-bits space */
2755         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2756                 phb->ioda.m32_pci_base);
2757 
2758         /* Setup linux iommu table */
2759         pe->table_group.tce32_start = 0;
2760         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2761         pe->table_group.max_dynamic_windows_supported =
2762                         IOMMU_TABLE_GROUP_MAX_TABLES;
2763         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2764         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2765 #ifdef CONFIG_IOMMU_API
2766         pe->table_group.ops = &pnv_pci_ioda2_ops;
2767 #endif
2768 
2769         rc = pnv_pci_ioda2_setup_default_config(pe);
2770         if (rc)
2771                 return;
2772 
2773         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2774                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2775 }
2776 
2777 #ifdef CONFIG_PCI_MSI
2778 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2779 {
2780         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2781                                            ioda.irq_chip);
2782 
2783         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2784 }
2785 
2786 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2787 {
2788         int64_t rc;
2789         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2790         struct irq_chip *chip = irq_data_get_irq_chip(d);
2791 
2792         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2793         WARN_ON_ONCE(rc);
2794 
2795         icp_native_eoi(d);
2796 }
2797 
2798 
2799 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2800 {
2801         struct irq_data *idata;
2802         struct irq_chip *ichip;
2803 
2804         /* The MSI EOI OPAL call is only needed on PHB3 */
2805         if (phb->model != PNV_PHB_MODEL_PHB3)
2806                 return;
2807 
2808         if (!phb->ioda.irq_chip_init) {
2809                 /*
2810                  * First time we setup an MSI IRQ, we need to setup the
2811                  * corresponding IRQ chip to route correctly.
2812                  */
2813                 idata = irq_get_irq_data(virq);
2814                 ichip = irq_data_get_irq_chip(idata);
2815                 phb->ioda.irq_chip_init = 1;
2816                 phb->ioda.irq_chip = *ichip;
2817                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2818         }
2819         irq_set_chip(virq, &phb->ioda.irq_chip);
2820 }
2821 
2822 /*
2823  * Returns true iff chip is something that we could call
2824  * pnv_opal_pci_msi_eoi for.
2825  */
2826 bool is_pnv_opal_msi(struct irq_chip *chip)
2827 {
2828         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2829 }
2830 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2831 
2832 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2833                                   unsigned int hwirq, unsigned int virq,
2834                                   unsigned int is_64, struct msi_msg *msg)
2835 {
2836         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2837         unsigned int xive_num = hwirq - phb->msi_base;
2838         __be32 data;
2839         int rc;
2840 
2841         /* No PE assigned ? bail out ... no MSI for you ! */
2842         if (pe == NULL)
2843                 return -ENXIO;
2844 
2845         /* Check if we have an MVE */
2846         if (pe->mve_number < 0)
2847                 return -ENXIO;
2848 
2849         /* Force 32-bit MSI on some broken devices */
2850         if (dev->no_64bit_msi)
2851                 is_64 = 0;
2852 
2853         /* Assign XIVE to PE */
2854         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2855         if (rc) {
2856                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2857                         pci_name(dev), rc, xive_num);
2858                 return -EIO;
2859         }
2860 
2861         if (is_64) {
2862                 __be64 addr64;
2863 
2864                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2865                                      &addr64, &data);
2866                 if (rc) {
2867                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2868                                 pci_name(dev), rc);
2869                         return -EIO;
2870                 }
2871                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2872                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2873         } else {
2874                 __be32 addr32;
2875 
2876                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2877                                      &addr32, &data);
2878                 if (rc) {
2879                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2880                                 pci_name(dev), rc);
2881                         return -EIO;
2882                 }
2883                 msg->address_hi = 0;
2884                 msg->address_lo = be32_to_cpu(addr32);
2885         }
2886         msg->data = be32_to_cpu(data);
2887 
2888         pnv_set_msi_irq_chip(phb, virq);
2889 
2890         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2891                  " address=%x_%08x data=%x PE# %x\n",
2892                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2893                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2894 
2895         return 0;
2896 }
2897 
2898 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2899 {
2900         unsigned int count;
2901         const __be32 *prop = of_get_property(phb->hose->dn,
2902                                              "ibm,opal-msi-ranges", NULL);
2903         if (!prop) {
2904                 /* BML Fallback */
2905                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2906         }
2907         if (!prop)
2908                 return;
2909 
2910         phb->msi_base = be32_to_cpup(prop);
2911         count = be32_to_cpup(prop + 1);
2912         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2913                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2914                        phb->hose->global_number);
2915                 return;
2916         }
2917 
2918         phb->msi_setup = pnv_pci_ioda_msi_setup;
2919         phb->msi32_support = 1;
2920         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2921                 count, phb->msi_base);
2922 }
2923 #else
2924 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2925 #endif /* CONFIG_PCI_MSI */
2926 
2927 #ifdef CONFIG_PCI_IOV
2928 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2929 {
2930         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2931         struct pnv_phb *phb = hose->private_data;
2932         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2933         struct resource *res;
2934         int i;
2935         resource_size_t size, total_vf_bar_sz;
2936         struct pci_dn *pdn;
2937         int mul, total_vfs;
2938 
2939         if (!pdev->is_physfn || pdev->is_added)
2940                 return;
2941 
2942         pdn = pci_get_pdn(pdev);
2943         pdn->vfs_expanded = 0;
2944         pdn->m64_single_mode = false;
2945 
2946         total_vfs = pci_sriov_get_totalvfs(pdev);
2947         mul = phb->ioda.total_pe_num;
2948         total_vf_bar_sz = 0;
2949 
2950         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2951                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2952                 if (!res->flags || res->parent)
2953                         continue;
2954                 if (!pnv_pci_is_m64_flags(res->flags)) {
2955                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2956                                         " non M64 VF BAR%d: %pR. \n",
2957                                  i, res);
2958                         goto truncate_iov;
2959                 }
2960 
2961                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2962                                 i + PCI_IOV_RESOURCES);
2963 
2964                 /*
2965                  * If bigger than quarter of M64 segment size, just round up
2966                  * power of two.
2967                  *
2968                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2969                  * with other devices, IOV BAR size is expanded to be
2970                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2971                  * segment size , the expanded size would equal to half of the
2972                  * whole M64 space size, which will exhaust the M64 Space and
2973                  * limit the system flexibility.  This is a design decision to
2974                  * set the boundary to quarter of the M64 segment size.
2975                  */
2976                 if (total_vf_bar_sz > gate) {
2977                         mul = roundup_pow_of_two(total_vfs);
2978                         dev_info(&pdev->dev,
2979                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2980                                 total_vf_bar_sz, gate, mul);
2981                         pdn->m64_single_mode = true;
2982                         break;
2983                 }
2984         }
2985 
2986         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2987                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2988                 if (!res->flags || res->parent)
2989                         continue;
2990 
2991                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2992                 /*
2993                  * On PHB3, the minimum size alignment of M64 BAR in single
2994                  * mode is 32MB.
2995                  */
2996                 if (pdn->m64_single_mode && (size < SZ_32M))
2997                         goto truncate_iov;
2998                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2999                 res->end = res->start + size * mul - 1;
3000                 dev_dbg(&pdev->dev, "                       %pR\n", res);
3001                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3002                          i, res, mul);
3003         }
3004         pdn->vfs_expanded = mul;
3005 
3006         return;
3007 
3008 truncate_iov:
3009         /* To save MMIO space, IOV BAR is truncated. */
3010         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3011                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3012                 res->flags = 0;
3013                 res->end = res->start - 1;
3014         }
3015 }
3016 #endif /* CONFIG_PCI_IOV */
3017 
3018 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3019                                   struct resource *res)
3020 {
3021         struct pnv_phb *phb = pe->phb;
3022         struct pci_bus_region region;
3023         int index;
3024         int64_t rc;
3025 
3026         if (!res || !res->flags || res->start > res->end)
3027                 return;
3028 
3029         if (res->flags & IORESOURCE_IO) {
3030                 region.start = res->start - phb->ioda.io_pci_base;
3031                 region.end   = res->end - phb->ioda.io_pci_base;
3032                 index = region.start / phb->ioda.io_segsize;
3033 
3034                 while (index < phb->ioda.total_pe_num &&
3035                        region.start <= region.end) {
3036                         phb->ioda.io_segmap[index] = pe->pe_number;
3037                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3038                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3039                         if (rc != OPAL_SUCCESS) {
3040                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3041                                        __func__, rc, index, pe->pe_number);
3042                                 break;
3043                         }
3044 
3045                         region.start += phb->ioda.io_segsize;
3046                         index++;
3047                 }
3048         } else if ((res->flags & IORESOURCE_MEM) &&
3049                    !pnv_pci_is_m64(phb, res)) {
3050                 region.start = res->start -
3051                                phb->hose->mem_offset[0] -
3052                                phb->ioda.m32_pci_base;
3053                 region.end   = res->end -
3054                                phb->hose->mem_offset[0] -
3055                                phb->ioda.m32_pci_base;
3056                 index = region.start / phb->ioda.m32_segsize;
3057 
3058                 while (index < phb->ioda.total_pe_num &&
3059                        region.start <= region.end) {
3060                         phb->ioda.m32_segmap[index] = pe->pe_number;
3061                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3062                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3063                         if (rc != OPAL_SUCCESS) {
3064                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3065                                        __func__, rc, index, pe->pe_number);
3066                                 break;
3067                         }
3068 
3069                         region.start += phb->ioda.m32_segsize;
3070                         index++;
3071                 }
3072         }
3073 }
3074 
3075 /*
3076  * This function is supposed to be called on basis of PE from top
3077  * to bottom style. So the the I/O or MMIO segment assigned to
3078  * parent PE could be overridden by its child PEs if necessary.
3079  */
3080 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3081 {
3082         struct pci_dev *pdev;
3083         int i;
3084 
3085         /*
3086          * NOTE: We only care PCI bus based PE for now. For PCI
3087          * device based PE, for example SRIOV sensitive VF should
3088          * be figured out later.
3089          */
3090         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3091 
3092         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3093                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3094                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3095 
3096                 /*
3097                  * If the PE contains all subordinate PCI buses, the
3098                  * windows of the child bridges should be mapped to
3099                  * the PE as well.
3100                  */
3101                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3102                         continue;
3103                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3104                         pnv_ioda_setup_pe_res(pe,
3105                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3106         }
3107 }
3108 
3109 #ifdef CONFIG_DEBUG_FS
3110 static int pnv_pci_diag_data_set(void *data, u64 val)
3111 {
3112         struct pci_controller *hose;
3113         struct pnv_phb *phb;
3114         s64 ret;
3115 
3116         if (val != 1ULL)
3117                 return -EINVAL;
3118 
3119         hose = (struct pci_controller *)data;
3120         if (!hose || !hose->private_data)
3121                 return -ENODEV;
3122 
3123         phb = hose->private_data;
3124 
3125         /* Retrieve the diag data from firmware */
3126         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
3127                                           PNV_PCI_DIAG_BUF_SIZE);
3128         if (ret != OPAL_SUCCESS)
3129                 return -EIO;
3130 
3131         /* Print the diag data to the kernel log */
3132         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
3133         return 0;
3134 }
3135 
3136 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3137                         pnv_pci_diag_data_set, "%llu\n");
3138 
3139 #endif /* CONFIG_DEBUG_FS */
3140 
3141 static void pnv_pci_ioda_create_dbgfs(void)
3142 {
3143 #ifdef CONFIG_DEBUG_FS
3144         struct pci_controller *hose, *tmp;
3145         struct pnv_phb *phb;
3146         char name[16];
3147 
3148         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3149                 phb = hose->private_data;
3150 
3151                 /* Notify initialization of PHB done */
3152                 phb->initialized = 1;
3153 
3154                 sprintf(name, "PCI%04x", hose->global_number);
3155                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3156                 if (!phb->dbgfs) {
3157                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3158                                 __func__, hose->global_number);
3159                         continue;
3160                 }
3161 
3162                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3163                                     &pnv_pci_diag_data_fops);
3164         }
3165 #endif /* CONFIG_DEBUG_FS */
3166 }
3167 
3168 static void pnv_pci_ioda_fixup(void)
3169 {
3170         pnv_pci_ioda_setup_PEs();
3171         pnv_pci_ioda_setup_iommu_api();
3172         pnv_pci_ioda_create_dbgfs();
3173 
3174 #ifdef CONFIG_EEH
3175         eeh_init();
3176         eeh_addr_cache_build();
3177 #endif
3178 }
3179 
3180 /*
3181  * Returns the alignment for I/O or memory windows for P2P
3182  * bridges. That actually depends on how PEs are segmented.
3183  * For now, we return I/O or M32 segment size for PE sensitive
3184  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3185  * 1MiB for memory) will be returned.
3186  *
3187  * The current PCI bus might be put into one PE, which was
3188  * create against the parent PCI bridge. For that case, we
3189  * needn't enlarge the alignment so that we can save some
3190  * resources.
3191  */
3192 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3193                                                 unsigned long type)
3194 {
3195         struct pci_dev *bridge;
3196         struct pci_controller *hose = pci_bus_to_host(bus);
3197         struct pnv_phb *phb = hose->private_data;
3198         int num_pci_bridges = 0;
3199 
3200         bridge = bus->self;
3201         while (bridge) {
3202                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3203                         num_pci_bridges++;
3204                         if (num_pci_bridges >= 2)
3205                                 return 1;
3206                 }
3207 
3208                 bridge = bridge->bus->self;
3209         }
3210 
3211         /*
3212          * We fall back to M32 if M64 isn't supported. We enforce the M64
3213          * alignment for any 64-bit resource, PCIe doesn't care and
3214          * bridges only do 64-bit prefetchable anyway.
3215          */
3216         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3217                 return phb->ioda.m64_segsize;
3218         if (type & IORESOURCE_MEM)
3219                 return phb->ioda.m32_segsize;
3220 
3221         return phb->ioda.io_segsize;
3222 }
3223 
3224 /*
3225  * We are updating root port or the upstream port of the
3226  * bridge behind the root port with PHB's windows in order
3227  * to accommodate the changes on required resources during
3228  * PCI (slot) hotplug, which is connected to either root
3229  * port or the downstream ports of PCIe switch behind the
3230  * root port.
3231  */
3232 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3233                                            unsigned long type)
3234 {
3235         struct pci_controller *hose = pci_bus_to_host(bus);
3236         struct pnv_phb *phb = hose->private_data;
3237         struct pci_dev *bridge = bus->self;
3238         struct resource *r, *w;
3239         bool msi_region = false;
3240         int i;
3241 
3242         /* Check if we need apply fixup to the bridge's windows */
3243         if (!pci_is_root_bus(bridge->bus) &&
3244             !pci_is_root_bus(bridge->bus->self->bus))
3245                 return;
3246 
3247         /* Fixup the resources */
3248         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3249                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3250                 if (!r->flags || !r->parent)
3251                         continue;
3252 
3253                 w = NULL;
3254                 if (r->flags & type & IORESOURCE_IO)
3255                         w = &hose->io_resource;
3256                 else if (pnv_pci_is_m64(phb, r) &&
3257                          (type & IORESOURCE_PREFETCH) &&
3258                          phb->ioda.m64_segsize)
3259                         w = &hose->mem_resources[1];
3260                 else if (r->flags & type & IORESOURCE_MEM) {
3261                         w = &hose->mem_resources[0];
3262                         msi_region = true;
3263                 }
3264 
3265                 r->start = w->start;
3266                 r->end = w->end;
3267 
3268                 /* The 64KB 32-bits MSI region shouldn't be included in
3269                  * the 32-bits bridge window. Otherwise, we can see strange
3270                  * issues. One of them is EEH error observed on Garrison.
3271                  *
3272                  * Exclude top 1MB region which is the minimal alignment of
3273                  * 32-bits bridge window.
3274                  */
3275                 if (msi_region) {
3276                         r->end += 0x10000;
3277                         r->end -= 0x100000;
3278                 }
3279         }
3280 }
3281 
3282 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3283 {
3284         struct pci_controller *hose = pci_bus_to_host(bus);
3285         struct pnv_phb *phb = hose->private_data;
3286         struct pci_dev *bridge = bus->self;
3287         struct pnv_ioda_pe *pe;
3288         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3289 
3290         /* Extend bridge's windows if necessary */
3291         pnv_pci_fixup_bridge_resources(bus, type);
3292 
3293         /* The PE for root bus should be realized before any one else */
3294         if (!phb->ioda.root_pe_populated) {
3295                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3296                 if (pe) {
3297                         phb->ioda.root_pe_idx = pe->pe_number;
3298                         phb->ioda.root_pe_populated = true;
3299                 }
3300         }
3301 
3302         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3303         if (list_empty(&bus->devices))
3304                 return;
3305 
3306         /* Reserve PEs according to used M64 resources */
3307         if (phb->reserve_m64_pe)
3308                 phb->reserve_m64_pe(bus, NULL, all);
3309 
3310         /*
3311          * Assign PE. We might run here because of partial hotplug.
3312          * For the case, we just pick up the existing PE and should
3313          * not allocate resources again.
3314          */
3315         pe = pnv_ioda_setup_bus_PE(bus, all);
3316         if (!pe)
3317                 return;
3318 
3319         pnv_ioda_setup_pe_seg(pe);
3320         switch (phb->type) {
3321         case PNV_PHB_IODA1:
3322                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3323                 break;
3324         case PNV_PHB_IODA2:
3325                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3326                 break;
3327         default:
3328                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3329                         __func__, phb->hose->global_number, phb->type);
3330         }
3331 }
3332 
3333 static resource_size_t pnv_pci_default_alignment(void)
3334 {
3335         return PAGE_SIZE;
3336 }
3337 
3338 #ifdef CONFIG_PCI_IOV
3339 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3340                                                       int resno)
3341 {
3342         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3343         struct pnv_phb *phb = hose->private_data;
3344         struct pci_dn *pdn = pci_get_pdn(pdev);
3345         resource_size_t align;
3346 
3347         /*
3348          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3349          * SR-IOV. While from hardware perspective, the range mapped by M64
3350          * BAR should be size aligned.
3351          *
3352          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3353          * powernv-specific hardware restriction is gone. But if just use the
3354          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3355          * in one segment of M64 #15, which introduces the PE conflict between
3356          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3357          * m64_segsize.
3358          *
3359          * This function returns the total IOV BAR size if M64 BAR is in
3360          * Shared PE mode or just VF BAR size if not.
3361          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3362          * M64 segment size if IOV BAR size is less.
3363          */
3364         align = pci_iov_resource_size(pdev, resno);
3365         if (!pdn->vfs_expanded)
3366                 return align;
3367         if (pdn->m64_single_mode)
3368                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3369 
3370         return pdn->vfs_expanded * align;
3371 }
3372 #endif /* CONFIG_PCI_IOV */
3373 
3374 /* Prevent enabling devices for which we couldn't properly
3375  * assign a PE
3376  */
3377 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3378 {
3379         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3380         struct pnv_phb *phb = hose->private_data;
3381         struct pci_dn *pdn;
3382 
3383         /* The function is probably called while the PEs have
3384          * not be created yet. For example, resource reassignment
3385          * during PCI probe period. We just skip the check if
3386          * PEs isn't ready.
3387          */
3388         if (!phb->initialized)
3389                 return true;
3390 
3391         pdn = pci_get_pdn(dev);
3392         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3393                 return false;
3394 
3395         return true;
3396 }
3397 
3398 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3399                                        int num)
3400 {
3401         struct pnv_ioda_pe *pe = container_of(table_group,
3402                                               struct pnv_ioda_pe, table_group);
3403         struct pnv_phb *phb = pe->phb;
3404         unsigned int idx;
3405         long rc;
3406 
3407         pe_info(pe, "Removing DMA window #%d\n", num);
3408         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3409                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3410                         continue;
3411 
3412                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3413                                                 idx, 0, 0ul, 0ul, 0ul);
3414                 if (rc != OPAL_SUCCESS) {
3415                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3416                                 rc, idx);
3417                         return rc;
3418                 }
3419 
3420                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3421         }
3422 
3423         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3424         return OPAL_SUCCESS;
3425 }
3426 
3427 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3428 {
3429         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3430         struct iommu_table *tbl = pe->table_group.tables[0];
3431         int64_t rc;
3432 
3433         if (!weight)
3434                 return;
3435 
3436         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3437         if (rc != OPAL_SUCCESS)
3438                 return;
3439 
3440         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3441         if (pe->table_group.group) {
3442                 iommu_group_put(pe->table_group.group);
3443                 WARN_ON(pe->table_group.group);
3444         }
3445 
3446         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3447         iommu_tce_table_put(tbl);
3448 }
3449 
3450 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3451 {
3452         struct iommu_table *tbl = pe->table_group.tables[0];
3453         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3454 #ifdef CONFIG_IOMMU_API
3455         int64_t rc;
3456 #endif
3457 
3458         if (!weight)
3459                 return;
3460 
3461 #ifdef CONFIG_IOMMU_API
3462         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3463         if (rc)
3464                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3465 #endif
3466 
3467         pnv_pci_ioda2_set_bypass(pe, false);
3468         if (pe->table_group.group) {
3469                 iommu_group_put(pe->table_group.group);
3470                 WARN_ON(pe->table_group.group);
3471         }
3472 
3473         pnv_pci_ioda2_table_free_pages(tbl);
3474         iommu_tce_table_put(tbl);
3475 }
3476 
3477 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3478                                  unsigned short win,
3479                                  unsigned int *map)
3480 {
3481         struct pnv_phb *phb = pe->phb;
3482         int idx;
3483         int64_t rc;
3484 
3485         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3486                 if (map[idx] != pe->pe_number)
3487                         continue;
3488 
3489                 if (win == OPAL_M64_WINDOW_TYPE)
3490                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3491                                         phb->ioda.reserved_pe_idx, win,
3492                                         idx / PNV_IODA1_M64_SEGS,
3493                                         idx % PNV_IODA1_M64_SEGS);
3494                 else
3495                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3496                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3497 
3498                 if (rc != OPAL_SUCCESS)
3499                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3500                                 rc, win, idx);
3501 
3502                 map[idx] = IODA_INVALID_PE;
3503         }
3504 }
3505 
3506 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3507 {
3508         struct pnv_phb *phb = pe->phb;
3509 
3510         if (phb->type == PNV_PHB_IODA1) {
3511                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3512                                      phb->ioda.io_segmap);
3513                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3514                                      phb->ioda.m32_segmap);
3515                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3516                                      phb->ioda.m64_segmap);
3517         } else if (phb->type == PNV_PHB_IODA2) {
3518                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3519                                      phb->ioda.m32_segmap);
3520         }
3521 }
3522 
3523 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3524 {
3525         struct pnv_phb *phb = pe->phb;
3526         struct pnv_ioda_pe *slave, *tmp;
3527 
3528         list_del(&pe->list);
3529         switch (phb->type) {
3530         case PNV_PHB_IODA1:
3531                 pnv_pci_ioda1_release_pe_dma(pe);
3532                 break;
3533         case PNV_PHB_IODA2:
3534                 pnv_pci_ioda2_release_pe_dma(pe);
3535                 break;
3536         default:
3537                 WARN_ON(1);
3538         }
3539 
3540         pnv_ioda_release_pe_seg(pe);
3541         pnv_ioda_deconfigure_pe(pe->phb, pe);
3542 
3543         /* Release slave PEs in the compound PE */
3544         if (pe->flags & PNV_IODA_PE_MASTER) {
3545                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3546                         list_del(&slave->list);
3547                         pnv_ioda_free_pe(slave);
3548                 }
3549         }
3550 
3551         /*
3552          * The PE for root bus can be removed because of hotplug in EEH
3553          * recovery for fenced PHB error. We need to mark the PE dead so
3554          * that it can be populated again in PCI hot add path. The PE
3555          * shouldn't be destroyed as it's the global reserved resource.
3556          */
3557         if (phb->ioda.root_pe_populated &&
3558             phb->ioda.root_pe_idx == pe->pe_number)
3559                 phb->ioda.root_pe_populated = false;
3560         else
3561                 pnv_ioda_free_pe(pe);
3562 }
3563 
3564 static void pnv_pci_release_device(struct pci_dev *pdev)
3565 {
3566         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3567         struct pnv_phb *phb = hose->private_data;
3568         struct pci_dn *pdn = pci_get_pdn(pdev);
3569         struct pnv_ioda_pe *pe;
3570 
3571         if (pdev->is_virtfn)
3572                 return;
3573 
3574         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3575                 return;
3576 
3577         /*
3578          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3579          * isn't removed and added afterwards in this scenario. We should
3580          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3581          * device count is decreased on removing devices while failing to
3582          * be increased on adding devices. It leads to unbalanced PE's device
3583          * count and eventually make normal PCI hotplug path broken.
3584          */
3585         pe = &phb->ioda.pe_array[pdn->pe_number];
3586         pdn->pe_number = IODA_INVALID_PE;
3587 
3588         WARN_ON(--pe->device_count < 0);
3589         if (pe->device_count == 0)
3590                 pnv_ioda_release_pe(pe);
3591 }
3592 
3593 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3594 {
3595         struct pnv_phb *phb = hose->private_data;
3596 
3597         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3598                        OPAL_ASSERT_RESET);
3599 }
3600 
3601 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3602         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3603         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3604 #ifdef CONFIG_PCI_MSI
3605         .setup_msi_irqs         = pnv_setup_msi_irqs,
3606         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3607 #endif
3608         .enable_device_hook     = pnv_pci_enable_device_hook,
3609         .release_device         = pnv_pci_release_device,
3610         .window_alignment       = pnv_pci_window_alignment,
3611         .setup_bridge           = pnv_pci_setup_bridge,
3612         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3613         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3614         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3615         .shutdown               = pnv_pci_ioda_shutdown,
3616 };
3617 
3618 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3619 {
3620         dev_err_once(&npdev->dev,
3621                         "%s operation unsupported for NVLink devices\n",
3622                         __func__);
3623         return -EPERM;
3624 }
3625 
3626 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3627         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3628 #ifdef CONFIG_PCI_MSI
3629         .setup_msi_irqs         = pnv_setup_msi_irqs,
3630         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3631 #endif
3632         .enable_device_hook     = pnv_pci_enable_device_hook,
3633         .window_alignment       = pnv_pci_window_alignment,
3634         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3635         .dma_set_mask           = pnv_npu_dma_set_mask,
3636         .shutdown               = pnv_pci_ioda_shutdown,
3637 };
3638 
3639 #ifdef CONFIG_CXL_BASE
3640 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3641         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3642         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3643 #ifdef CONFIG_PCI_MSI
3644         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3645         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3646 #endif
3647         .enable_device_hook     = pnv_cxl_enable_device_hook,
3648         .disable_device         = pnv_cxl_disable_device,
3649         .release_device         = pnv_pci_release_device,
3650         .window_alignment       = pnv_pci_window_alignment,
3651         .setup_bridge           = pnv_pci_setup_bridge,
3652         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3653         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3654         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3655         .shutdown               = pnv_pci_ioda_shutdown,
3656 };
3657 #endif
3658 
3659 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3660                                          u64 hub_id, int ioda_type)
3661 {
3662         struct pci_controller *hose;
3663         struct pnv_phb *phb;
3664         unsigned long size, m64map_off, m32map_off, pemap_off;
3665         unsigned long iomap_off = 0, dma32map_off = 0;
3666         struct resource r;
3667         const __be64 *prop64;
3668         const __be32 *prop32;
3669         int len;
3670         unsigned int segno;
3671         u64 phb_id;
3672         void *aux;
3673         long rc;
3674 
3675         if (!of_device_is_available(np))
3676                 return;
3677 
3678         pr_info("Initializing %s PHB (%s)\n",
3679                 pnv_phb_names[ioda_type], of_node_full_name(np));
3680 
3681         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3682         if (!prop64) {
3683                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3684                 return;
3685         }
3686         phb_id = be64_to_cpup(prop64);
3687         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3688 
3689         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3690 
3691         /* Allocate PCI controller */
3692         phb->hose = hose = pcibios_alloc_controller(np);
3693         if (!phb->hose) {
3694                 pr_err("  Can't allocate PCI controller for %s\n",
3695                        np->full_name);
3696                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3697                 return;
3698         }
3699 
3700         spin_lock_init(&phb->lock);
3701         prop32 = of_get_property(np, "bus-range", &len);
3702         if (prop32 && len == 8) {
3703                 hose->first_busno = be32_to_cpu(prop32[0]);
3704                 hose->last_busno = be32_to_cpu(prop32[1]);
3705         } else {
3706                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3707                 hose->first_busno = 0;
3708                 hose->last_busno = 0xff;
3709         }
3710         hose->private_data = phb;
3711         phb->hub_id = hub_id;
3712         phb->opal_id = phb_id;
3713         phb->type = ioda_type;
3714         mutex_init(&phb->ioda.pe_alloc_mutex);
3715 
3716         /* Detect specific models for error handling */
3717         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3718                 phb->model = PNV_PHB_MODEL_P7IOC;
3719         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3720                 phb->model = PNV_PHB_MODEL_PHB3;
3721         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3722                 phb->model = PNV_PHB_MODEL_NPU;
3723         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3724                 phb->model = PNV_PHB_MODEL_NPU2;
3725         else
3726                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3727 
3728         /* Parse 32-bit and IO ranges (if any) */
3729         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3730 
3731         /* Get registers */
3732         if (!of_address_to_resource(np, 0, &r)) {
3733                 phb->regs_phys = r.start;
3734                 phb->regs = ioremap(r.start, resource_size(&r));
3735                 if (phb->regs == NULL)
3736                         pr_err("  Failed to map registers !\n");
3737         }
3738 
3739         /* Initialize more IODA stuff */
3740         phb->ioda.total_pe_num = 1;
3741         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3742         if (prop32)
3743                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3744         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3745         if (prop32)
3746                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3747 
3748         /* Invalidate RID to PE# mapping */
3749         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3750                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3751 
3752         /* Parse 64-bit MMIO range */
3753         pnv_ioda_parse_m64_window(phb);
3754 
3755         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3756         /* FW Has already off top 64k of M32 space (MSI space) */
3757         phb->ioda.m32_size += 0x10000;
3758 
3759         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3760         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3761         phb->ioda.io_size = hose->pci_io_size;
3762         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3763         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3764 
3765         /* Calculate how many 32-bit TCE segments we have */
3766         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3767                                 PNV_IODA1_DMA32_SEGSIZE;
3768 
3769         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3770         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3771                         sizeof(unsigned long));
3772         m64map_off = size;
3773         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3774         m32map_off = size;
3775         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3776         if (phb->type == PNV_PHB_IODA1) {
3777                 iomap_off = size;
3778                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3779                 dma32map_off = size;
3780                 size += phb->ioda.dma32_count *
3781                         sizeof(phb->ioda.dma32_segmap[0]);
3782         }
3783         pemap_off = size;
3784         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3785         aux = memblock_virt_alloc(size, 0);
3786         phb->ioda.pe_alloc = aux;
3787         phb->ioda.m64_segmap = aux + m64map_off;
3788         phb->ioda.m32_segmap = aux + m32map_off;
3789         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3790                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3791                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3792         }
3793         if (phb->type == PNV_PHB_IODA1) {
3794                 phb->ioda.io_segmap = aux + iomap_off;
3795                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3796                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3797 
3798                 phb->ioda.dma32_segmap = aux + dma32map_off;
3799                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3800                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3801         }
3802         phb->ioda.pe_array = aux + pemap_off;
3803 
3804         /*
3805          * Choose PE number for root bus, which shouldn't have
3806          * M64 resources consumed by its child devices. To pick
3807          * the PE number adjacent to the reserved one if possible.
3808          */
3809         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3810         if (phb->ioda.reserved_pe_idx == 0) {
3811                 phb->ioda.root_pe_idx = 1;
3812                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3813         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3814                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3815                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3816         } else {
3817                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3818         }
3819 
3820         INIT_LIST_HEAD(&phb->ioda.pe_list);
3821         mutex_init(&phb->ioda.pe_list_mutex);
3822 
3823         /* Calculate how many 32-bit TCE segments we have */
3824         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3825                                 PNV_IODA1_DMA32_SEGSIZE;
3826 
3827 #if 0 /* We should really do that ... */
3828         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3829                                          window_type,
3830                                          window_num,
3831                                          starting_real_address,
3832                                          starting_pci_address,
3833                                          segment_size);
3834 #endif
3835 
3836         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3837                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3838                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3839         if (phb->ioda.m64_size)
3840                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3841                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3842         if (phb->ioda.io_size)
3843                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3844                         phb->ioda.io_size, phb->ioda.io_segsize);
3845 
3846 
3847         phb->hose->ops = &pnv_pci_ops;
3848         phb->get_pe_state = pnv_ioda_get_pe_state;
3849         phb->freeze_pe = pnv_ioda_freeze_pe;
3850         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3851 
3852         /* Setup MSI support */
3853         pnv_pci_init_ioda_msis(phb);
3854 
3855         /*
3856          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3857          * to let the PCI core do resource assignment. It's supposed
3858          * that the PCI core will do correct I/O and MMIO alignment
3859          * for the P2P bridge bars so that each PCI bus (excluding
3860          * the child P2P bridges) can form individual PE.
3861          */
3862         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3863 
3864         if (phb->type == PNV_PHB_NPU) {
3865                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3866         } else {
3867                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3868                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3869         }
3870 
3871         ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3872 
3873 #ifdef CONFIG_PCI_IOV
3874         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3875         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3876 #endif
3877 
3878         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3879 
3880         /* Reset IODA tables to a clean state */
3881         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3882         if (rc)
3883                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3884 
3885         /*
3886          * If we're running in kdump kernel, the previous kernel never
3887          * shutdown PCI devices correctly. We already got IODA table
3888          * cleaned out. So we have to issue PHB reset to stop all PCI
3889          * transactions from previous kernel.
3890          */
3891         if (is_kdump_kernel()) {
3892                 pr_info("  Issue PHB reset ...\n");
3893                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3894                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3895         }
3896 
3897         /* Remove M64 resource if we can't configure it successfully */
3898         if (!phb->init_m64 || phb->init_m64(phb))
3899                 hose->mem_resources[1].flags = 0;
3900 }
3901 
3902 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3903 {
3904         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3905 }
3906 
3907 void __init pnv_pci_init_npu_phb(struct device_node *np)
3908 {
3909         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3910 }
3911 
3912 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3913 {
3914         struct device_node *phbn;
3915         const __be64 *prop64;
3916         u64 hub_id;
3917 
3918         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3919 
3920         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3921         if (!prop64) {
3922                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3923                 return;
3924         }
3925         hub_id = be64_to_cpup(prop64);
3926         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3927 
3928         /* Count child PHBs */
3929         for_each_child_of_node(np, phbn) {
3930                 /* Look for IODA1 PHBs */
3931                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3932                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3933         }
3934 }
3935 

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