1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
29
30 #include <asm/sections.h>
31 #include <asm/io.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/opal.h>
38 #include <asm/iommu.h>
39 #include <asm/tce.h>
40 #include <asm/xics.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
45
46 #include <misc/cxl-base.h>
47
48 #include "powernv.h"
49 #include "pci.h"
50
51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54
55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
56 #define POWERNV_IOMMU_MAX_LEVELS 5
57
58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
60
61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
62 const char *fmt, ...)
63 {
64 struct va_format vaf;
65 va_list args;
66 char pfix[32];
67
68 va_start(args, fmt);
69
70 vaf.fmt = fmt;
71 vaf.va = &args;
72
73 if (pe->flags & PNV_IODA_PE_DEV)
74 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
75 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
76 sprintf(pfix, "%04x:%02x ",
77 pci_domain_nr(pe->pbus), pe->pbus->number);
78 #ifdef CONFIG_PCI_IOV
79 else if (pe->flags & PNV_IODA_PE_VF)
80 sprintf(pfix, "%04x:%02x:%2x.%d",
81 pci_domain_nr(pe->parent_dev->bus),
82 (pe->rid & 0xff00) >> 8,
83 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
84 #endif /* CONFIG_PCI_IOV*/
85
86 printk("%spci %s: [PE# %.3d] %pV",
87 level, pfix, pe->pe_number, &vaf);
88
89 va_end(args);
90 }
91
92 static bool pnv_iommu_bypass_disabled __read_mostly;
93
94 static int __init iommu_setup(char *str)
95 {
96 if (!str)
97 return -EINVAL;
98
99 while (*str) {
100 if (!strncmp(str, "nobypass", 8)) {
101 pnv_iommu_bypass_disabled = true;
102 pr_info("PowerNV: IOMMU bypass window disabled.\n");
103 break;
104 }
105 str += strcspn(str, ",");
106 if (*str == ',')
107 str++;
108 }
109
110 return 0;
111 }
112 early_param("iommu", iommu_setup);
113
114 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
115 {
116 /*
117 * WARNING: We cannot rely on the resource flags. The Linux PCI
118 * allocation code sometimes decides to put a 64-bit prefetchable
119 * BAR in the 32-bit window, so we have to compare the addresses.
120 *
121 * For simplicity we only test resource start.
122 */
123 return (r->start >= phb->ioda.m64_base &&
124 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
125 }
126
127 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
128 {
129 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
130
131 return (resource_flags & flags) == flags;
132 }
133
134 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
135 {
136 phb->ioda.pe_array[pe_no].phb = phb;
137 phb->ioda.pe_array[pe_no].pe_number = pe_no;
138
139 return &phb->ioda.pe_array[pe_no];
140 }
141
142 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
143 {
144 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
145 pr_warn("%s: Invalid PE %d on PHB#%x\n",
146 __func__, pe_no, phb->hose->global_number);
147 return;
148 }
149
150 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
151 pr_debug("%s: PE %d was reserved on PHB#%x\n",
152 __func__, pe_no, phb->hose->global_number);
153
154 pnv_ioda_init_pe(phb, pe_no);
155 }
156
157 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
158 {
159 long pe;
160
161 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
162 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
163 return pnv_ioda_init_pe(phb, pe);
164 }
165
166 return NULL;
167 }
168
169 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
170 {
171 struct pnv_phb *phb = pe->phb;
172 unsigned int pe_num = pe->pe_number;
173
174 WARN_ON(pe->pdev);
175
176 memset(pe, 0, sizeof(struct pnv_ioda_pe));
177 clear_bit(pe_num, phb->ioda.pe_alloc);
178 }
179
180 /* The default M64 BAR is shared by all PEs */
181 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
182 {
183 const char *desc;
184 struct resource *r;
185 s64 rc;
186
187 /* Configure the default M64 BAR */
188 rc = opal_pci_set_phb_mem_window(phb->opal_id,
189 OPAL_M64_WINDOW_TYPE,
190 phb->ioda.m64_bar_idx,
191 phb->ioda.m64_base,
192 0, /* unused */
193 phb->ioda.m64_size);
194 if (rc != OPAL_SUCCESS) {
195 desc = "configuring";
196 goto fail;
197 }
198
199 /* Enable the default M64 BAR */
200 rc = opal_pci_phb_mmio_enable(phb->opal_id,
201 OPAL_M64_WINDOW_TYPE,
202 phb->ioda.m64_bar_idx,
203 OPAL_ENABLE_M64_SPLIT);
204 if (rc != OPAL_SUCCESS) {
205 desc = "enabling";
206 goto fail;
207 }
208
209 /*
210 * Exclude the segments for reserved and root bus PE, which
211 * are first or last two PEs.
212 */
213 r = &phb->hose->mem_resources[1];
214 if (phb->ioda.reserved_pe_idx == 0)
215 r->start += (2 * phb->ioda.m64_segsize);
216 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
217 r->end -= (2 * phb->ioda.m64_segsize);
218 else
219 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
220 phb->ioda.reserved_pe_idx);
221
222 return 0;
223
224 fail:
225 pr_warn(" Failure %lld %s M64 BAR#%d\n",
226 rc, desc, phb->ioda.m64_bar_idx);
227 opal_pci_phb_mmio_enable(phb->opal_id,
228 OPAL_M64_WINDOW_TYPE,
229 phb->ioda.m64_bar_idx,
230 OPAL_DISABLE_M64);
231 return -EIO;
232 }
233
234 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
235 unsigned long *pe_bitmap)
236 {
237 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
238 struct pnv_phb *phb = hose->private_data;
239 struct resource *r;
240 resource_size_t base, sgsz, start, end;
241 int segno, i;
242
243 base = phb->ioda.m64_base;
244 sgsz = phb->ioda.m64_segsize;
245 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
246 r = &pdev->resource[i];
247 if (!r->parent || !pnv_pci_is_m64(phb, r))
248 continue;
249
250 start = _ALIGN_DOWN(r->start - base, sgsz);
251 end = _ALIGN_UP(r->end - base, sgsz);
252 for (segno = start / sgsz; segno < end / sgsz; segno++) {
253 if (pe_bitmap)
254 set_bit(segno, pe_bitmap);
255 else
256 pnv_ioda_reserve_pe(phb, segno);
257 }
258 }
259 }
260
261 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
262 {
263 struct resource *r;
264 int index;
265
266 /*
267 * There are 16 M64 BARs, each of which has 8 segments. So
268 * there are as many M64 segments as the maximum number of
269 * PEs, which is 128.
270 */
271 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
272 unsigned long base, segsz = phb->ioda.m64_segsize;
273 int64_t rc;
274
275 base = phb->ioda.m64_base +
276 index * PNV_IODA1_M64_SEGS * segsz;
277 rc = opal_pci_set_phb_mem_window(phb->opal_id,
278 OPAL_M64_WINDOW_TYPE, index, base, 0,
279 PNV_IODA1_M64_SEGS * segsz);
280 if (rc != OPAL_SUCCESS) {
281 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n",
282 rc, phb->hose->global_number, index);
283 goto fail;
284 }
285
286 rc = opal_pci_phb_mmio_enable(phb->opal_id,
287 OPAL_M64_WINDOW_TYPE, index,
288 OPAL_ENABLE_M64_SPLIT);
289 if (rc != OPAL_SUCCESS) {
290 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n",
291 rc, phb->hose->global_number, index);
292 goto fail;
293 }
294 }
295
296 /*
297 * Exclude the segments for reserved and root bus PE, which
298 * are first or last two PEs.
299 */
300 r = &phb->hose->mem_resources[1];
301 if (phb->ioda.reserved_pe_idx == 0)
302 r->start += (2 * phb->ioda.m64_segsize);
303 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
304 r->end -= (2 * phb->ioda.m64_segsize);
305 else
306 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
307 phb->ioda.reserved_pe_idx, phb->hose->global_number);
308
309 return 0;
310
311 fail:
312 for ( ; index >= 0; index--)
313 opal_pci_phb_mmio_enable(phb->opal_id,
314 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
315
316 return -EIO;
317 }
318
319 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
320 unsigned long *pe_bitmap,
321 bool all)
322 {
323 struct pci_dev *pdev;
324
325 list_for_each_entry(pdev, &bus->devices, bus_list) {
326 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
327
328 if (all && pdev->subordinate)
329 pnv_ioda_reserve_m64_pe(pdev->subordinate,
330 pe_bitmap, all);
331 }
332 }
333
334 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
335 {
336 struct pci_controller *hose = pci_bus_to_host(bus);
337 struct pnv_phb *phb = hose->private_data;
338 struct pnv_ioda_pe *master_pe, *pe;
339 unsigned long size, *pe_alloc;
340 int i;
341
342 /* Root bus shouldn't use M64 */
343 if (pci_is_root_bus(bus))
344 return NULL;
345
346 /* Allocate bitmap */
347 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
348 pe_alloc = kzalloc(size, GFP_KERNEL);
349 if (!pe_alloc) {
350 pr_warn("%s: Out of memory !\n",
351 __func__);
352 return NULL;
353 }
354
355 /* Figure out reserved PE numbers by the PE */
356 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
357
358 /*
359 * the current bus might not own M64 window and that's all
360 * contributed by its child buses. For the case, we needn't
361 * pick M64 dependent PE#.
362 */
363 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
364 kfree(pe_alloc);
365 return NULL;
366 }
367
368 /*
369 * Figure out the master PE and put all slave PEs to master
370 * PE's list to form compound PE.
371 */
372 master_pe = NULL;
373 i = -1;
374 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
375 phb->ioda.total_pe_num) {
376 pe = &phb->ioda.pe_array[i];
377
378 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
379 if (!master_pe) {
380 pe->flags |= PNV_IODA_PE_MASTER;
381 INIT_LIST_HEAD(&pe->slaves);
382 master_pe = pe;
383 } else {
384 pe->flags |= PNV_IODA_PE_SLAVE;
385 pe->master = master_pe;
386 list_add_tail(&pe->list, &master_pe->slaves);
387 }
388
389 /*
390 * P7IOC supports M64DT, which helps mapping M64 segment
391 * to one particular PE#. However, PHB3 has fixed mapping
392 * between M64 segment and PE#. In order to have same logic
393 * for P7IOC and PHB3, we enforce fixed mapping between M64
394 * segment and PE# on P7IOC.
395 */
396 if (phb->type == PNV_PHB_IODA1) {
397 int64_t rc;
398
399 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
400 pe->pe_number, OPAL_M64_WINDOW_TYPE,
401 pe->pe_number / PNV_IODA1_M64_SEGS,
402 pe->pe_number % PNV_IODA1_M64_SEGS);
403 if (rc != OPAL_SUCCESS)
404 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
405 __func__, rc, phb->hose->global_number,
406 pe->pe_number);
407 }
408 }
409
410 kfree(pe_alloc);
411 return master_pe;
412 }
413
414 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
415 {
416 struct pci_controller *hose = phb->hose;
417 struct device_node *dn = hose->dn;
418 struct resource *res;
419 u32 m64_range[2], i;
420 const u32 *r;
421 u64 pci_addr;
422
423 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
424 pr_info(" Not support M64 window\n");
425 return;
426 }
427
428 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
429 pr_info(" Firmware too old to support M64 window\n");
430 return;
431 }
432
433 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
434 if (!r) {
435 pr_info(" No <ibm,opal-m64-window> on %s\n",
436 dn->full_name);
437 return;
438 }
439
440 /*
441 * Find the available M64 BAR range and pickup the last one for
442 * covering the whole 64-bits space. We support only one range.
443 */
444 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
445 m64_range, 2)) {
446 /* In absence of the property, assume 0..15 */
447 m64_range[0] = 0;
448 m64_range[1] = 16;
449 }
450 /* We only support 64 bits in our allocator */
451 if (m64_range[1] > 63) {
452 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
453 __func__, m64_range[1], phb->hose->global_number);
454 m64_range[1] = 63;
455 }
456 /* Empty range, no m64 */
457 if (m64_range[1] <= m64_range[0]) {
458 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
459 __func__, phb->hose->global_number);
460 return;
461 }
462
463 /* Configure M64 informations */
464 res = &hose->mem_resources[1];
465 res->name = dn->full_name;
466 res->start = of_translate_address(dn, r + 2);
467 res->end = res->start + of_read_number(r + 4, 2) - 1;
468 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
469 pci_addr = of_read_number(r, 2);
470 hose->mem_offset[1] = res->start - pci_addr;
471
472 phb->ioda.m64_size = resource_size(res);
473 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
474 phb->ioda.m64_base = pci_addr;
475
476 /* This lines up nicely with the display from processing OF ranges */
477 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
478 res->start, res->end, pci_addr, m64_range[0],
479 m64_range[0] + m64_range[1] - 1);
480
481 /* Mark all M64 used up by default */
482 phb->ioda.m64_bar_alloc = (unsigned long)-1;
483
484 /* Use last M64 BAR to cover M64 window */
485 m64_range[1]--;
486 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
487
488 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
489
490 /* Mark remaining ones free */
491 for (i = m64_range[0]; i < m64_range[1]; i++)
492 clear_bit(i, &phb->ioda.m64_bar_alloc);
493
494 /*
495 * Setup init functions for M64 based on IODA version, IODA3 uses
496 * the IODA2 code.
497 */
498 if (phb->type == PNV_PHB_IODA1)
499 phb->init_m64 = pnv_ioda1_init_m64;
500 else
501 phb->init_m64 = pnv_ioda2_init_m64;
502 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
503 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
504 }
505
506 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
507 {
508 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
509 struct pnv_ioda_pe *slave;
510 s64 rc;
511
512 /* Fetch master PE */
513 if (pe->flags & PNV_IODA_PE_SLAVE) {
514 pe = pe->master;
515 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
516 return;
517
518 pe_no = pe->pe_number;
519 }
520
521 /* Freeze master PE */
522 rc = opal_pci_eeh_freeze_set(phb->opal_id,
523 pe_no,
524 OPAL_EEH_ACTION_SET_FREEZE_ALL);
525 if (rc != OPAL_SUCCESS) {
526 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
527 __func__, rc, phb->hose->global_number, pe_no);
528 return;
529 }
530
531 /* Freeze slave PEs */
532 if (!(pe->flags & PNV_IODA_PE_MASTER))
533 return;
534
535 list_for_each_entry(slave, &pe->slaves, list) {
536 rc = opal_pci_eeh_freeze_set(phb->opal_id,
537 slave->pe_number,
538 OPAL_EEH_ACTION_SET_FREEZE_ALL);
539 if (rc != OPAL_SUCCESS)
540 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
541 __func__, rc, phb->hose->global_number,
542 slave->pe_number);
543 }
544 }
545
546 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
547 {
548 struct pnv_ioda_pe *pe, *slave;
549 s64 rc;
550
551 /* Find master PE */
552 pe = &phb->ioda.pe_array[pe_no];
553 if (pe->flags & PNV_IODA_PE_SLAVE) {
554 pe = pe->master;
555 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
556 pe_no = pe->pe_number;
557 }
558
559 /* Clear frozen state for master PE */
560 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
561 if (rc != OPAL_SUCCESS) {
562 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
563 __func__, rc, opt, phb->hose->global_number, pe_no);
564 return -EIO;
565 }
566
567 if (!(pe->flags & PNV_IODA_PE_MASTER))
568 return 0;
569
570 /* Clear frozen state for slave PEs */
571 list_for_each_entry(slave, &pe->slaves, list) {
572 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
573 slave->pe_number,
574 opt);
575 if (rc != OPAL_SUCCESS) {
576 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
577 __func__, rc, opt, phb->hose->global_number,
578 slave->pe_number);
579 return -EIO;
580 }
581 }
582
583 return 0;
584 }
585
586 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
587 {
588 struct pnv_ioda_pe *slave, *pe;
589 u8 fstate, state;
590 __be16 pcierr;
591 s64 rc;
592
593 /* Sanity check on PE number */
594 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
595 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
596
597 /*
598 * Fetch the master PE and the PE instance might be
599 * not initialized yet.
600 */
601 pe = &phb->ioda.pe_array[pe_no];
602 if (pe->flags & PNV_IODA_PE_SLAVE) {
603 pe = pe->master;
604 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
605 pe_no = pe->pe_number;
606 }
607
608 /* Check the master PE */
609 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
610 &state, &pcierr, NULL);
611 if (rc != OPAL_SUCCESS) {
612 pr_warn("%s: Failure %lld getting "
613 "PHB#%x-PE#%x state\n",
614 __func__, rc,
615 phb->hose->global_number, pe_no);
616 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
617 }
618
619 /* Check the slave PE */
620 if (!(pe->flags & PNV_IODA_PE_MASTER))
621 return state;
622
623 list_for_each_entry(slave, &pe->slaves, list) {
624 rc = opal_pci_eeh_freeze_status(phb->opal_id,
625 slave->pe_number,
626 &fstate,
627 &pcierr,
628 NULL);
629 if (rc != OPAL_SUCCESS) {
630 pr_warn("%s: Failure %lld getting "
631 "PHB#%x-PE#%x state\n",
632 __func__, rc,
633 phb->hose->global_number, slave->pe_number);
634 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
635 }
636
637 /*
638 * Override the result based on the ascending
639 * priority.
640 */
641 if (fstate > state)
642 state = fstate;
643 }
644
645 return state;
646 }
647
648 /* Currently those 2 are only used when MSIs are enabled, this will change
649 * but in the meantime, we need to protect them to avoid warnings
650 */
651 #ifdef CONFIG_PCI_MSI
652 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
653 {
654 struct pci_controller *hose = pci_bus_to_host(dev->bus);
655 struct pnv_phb *phb = hose->private_data;
656 struct pci_dn *pdn = pci_get_pdn(dev);
657
658 if (!pdn)
659 return NULL;
660 if (pdn->pe_number == IODA_INVALID_PE)
661 return NULL;
662 return &phb->ioda.pe_array[pdn->pe_number];
663 }
664 #endif /* CONFIG_PCI_MSI */
665
666 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
667 struct pnv_ioda_pe *parent,
668 struct pnv_ioda_pe *child,
669 bool is_add)
670 {
671 const char *desc = is_add ? "adding" : "removing";
672 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
673 OPAL_REMOVE_PE_FROM_DOMAIN;
674 struct pnv_ioda_pe *slave;
675 long rc;
676
677 /* Parent PE affects child PE */
678 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
679 child->pe_number, op);
680 if (rc != OPAL_SUCCESS) {
681 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
682 rc, desc);
683 return -ENXIO;
684 }
685
686 if (!(child->flags & PNV_IODA_PE_MASTER))
687 return 0;
688
689 /* Compound case: parent PE affects slave PEs */
690 list_for_each_entry(slave, &child->slaves, list) {
691 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
692 slave->pe_number, op);
693 if (rc != OPAL_SUCCESS) {
694 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
695 rc, desc);
696 return -ENXIO;
697 }
698 }
699
700 return 0;
701 }
702
703 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
704 struct pnv_ioda_pe *pe,
705 bool is_add)
706 {
707 struct pnv_ioda_pe *slave;
708 struct pci_dev *pdev = NULL;
709 int ret;
710
711 /*
712 * Clear PE frozen state. If it's master PE, we need
713 * clear slave PE frozen state as well.
714 */
715 if (is_add) {
716 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
717 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
718 if (pe->flags & PNV_IODA_PE_MASTER) {
719 list_for_each_entry(slave, &pe->slaves, list)
720 opal_pci_eeh_freeze_clear(phb->opal_id,
721 slave->pe_number,
722 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
723 }
724 }
725
726 /*
727 * Associate PE in PELT. We need add the PE into the
728 * corresponding PELT-V as well. Otherwise, the error
729 * originated from the PE might contribute to other
730 * PEs.
731 */
732 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
733 if (ret)
734 return ret;
735
736 /* For compound PEs, any one affects all of them */
737 if (pe->flags & PNV_IODA_PE_MASTER) {
738 list_for_each_entry(slave, &pe->slaves, list) {
739 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
740 if (ret)
741 return ret;
742 }
743 }
744
745 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
746 pdev = pe->pbus->self;
747 else if (pe->flags & PNV_IODA_PE_DEV)
748 pdev = pe->pdev->bus->self;
749 #ifdef CONFIG_PCI_IOV
750 else if (pe->flags & PNV_IODA_PE_VF)
751 pdev = pe->parent_dev;
752 #endif /* CONFIG_PCI_IOV */
753 while (pdev) {
754 struct pci_dn *pdn = pci_get_pdn(pdev);
755 struct pnv_ioda_pe *parent;
756
757 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
758 parent = &phb->ioda.pe_array[pdn->pe_number];
759 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
760 if (ret)
761 return ret;
762 }
763
764 pdev = pdev->bus->self;
765 }
766
767 return 0;
768 }
769
770 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
771 {
772 struct pci_dev *parent;
773 uint8_t bcomp, dcomp, fcomp;
774 int64_t rc;
775 long rid_end, rid;
776
777 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
778 if (pe->pbus) {
779 int count;
780
781 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
782 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
783 parent = pe->pbus->self;
784 if (pe->flags & PNV_IODA_PE_BUS_ALL)
785 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
786 else
787 count = 1;
788
789 switch(count) {
790 case 1: bcomp = OpalPciBusAll; break;
791 case 2: bcomp = OpalPciBus7Bits; break;
792 case 4: bcomp = OpalPciBus6Bits; break;
793 case 8: bcomp = OpalPciBus5Bits; break;
794 case 16: bcomp = OpalPciBus4Bits; break;
795 case 32: bcomp = OpalPciBus3Bits; break;
796 default:
797 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
798 count);
799 /* Do an exact match only */
800 bcomp = OpalPciBusAll;
801 }
802 rid_end = pe->rid + (count << 8);
803 } else {
804 #ifdef CONFIG_PCI_IOV
805 if (pe->flags & PNV_IODA_PE_VF)
806 parent = pe->parent_dev;
807 else
808 #endif
809 parent = pe->pdev->bus->self;
810 bcomp = OpalPciBusAll;
811 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
812 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
813 rid_end = pe->rid + 1;
814 }
815
816 /* Clear the reverse map */
817 for (rid = pe->rid; rid < rid_end; rid++)
818 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
819
820 /* Release from all parents PELT-V */
821 while (parent) {
822 struct pci_dn *pdn = pci_get_pdn(parent);
823 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
824 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
825 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
826 /* XXX What to do in case of error ? */
827 }
828 parent = parent->bus->self;
829 }
830
831 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
832 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
833
834 /* Disassociate PE in PELT */
835 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
836 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
837 if (rc)
838 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
839 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
840 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
841 if (rc)
842 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
843
844 pe->pbus = NULL;
845 pe->pdev = NULL;
846 #ifdef CONFIG_PCI_IOV
847 pe->parent_dev = NULL;
848 #endif
849
850 return 0;
851 }
852
853 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
854 {
855 struct pci_dev *parent;
856 uint8_t bcomp, dcomp, fcomp;
857 long rc, rid_end, rid;
858
859 /* Bus validation ? */
860 if (pe->pbus) {
861 int count;
862
863 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
864 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
865 parent = pe->pbus->self;
866 if (pe->flags & PNV_IODA_PE_BUS_ALL)
867 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
868 else
869 count = 1;
870
871 switch(count) {
872 case 1: bcomp = OpalPciBusAll; break;
873 case 2: bcomp = OpalPciBus7Bits; break;
874 case 4: bcomp = OpalPciBus6Bits; break;
875 case 8: bcomp = OpalPciBus5Bits; break;
876 case 16: bcomp = OpalPciBus4Bits; break;
877 case 32: bcomp = OpalPciBus3Bits; break;
878 default:
879 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
880 count);
881 /* Do an exact match only */
882 bcomp = OpalPciBusAll;
883 }
884 rid_end = pe->rid + (count << 8);
885 } else {
886 #ifdef CONFIG_PCI_IOV
887 if (pe->flags & PNV_IODA_PE_VF)
888 parent = pe->parent_dev;
889 else
890 #endif /* CONFIG_PCI_IOV */
891 parent = pe->pdev->bus->self;
892 bcomp = OpalPciBusAll;
893 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
894 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
895 rid_end = pe->rid + 1;
896 }
897
898 /*
899 * Associate PE in PELT. We need add the PE into the
900 * corresponding PELT-V as well. Otherwise, the error
901 * originated from the PE might contribute to other
902 * PEs.
903 */
904 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
905 bcomp, dcomp, fcomp, OPAL_MAP_PE);
906 if (rc) {
907 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
908 return -ENXIO;
909 }
910
911 /*
912 * Configure PELTV. NPUs don't have a PELTV table so skip
913 * configuration on them.
914 */
915 if (phb->type != PNV_PHB_NPU)
916 pnv_ioda_set_peltv(phb, pe, true);
917
918 /* Setup reverse map */
919 for (rid = pe->rid; rid < rid_end; rid++)
920 phb->ioda.pe_rmap[rid] = pe->pe_number;
921
922 /* Setup one MVTs on IODA1 */
923 if (phb->type != PNV_PHB_IODA1) {
924 pe->mve_number = 0;
925 goto out;
926 }
927
928 pe->mve_number = pe->pe_number;
929 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
930 if (rc != OPAL_SUCCESS) {
931 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
932 rc, pe->mve_number);
933 pe->mve_number = -1;
934 } else {
935 rc = opal_pci_set_mve_enable(phb->opal_id,
936 pe->mve_number, OPAL_ENABLE_MVE);
937 if (rc) {
938 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
939 rc, pe->mve_number);
940 pe->mve_number = -1;
941 }
942 }
943
944 out:
945 return 0;
946 }
947
948 #ifdef CONFIG_PCI_IOV
949 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
950 {
951 struct pci_dn *pdn = pci_get_pdn(dev);
952 int i;
953 struct resource *res, res2;
954 resource_size_t size;
955 u16 num_vfs;
956
957 if (!dev->is_physfn)
958 return -EINVAL;
959
960 /*
961 * "offset" is in VFs. The M64 windows are sized so that when they
962 * are segmented, each segment is the same size as the IOV BAR.
963 * Each segment is in a separate PE, and the high order bits of the
964 * address are the PE number. Therefore, each VF's BAR is in a
965 * separate PE, and changing the IOV BAR start address changes the
966 * range of PEs the VFs are in.
967 */
968 num_vfs = pdn->num_vfs;
969 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
970 res = &dev->resource[i + PCI_IOV_RESOURCES];
971 if (!res->flags || !res->parent)
972 continue;
973
974 /*
975 * The actual IOV BAR range is determined by the start address
976 * and the actual size for num_vfs VFs BAR. This check is to
977 * make sure that after shifting, the range will not overlap
978 * with another device.
979 */
980 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
981 res2.flags = res->flags;
982 res2.start = res->start + (size * offset);
983 res2.end = res2.start + (size * num_vfs) - 1;
984
985 if (res2.end > res->end) {
986 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
987 i, &res2, res, num_vfs, offset);
988 return -EBUSY;
989 }
990 }
991
992 /*
993 * After doing so, there would be a "hole" in the /proc/iomem when
994 * offset is a positive value. It looks like the device return some
995 * mmio back to the system, which actually no one could use it.
996 */
997 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
998 res = &dev->resource[i + PCI_IOV_RESOURCES];
999 if (!res->flags || !res->parent)
1000 continue;
1001
1002 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1003 res2 = *res;
1004 res->start += size * offset;
1005
1006 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1007 i, &res2, res, (offset > 0) ? "En" : "Dis",
1008 num_vfs, offset);
1009 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1010 }
1011 return 0;
1012 }
1013 #endif /* CONFIG_PCI_IOV */
1014
1015 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1016 {
1017 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1018 struct pnv_phb *phb = hose->private_data;
1019 struct pci_dn *pdn = pci_get_pdn(dev);
1020 struct pnv_ioda_pe *pe;
1021
1022 if (!pdn) {
1023 pr_err("%s: Device tree node not associated properly\n",
1024 pci_name(dev));
1025 return NULL;
1026 }
1027 if (pdn->pe_number != IODA_INVALID_PE)
1028 return NULL;
1029
1030 pe = pnv_ioda_alloc_pe(phb);
1031 if (!pe) {
1032 pr_warning("%s: Not enough PE# available, disabling device\n",
1033 pci_name(dev));
1034 return NULL;
1035 }
1036
1037 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1038 * pointer in the PE data structure, both should be destroyed at the
1039 * same time. However, this needs to be looked at more closely again
1040 * once we actually start removing things (Hotplug, SR-IOV, ...)
1041 *
1042 * At some point we want to remove the PDN completely anyways
1043 */
1044 pci_dev_get(dev);
1045 pdn->pcidev = dev;
1046 pdn->pe_number = pe->pe_number;
1047 pe->flags = PNV_IODA_PE_DEV;
1048 pe->pdev = dev;
1049 pe->pbus = NULL;
1050 pe->mve_number = -1;
1051 pe->rid = dev->bus->number << 8 | pdn->devfn;
1052
1053 pe_info(pe, "Associated device to PE\n");
1054
1055 if (pnv_ioda_configure_pe(phb, pe)) {
1056 /* XXX What do we do here ? */
1057 pnv_ioda_free_pe(pe);
1058 pdn->pe_number = IODA_INVALID_PE;
1059 pe->pdev = NULL;
1060 pci_dev_put(dev);
1061 return NULL;
1062 }
1063
1064 /* Put PE to the list */
1065 list_add_tail(&pe->list, &phb->ioda.pe_list);
1066
1067 return pe;
1068 }
1069
1070 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1071 {
1072 struct pci_dev *dev;
1073
1074 list_for_each_entry(dev, &bus->devices, bus_list) {
1075 struct pci_dn *pdn = pci_get_pdn(dev);
1076
1077 if (pdn == NULL) {
1078 pr_warn("%s: No device node associated with device !\n",
1079 pci_name(dev));
1080 continue;
1081 }
1082
1083 /*
1084 * In partial hotplug case, the PCI device might be still
1085 * associated with the PE and needn't attach it to the PE
1086 * again.
1087 */
1088 if (pdn->pe_number != IODA_INVALID_PE)
1089 continue;
1090
1091 pe->device_count++;
1092 pdn->pcidev = dev;
1093 pdn->pe_number = pe->pe_number;
1094 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1095 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1096 }
1097 }
1098
1099 /*
1100 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1101 * single PCI bus. Another one that contains the primary PCI bus and its
1102 * subordinate PCI devices and buses. The second type of PE is normally
1103 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1104 */
1105 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1106 {
1107 struct pci_controller *hose = pci_bus_to_host(bus);
1108 struct pnv_phb *phb = hose->private_data;
1109 struct pnv_ioda_pe *pe = NULL;
1110 unsigned int pe_num;
1111
1112 /*
1113 * In partial hotplug case, the PE instance might be still alive.
1114 * We should reuse it instead of allocating a new one.
1115 */
1116 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1117 if (pe_num != IODA_INVALID_PE) {
1118 pe = &phb->ioda.pe_array[pe_num];
1119 pnv_ioda_setup_same_PE(bus, pe);
1120 return NULL;
1121 }
1122
1123 /* PE number for root bus should have been reserved */
1124 if (pci_is_root_bus(bus) &&
1125 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1126 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1127
1128 /* Check if PE is determined by M64 */
1129 if (!pe && phb->pick_m64_pe)
1130 pe = phb->pick_m64_pe(bus, all);
1131
1132 /* The PE number isn't pinned by M64 */
1133 if (!pe)
1134 pe = pnv_ioda_alloc_pe(phb);
1135
1136 if (!pe) {
1137 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1138 __func__, pci_domain_nr(bus), bus->number);
1139 return NULL;
1140 }
1141
1142 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1143 pe->pbus = bus;
1144 pe->pdev = NULL;
1145 pe->mve_number = -1;
1146 pe->rid = bus->busn_res.start << 8;
1147
1148 if (all)
1149 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1150 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1151 else
1152 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1153 bus->busn_res.start, pe->pe_number);
1154
1155 if (pnv_ioda_configure_pe(phb, pe)) {
1156 /* XXX What do we do here ? */
1157 pnv_ioda_free_pe(pe);
1158 pe->pbus = NULL;
1159 return NULL;
1160 }
1161
1162 /* Associate it with all child devices */
1163 pnv_ioda_setup_same_PE(bus, pe);
1164
1165 /* Put PE to the list */
1166 list_add_tail(&pe->list, &phb->ioda.pe_list);
1167
1168 return pe;
1169 }
1170
1171 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1172 {
1173 int pe_num, found_pe = false, rc;
1174 long rid;
1175 struct pnv_ioda_pe *pe;
1176 struct pci_dev *gpu_pdev;
1177 struct pci_dn *npu_pdn;
1178 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1179 struct pnv_phb *phb = hose->private_data;
1180
1181 /*
1182 * Due to a hardware errata PE#0 on the NPU is reserved for
1183 * error handling. This means we only have three PEs remaining
1184 * which need to be assigned to four links, implying some
1185 * links must share PEs.
1186 *
1187 * To achieve this we assign PEs such that NPUs linking the
1188 * same GPU get assigned the same PE.
1189 */
1190 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1191 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1192 pe = &phb->ioda.pe_array[pe_num];
1193 if (!pe->pdev)
1194 continue;
1195
1196 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1197 /*
1198 * This device has the same peer GPU so should
1199 * be assigned the same PE as the existing
1200 * peer NPU.
1201 */
1202 dev_info(&npu_pdev->dev,
1203 "Associating to existing PE %d\n", pe_num);
1204 pci_dev_get(npu_pdev);
1205 npu_pdn = pci_get_pdn(npu_pdev);
1206 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1207 npu_pdn->pcidev = npu_pdev;
1208 npu_pdn->pe_number = pe_num;
1209 phb->ioda.pe_rmap[rid] = pe->pe_number;
1210
1211 /* Map the PE to this link */
1212 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1213 OpalPciBusAll,
1214 OPAL_COMPARE_RID_DEVICE_NUMBER,
1215 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1216 OPAL_MAP_PE);
1217 WARN_ON(rc != OPAL_SUCCESS);
1218 found_pe = true;
1219 break;
1220 }
1221 }
1222
1223 if (!found_pe)
1224 /*
1225 * Could not find an existing PE so allocate a new
1226 * one.
1227 */
1228 return pnv_ioda_setup_dev_PE(npu_pdev);
1229 else
1230 return pe;
1231 }
1232
1233 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1234 {
1235 struct pci_dev *pdev;
1236
1237 list_for_each_entry(pdev, &bus->devices, bus_list)
1238 pnv_ioda_setup_npu_PE(pdev);
1239 }
1240
1241 static void pnv_pci_ioda_setup_PEs(void)
1242 {
1243 struct pci_controller *hose, *tmp;
1244 struct pnv_phb *phb;
1245
1246 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1247 phb = hose->private_data;
1248 if (phb->type == PNV_PHB_NPU) {
1249 /* PE#0 is needed for error reporting */
1250 pnv_ioda_reserve_pe(phb, 0);
1251 pnv_ioda_setup_npu_PEs(hose->bus);
1252 }
1253 }
1254 }
1255
1256 #ifdef CONFIG_PCI_IOV
1257 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1258 {
1259 struct pci_bus *bus;
1260 struct pci_controller *hose;
1261 struct pnv_phb *phb;
1262 struct pci_dn *pdn;
1263 int i, j;
1264 int m64_bars;
1265
1266 bus = pdev->bus;
1267 hose = pci_bus_to_host(bus);
1268 phb = hose->private_data;
1269 pdn = pci_get_pdn(pdev);
1270
1271 if (pdn->m64_single_mode)
1272 m64_bars = num_vfs;
1273 else
1274 m64_bars = 1;
1275
1276 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1277 for (j = 0; j < m64_bars; j++) {
1278 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1279 continue;
1280 opal_pci_phb_mmio_enable(phb->opal_id,
1281 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1282 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1283 pdn->m64_map[j][i] = IODA_INVALID_M64;
1284 }
1285
1286 kfree(pdn->m64_map);
1287 return 0;
1288 }
1289
1290 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1291 {
1292 struct pci_bus *bus;
1293 struct pci_controller *hose;
1294 struct pnv_phb *phb;
1295 struct pci_dn *pdn;
1296 unsigned int win;
1297 struct resource *res;
1298 int i, j;
1299 int64_t rc;
1300 int total_vfs;
1301 resource_size_t size, start;
1302 int pe_num;
1303 int m64_bars;
1304
1305 bus = pdev->bus;
1306 hose = pci_bus_to_host(bus);
1307 phb = hose->private_data;
1308 pdn = pci_get_pdn(pdev);
1309 total_vfs = pci_sriov_get_totalvfs(pdev);
1310
1311 if (pdn->m64_single_mode)
1312 m64_bars = num_vfs;
1313 else
1314 m64_bars = 1;
1315
1316 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1317 if (!pdn->m64_map)
1318 return -ENOMEM;
1319 /* Initialize the m64_map to IODA_INVALID_M64 */
1320 for (i = 0; i < m64_bars ; i++)
1321 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1322 pdn->m64_map[i][j] = IODA_INVALID_M64;
1323
1324
1325 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1326 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1327 if (!res->flags || !res->parent)
1328 continue;
1329
1330 for (j = 0; j < m64_bars; j++) {
1331 do {
1332 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1333 phb->ioda.m64_bar_idx + 1, 0);
1334
1335 if (win >= phb->ioda.m64_bar_idx + 1)
1336 goto m64_failed;
1337 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1338
1339 pdn->m64_map[j][i] = win;
1340
1341 if (pdn->m64_single_mode) {
1342 size = pci_iov_resource_size(pdev,
1343 PCI_IOV_RESOURCES + i);
1344 start = res->start + size * j;
1345 } else {
1346 size = resource_size(res);
1347 start = res->start;
1348 }
1349
1350 /* Map the M64 here */
1351 if (pdn->m64_single_mode) {
1352 pe_num = pdn->pe_num_map[j];
1353 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1354 pe_num, OPAL_M64_WINDOW_TYPE,
1355 pdn->m64_map[j][i], 0);
1356 }
1357
1358 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1359 OPAL_M64_WINDOW_TYPE,
1360 pdn->m64_map[j][i],
1361 start,
1362 0, /* unused */
1363 size);
1364
1365
1366 if (rc != OPAL_SUCCESS) {
1367 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1368 win, rc);
1369 goto m64_failed;
1370 }
1371
1372 if (pdn->m64_single_mode)
1373 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1374 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1375 else
1376 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1377 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1378
1379 if (rc != OPAL_SUCCESS) {
1380 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1381 win, rc);
1382 goto m64_failed;
1383 }
1384 }
1385 }
1386 return 0;
1387
1388 m64_failed:
1389 pnv_pci_vf_release_m64(pdev, num_vfs);
1390 return -EBUSY;
1391 }
1392
1393 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1394 int num);
1395 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1396
1397 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1398 {
1399 struct iommu_table *tbl;
1400 int64_t rc;
1401
1402 tbl = pe->table_group.tables[0];
1403 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1404 if (rc)
1405 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1406
1407 pnv_pci_ioda2_set_bypass(pe, false);
1408 if (pe->table_group.group) {
1409 iommu_group_put(pe->table_group.group);
1410 BUG_ON(pe->table_group.group);
1411 }
1412 pnv_pci_ioda2_table_free_pages(tbl);
1413 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1414 }
1415
1416 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1417 {
1418 struct pci_bus *bus;
1419 struct pci_controller *hose;
1420 struct pnv_phb *phb;
1421 struct pnv_ioda_pe *pe, *pe_n;
1422 struct pci_dn *pdn;
1423
1424 bus = pdev->bus;
1425 hose = pci_bus_to_host(bus);
1426 phb = hose->private_data;
1427 pdn = pci_get_pdn(pdev);
1428
1429 if (!pdev->is_physfn)
1430 return;
1431
1432 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1433 if (pe->parent_dev != pdev)
1434 continue;
1435
1436 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1437
1438 /* Remove from list */
1439 mutex_lock(&phb->ioda.pe_list_mutex);
1440 list_del(&pe->list);
1441 mutex_unlock(&phb->ioda.pe_list_mutex);
1442
1443 pnv_ioda_deconfigure_pe(phb, pe);
1444
1445 pnv_ioda_free_pe(pe);
1446 }
1447 }
1448
1449 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1450 {
1451 struct pci_bus *bus;
1452 struct pci_controller *hose;
1453 struct pnv_phb *phb;
1454 struct pnv_ioda_pe *pe;
1455 struct pci_dn *pdn;
1456 struct pci_sriov *iov;
1457 u16 num_vfs, i;
1458
1459 bus = pdev->bus;
1460 hose = pci_bus_to_host(bus);
1461 phb = hose->private_data;
1462 pdn = pci_get_pdn(pdev);
1463 iov = pdev->sriov;
1464 num_vfs = pdn->num_vfs;
1465
1466 /* Release VF PEs */
1467 pnv_ioda_release_vf_PE(pdev);
1468
1469 if (phb->type == PNV_PHB_IODA2) {
1470 if (!pdn->m64_single_mode)
1471 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1472
1473 /* Release M64 windows */
1474 pnv_pci_vf_release_m64(pdev, num_vfs);
1475
1476 /* Release PE numbers */
1477 if (pdn->m64_single_mode) {
1478 for (i = 0; i < num_vfs; i++) {
1479 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1480 continue;
1481
1482 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1483 pnv_ioda_free_pe(pe);
1484 }
1485 } else
1486 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1487 /* Releasing pe_num_map */
1488 kfree(pdn->pe_num_map);
1489 }
1490 }
1491
1492 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1493 struct pnv_ioda_pe *pe);
1494 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1495 {
1496 struct pci_bus *bus;
1497 struct pci_controller *hose;
1498 struct pnv_phb *phb;
1499 struct pnv_ioda_pe *pe;
1500 int pe_num;
1501 u16 vf_index;
1502 struct pci_dn *pdn;
1503
1504 bus = pdev->bus;
1505 hose = pci_bus_to_host(bus);
1506 phb = hose->private_data;
1507 pdn = pci_get_pdn(pdev);
1508
1509 if (!pdev->is_physfn)
1510 return;
1511
1512 /* Reserve PE for each VF */
1513 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1514 if (pdn->m64_single_mode)
1515 pe_num = pdn->pe_num_map[vf_index];
1516 else
1517 pe_num = *pdn->pe_num_map + vf_index;
1518
1519 pe = &phb->ioda.pe_array[pe_num];
1520 pe->pe_number = pe_num;
1521 pe->phb = phb;
1522 pe->flags = PNV_IODA_PE_VF;
1523 pe->pbus = NULL;
1524 pe->parent_dev = pdev;
1525 pe->mve_number = -1;
1526 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1527 pci_iov_virtfn_devfn(pdev, vf_index);
1528
1529 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1530 hose->global_number, pdev->bus->number,
1531 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1532 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1533
1534 if (pnv_ioda_configure_pe(phb, pe)) {
1535 /* XXX What do we do here ? */
1536 pnv_ioda_free_pe(pe);
1537 pe->pdev = NULL;
1538 continue;
1539 }
1540
1541 /* Put PE to the list */
1542 mutex_lock(&phb->ioda.pe_list_mutex);
1543 list_add_tail(&pe->list, &phb->ioda.pe_list);
1544 mutex_unlock(&phb->ioda.pe_list_mutex);
1545
1546 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1547 }
1548 }
1549
1550 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1551 {
1552 struct pci_bus *bus;
1553 struct pci_controller *hose;
1554 struct pnv_phb *phb;
1555 struct pnv_ioda_pe *pe;
1556 struct pci_dn *pdn;
1557 int ret;
1558 u16 i;
1559
1560 bus = pdev->bus;
1561 hose = pci_bus_to_host(bus);
1562 phb = hose->private_data;
1563 pdn = pci_get_pdn(pdev);
1564
1565 if (phb->type == PNV_PHB_IODA2) {
1566 if (!pdn->vfs_expanded) {
1567 dev_info(&pdev->dev, "don't support this SRIOV device"
1568 " with non 64bit-prefetchable IOV BAR\n");
1569 return -ENOSPC;
1570 }
1571
1572 /*
1573 * When M64 BARs functions in Single PE mode, the number of VFs
1574 * could be enabled must be less than the number of M64 BARs.
1575 */
1576 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1577 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1578 return -EBUSY;
1579 }
1580
1581 /* Allocating pe_num_map */
1582 if (pdn->m64_single_mode)
1583 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1584 GFP_KERNEL);
1585 else
1586 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1587
1588 if (!pdn->pe_num_map)
1589 return -ENOMEM;
1590
1591 if (pdn->m64_single_mode)
1592 for (i = 0; i < num_vfs; i++)
1593 pdn->pe_num_map[i] = IODA_INVALID_PE;
1594
1595 /* Calculate available PE for required VFs */
1596 if (pdn->m64_single_mode) {
1597 for (i = 0; i < num_vfs; i++) {
1598 pe = pnv_ioda_alloc_pe(phb);
1599 if (!pe) {
1600 ret = -EBUSY;
1601 goto m64_failed;
1602 }
1603
1604 pdn->pe_num_map[i] = pe->pe_number;
1605 }
1606 } else {
1607 mutex_lock(&phb->ioda.pe_alloc_mutex);
1608 *pdn->pe_num_map = bitmap_find_next_zero_area(
1609 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1610 0, num_vfs, 0);
1611 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1612 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1613 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1614 kfree(pdn->pe_num_map);
1615 return -EBUSY;
1616 }
1617 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1618 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1619 }
1620 pdn->num_vfs = num_vfs;
1621
1622 /* Assign M64 window accordingly */
1623 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1624 if (ret) {
1625 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1626 goto m64_failed;
1627 }
1628
1629 /*
1630 * When using one M64 BAR to map one IOV BAR, we need to shift
1631 * the IOV BAR according to the PE# allocated to the VFs.
1632 * Otherwise, the PE# for the VF will conflict with others.
1633 */
1634 if (!pdn->m64_single_mode) {
1635 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1636 if (ret)
1637 goto m64_failed;
1638 }
1639 }
1640
1641 /* Setup VF PEs */
1642 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1643
1644 return 0;
1645
1646 m64_failed:
1647 if (pdn->m64_single_mode) {
1648 for (i = 0; i < num_vfs; i++) {
1649 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1650 continue;
1651
1652 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1653 pnv_ioda_free_pe(pe);
1654 }
1655 } else
1656 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1657
1658 /* Releasing pe_num_map */
1659 kfree(pdn->pe_num_map);
1660
1661 return ret;
1662 }
1663
1664 int pcibios_sriov_disable(struct pci_dev *pdev)
1665 {
1666 pnv_pci_sriov_disable(pdev);
1667
1668 /* Release PCI data */
1669 remove_dev_pci_data(pdev);
1670 return 0;
1671 }
1672
1673 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1674 {
1675 /* Allocate PCI data */
1676 add_dev_pci_data(pdev);
1677
1678 return pnv_pci_sriov_enable(pdev, num_vfs);
1679 }
1680 #endif /* CONFIG_PCI_IOV */
1681
1682 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1683 {
1684 struct pci_dn *pdn = pci_get_pdn(pdev);
1685 struct pnv_ioda_pe *pe;
1686
1687 /*
1688 * The function can be called while the PE#
1689 * hasn't been assigned. Do nothing for the
1690 * case.
1691 */
1692 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1693 return;
1694
1695 pe = &phb->ioda.pe_array[pdn->pe_number];
1696 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1697 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1698 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1699 /*
1700 * Note: iommu_add_device() will fail here as
1701 * for physical PE: the device is already added by now;
1702 * for virtual PE: sysfs entries are not ready yet and
1703 * tce_iommu_bus_notifier will add the device to a group later.
1704 */
1705 }
1706
1707 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1708 {
1709 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1710 struct pnv_phb *phb = hose->private_data;
1711 struct pci_dn *pdn = pci_get_pdn(pdev);
1712 struct pnv_ioda_pe *pe;
1713 uint64_t top;
1714 bool bypass = false;
1715
1716 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1717 return -ENODEV;;
1718
1719 pe = &phb->ioda.pe_array[pdn->pe_number];
1720 if (pe->tce_bypass_enabled) {
1721 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1722 bypass = (dma_mask >= top);
1723 }
1724
1725 if (bypass) {
1726 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1727 set_dma_ops(&pdev->dev, &dma_direct_ops);
1728 } else {
1729 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1730 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1731 }
1732 *pdev->dev.dma_mask = dma_mask;
1733
1734 /* Update peer npu devices */
1735 pnv_npu_try_dma_set_bypass(pdev, bypass);
1736
1737 return 0;
1738 }
1739
1740 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1741 {
1742 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1743 struct pnv_phb *phb = hose->private_data;
1744 struct pci_dn *pdn = pci_get_pdn(pdev);
1745 struct pnv_ioda_pe *pe;
1746 u64 end, mask;
1747
1748 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1749 return 0;
1750
1751 pe = &phb->ioda.pe_array[pdn->pe_number];
1752 if (!pe->tce_bypass_enabled)
1753 return __dma_get_required_mask(&pdev->dev);
1754
1755
1756 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1757 mask = 1ULL << (fls64(end) - 1);
1758 mask += mask - 1;
1759
1760 return mask;
1761 }
1762
1763 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1764 struct pci_bus *bus)
1765 {
1766 struct pci_dev *dev;
1767
1768 list_for_each_entry(dev, &bus->devices, bus_list) {
1769 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1770 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1771 iommu_add_device(&dev->dev);
1772
1773 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1774 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1775 }
1776 }
1777
1778 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1779 bool real_mode)
1780 {
1781 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1782 (phb->regs + 0x210);
1783 }
1784
1785 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1786 unsigned long index, unsigned long npages, bool rm)
1787 {
1788 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1789 &tbl->it_group_list, struct iommu_table_group_link,
1790 next);
1791 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1792 struct pnv_ioda_pe, table_group);
1793 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1794 unsigned long start, end, inc;
1795
1796 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1797 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1798 npages - 1);
1799
1800 /* p7ioc-style invalidation, 2 TCEs per write */
1801 start |= (1ull << 63);
1802 end |= (1ull << 63);
1803 inc = 16;
1804 end |= inc - 1; /* round up end to be different than start */
1805
1806 mb(); /* Ensure above stores are visible */
1807 while (start <= end) {
1808 if (rm)
1809 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1810 else
1811 __raw_writeq(cpu_to_be64(start), invalidate);
1812 start += inc;
1813 }
1814
1815 /*
1816 * The iommu layer will do another mb() for us on build()
1817 * and we don't care on free()
1818 */
1819 }
1820
1821 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1822 long npages, unsigned long uaddr,
1823 enum dma_data_direction direction,
1824 unsigned long attrs)
1825 {
1826 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1827 attrs);
1828
1829 if (!ret)
1830 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1831
1832 return ret;
1833 }
1834
1835 #ifdef CONFIG_IOMMU_API
1836 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1837 unsigned long *hpa, enum dma_data_direction *direction)
1838 {
1839 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1840
1841 if (!ret)
1842 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1843
1844 return ret;
1845 }
1846 #endif
1847
1848 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1849 long npages)
1850 {
1851 pnv_tce_free(tbl, index, npages);
1852
1853 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1854 }
1855
1856 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1857 .set = pnv_ioda1_tce_build,
1858 #ifdef CONFIG_IOMMU_API
1859 .exchange = pnv_ioda1_tce_xchg,
1860 #endif
1861 .clear = pnv_ioda1_tce_free,
1862 .get = pnv_tce_get,
1863 };
1864
1865 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1866 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1867 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1868
1869 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1870 {
1871 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1872 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1873
1874 mb(); /* Ensure previous TCE table stores are visible */
1875 if (rm)
1876 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1877 else
1878 __raw_writeq(cpu_to_be64(val), invalidate);
1879 }
1880
1881 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1882 {
1883 /* 01xb - invalidate TCEs that match the specified PE# */
1884 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1885 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1886
1887 mb(); /* Ensure above stores are visible */
1888 __raw_writeq(cpu_to_be64(val), invalidate);
1889 }
1890
1891 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1892 unsigned shift, unsigned long index,
1893 unsigned long npages)
1894 {
1895 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1896 unsigned long start, end, inc;
1897
1898 /* We'll invalidate DMA address in PE scope */
1899 start = PHB3_TCE_KILL_INVAL_ONE;
1900 start |= (pe->pe_number & 0xFF);
1901 end = start;
1902
1903 /* Figure out the start, end and step */
1904 start |= (index << shift);
1905 end |= ((index + npages - 1) << shift);
1906 inc = (0x1ull << shift);
1907 mb();
1908
1909 while (start <= end) {
1910 if (rm)
1911 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1912 else
1913 __raw_writeq(cpu_to_be64(start), invalidate);
1914 start += inc;
1915 }
1916 }
1917
1918 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1919 {
1920 struct pnv_phb *phb = pe->phb;
1921
1922 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1923 pnv_pci_phb3_tce_invalidate_pe(pe);
1924 else
1925 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1926 pe->pe_number, 0, 0, 0);
1927 }
1928
1929 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1930 unsigned long index, unsigned long npages, bool rm)
1931 {
1932 struct iommu_table_group_link *tgl;
1933
1934 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1935 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1936 struct pnv_ioda_pe, table_group);
1937 struct pnv_phb *phb = pe->phb;
1938 unsigned int shift = tbl->it_page_shift;
1939
1940 if (phb->type == PNV_PHB_NPU) {
1941 /*
1942 * The NVLink hardware does not support TCE kill
1943 * per TCE entry so we have to invalidate
1944 * the entire cache for it.
1945 */
1946 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1947 continue;
1948 }
1949 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1950 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1951 index, npages);
1952 else if (rm)
1953 opal_rm_pci_tce_kill(phb->opal_id,
1954 OPAL_PCI_TCE_KILL_PAGES,
1955 pe->pe_number, 1u << shift,
1956 index << shift, npages);
1957 else
1958 opal_pci_tce_kill(phb->opal_id,
1959 OPAL_PCI_TCE_KILL_PAGES,
1960 pe->pe_number, 1u << shift,
1961 index << shift, npages);
1962 }
1963 }
1964
1965 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1966 long npages, unsigned long uaddr,
1967 enum dma_data_direction direction,
1968 unsigned long attrs)
1969 {
1970 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1971 attrs);
1972
1973 if (!ret)
1974 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1975
1976 return ret;
1977 }
1978
1979 #ifdef CONFIG_IOMMU_API
1980 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1981 unsigned long *hpa, enum dma_data_direction *direction)
1982 {
1983 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1984
1985 if (!ret)
1986 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1987
1988 return ret;
1989 }
1990 #endif
1991
1992 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1993 long npages)
1994 {
1995 pnv_tce_free(tbl, index, npages);
1996
1997 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1998 }
1999
2000 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2001 {
2002 pnv_pci_ioda2_table_free_pages(tbl);
2003 iommu_free_table(tbl, "pnv");
2004 }
2005
2006 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2007 .set = pnv_ioda2_tce_build,
2008 #ifdef CONFIG_IOMMU_API
2009 .exchange = pnv_ioda2_tce_xchg,
2010 #endif
2011 .clear = pnv_ioda2_tce_free,
2012 .get = pnv_tce_get,
2013 .free = pnv_ioda2_table_free,
2014 };
2015
2016 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2017 {
2018 unsigned int *weight = (unsigned int *)data;
2019
2020 /* This is quite simplistic. The "base" weight of a device
2021 * is 10. 0 means no DMA is to be accounted for it.
2022 */
2023 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2024 return 0;
2025
2026 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2027 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2028 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2029 *weight += 3;
2030 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2031 *weight += 15;
2032 else
2033 *weight += 10;
2034
2035 return 0;
2036 }
2037
2038 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2039 {
2040 unsigned int weight = 0;
2041
2042 /* SRIOV VF has same DMA32 weight as its PF */
2043 #ifdef CONFIG_PCI_IOV
2044 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2045 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2046 return weight;
2047 }
2048 #endif
2049
2050 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2051 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2052 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2053 struct pci_dev *pdev;
2054
2055 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2056 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2057 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2058 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2059 }
2060
2061 return weight;
2062 }
2063
2064 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2065 struct pnv_ioda_pe *pe)
2066 {
2067
2068 struct page *tce_mem = NULL;
2069 struct iommu_table *tbl;
2070 unsigned int weight, total_weight = 0;
2071 unsigned int tce32_segsz, base, segs, avail, i;
2072 int64_t rc;
2073 void *addr;
2074
2075 /* XXX FIXME: Handle 64-bit only DMA devices */
2076 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2077 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2078 weight = pnv_pci_ioda_pe_dma_weight(pe);
2079 if (!weight)
2080 return;
2081
2082 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2083 &total_weight);
2084 segs = (weight * phb->ioda.dma32_count) / total_weight;
2085 if (!segs)
2086 segs = 1;
2087
2088 /*
2089 * Allocate contiguous DMA32 segments. We begin with the expected
2090 * number of segments. With one more attempt, the number of DMA32
2091 * segments to be allocated is decreased by one until one segment
2092 * is allocated successfully.
2093 */
2094 do {
2095 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2096 for (avail = 0, i = base; i < base + segs; i++) {
2097 if (phb->ioda.dma32_segmap[i] ==
2098 IODA_INVALID_PE)
2099 avail++;
2100 }
2101
2102 if (avail == segs)
2103 goto found;
2104 }
2105 } while (--segs);
2106
2107 if (!segs) {
2108 pe_warn(pe, "No available DMA32 segments\n");
2109 return;
2110 }
2111
2112 found:
2113 tbl = pnv_pci_table_alloc(phb->hose->node);
2114 iommu_register_group(&pe->table_group, phb->hose->global_number,
2115 pe->pe_number);
2116 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2117
2118 /* Grab a 32-bit TCE table */
2119 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2120 weight, total_weight, base, segs);
2121 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2122 base * PNV_IODA1_DMA32_SEGSIZE,
2123 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2124
2125 /* XXX Currently, we allocate one big contiguous table for the
2126 * TCEs. We only really need one chunk per 256M of TCE space
2127 * (ie per segment) but that's an optimization for later, it
2128 * requires some added smarts with our get/put_tce implementation
2129 *
2130 * Each TCE page is 4KB in size and each TCE entry occupies 8
2131 * bytes
2132 */
2133 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2134 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2135 get_order(tce32_segsz * segs));
2136 if (!tce_mem) {
2137 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2138 goto fail;
2139 }
2140 addr = page_address(tce_mem);
2141 memset(addr, 0, tce32_segsz * segs);
2142
2143 /* Configure HW */
2144 for (i = 0; i < segs; i++) {
2145 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2146 pe->pe_number,
2147 base + i, 1,
2148 __pa(addr) + tce32_segsz * i,
2149 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2150 if (rc) {
2151 pe_err(pe, " Failed to configure 32-bit TCE table,"
2152 " err %ld\n", rc);
2153 goto fail;
2154 }
2155 }
2156
2157 /* Setup DMA32 segment mapping */
2158 for (i = base; i < base + segs; i++)
2159 phb->ioda.dma32_segmap[i] = pe->pe_number;
2160
2161 /* Setup linux iommu table */
2162 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2163 base * PNV_IODA1_DMA32_SEGSIZE,
2164 IOMMU_PAGE_SHIFT_4K);
2165
2166 tbl->it_ops = &pnv_ioda1_iommu_ops;
2167 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2168 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2169 iommu_init_table(tbl, phb->hose->node);
2170
2171 if (pe->flags & PNV_IODA_PE_DEV) {
2172 /*
2173 * Setting table base here only for carrying iommu_group
2174 * further down to let iommu_add_device() do the job.
2175 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2176 */
2177 set_iommu_table_base(&pe->pdev->dev, tbl);
2178 iommu_add_device(&pe->pdev->dev);
2179 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2180 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2181
2182 return;
2183 fail:
2184 /* XXX Failure: Try to fallback to 64-bit only ? */
2185 if (tce_mem)
2186 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2187 if (tbl) {
2188 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2189 iommu_free_table(tbl, "pnv");
2190 }
2191 }
2192
2193 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2194 int num, struct iommu_table *tbl)
2195 {
2196 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2197 table_group);
2198 struct pnv_phb *phb = pe->phb;
2199 int64_t rc;
2200 const unsigned long size = tbl->it_indirect_levels ?
2201 tbl->it_level_size : tbl->it_size;
2202 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2203 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2204
2205 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2206 start_addr, start_addr + win_size - 1,
2207 IOMMU_PAGE_SIZE(tbl));
2208
2209 /*
2210 * Map TCE table through TVT. The TVE index is the PE number
2211 * shifted by 1 bit for 32-bits DMA space.
2212 */
2213 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2214 pe->pe_number,
2215 (pe->pe_number << 1) + num,
2216 tbl->it_indirect_levels + 1,
2217 __pa(tbl->it_base),
2218 size << 3,
2219 IOMMU_PAGE_SIZE(tbl));
2220 if (rc) {
2221 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2222 return rc;
2223 }
2224
2225 pnv_pci_link_table_and_group(phb->hose->node, num,
2226 tbl, &pe->table_group);
2227 pnv_pci_ioda2_tce_invalidate_pe(pe);
2228
2229 return 0;
2230 }
2231
2232 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2233 {
2234 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2235 int64_t rc;
2236
2237 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2238 if (enable) {
2239 phys_addr_t top = memblock_end_of_DRAM();
2240
2241 top = roundup_pow_of_two(top);
2242 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2243 pe->pe_number,
2244 window_id,
2245 pe->tce_bypass_base,
2246 top);
2247 } else {
2248 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2249 pe->pe_number,
2250 window_id,
2251 pe->tce_bypass_base,
2252 0);
2253 }
2254 if (rc)
2255 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2256 else
2257 pe->tce_bypass_enabled = enable;
2258 }
2259
2260 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2261 __u32 page_shift, __u64 window_size, __u32 levels,
2262 struct iommu_table *tbl);
2263
2264 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2265 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2266 struct iommu_table **ptbl)
2267 {
2268 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2269 table_group);
2270 int nid = pe->phb->hose->node;
2271 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2272 long ret;
2273 struct iommu_table *tbl;
2274
2275 tbl = pnv_pci_table_alloc(nid);
2276 if (!tbl)
2277 return -ENOMEM;
2278
2279 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2280 bus_offset, page_shift, window_size,
2281 levels, tbl);
2282 if (ret) {
2283 iommu_free_table(tbl, "pnv");
2284 return ret;
2285 }
2286
2287 tbl->it_ops = &pnv_ioda2_iommu_ops;
2288
2289 *ptbl = tbl;
2290
2291 return 0;
2292 }
2293
2294 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2295 {
2296 struct iommu_table *tbl = NULL;
2297 long rc;
2298
2299 /*
2300 * crashkernel= specifies the kdump kernel's maximum memory at
2301 * some offset and there is no guaranteed the result is a power
2302 * of 2, which will cause errors later.
2303 */
2304 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2305
2306 /*
2307 * In memory constrained environments, e.g. kdump kernel, the
2308 * DMA window can be larger than available memory, which will
2309 * cause errors later.
2310 */
2311 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2312
2313 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2314 IOMMU_PAGE_SHIFT_4K,
2315 window_size,
2316 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2317 if (rc) {
2318 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2319 rc);
2320 return rc;
2321 }
2322
2323 iommu_init_table(tbl, pe->phb->hose->node);
2324
2325 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2326 if (rc) {
2327 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2328 rc);
2329 pnv_ioda2_table_free(tbl);
2330 return rc;
2331 }
2332
2333 if (!pnv_iommu_bypass_disabled)
2334 pnv_pci_ioda2_set_bypass(pe, true);
2335
2336 /*
2337 * Setting table base here only for carrying iommu_group
2338 * further down to let iommu_add_device() do the job.
2339 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2340 */
2341 if (pe->flags & PNV_IODA_PE_DEV)
2342 set_iommu_table_base(&pe->pdev->dev, tbl);
2343
2344 return 0;
2345 }
2346
2347 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2348 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2349 int num)
2350 {
2351 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2352 table_group);
2353 struct pnv_phb *phb = pe->phb;
2354 long ret;
2355
2356 pe_info(pe, "Removing DMA window #%d\n", num);
2357
2358 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2359 (pe->pe_number << 1) + num,
2360 0/* levels */, 0/* table address */,
2361 0/* table size */, 0/* page size */);
2362 if (ret)
2363 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2364 else
2365 pnv_pci_ioda2_tce_invalidate_pe(pe);
2366
2367 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2368
2369 return ret;
2370 }
2371 #endif
2372
2373 #ifdef CONFIG_IOMMU_API
2374 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2375 __u64 window_size, __u32 levels)
2376 {
2377 unsigned long bytes = 0;
2378 const unsigned window_shift = ilog2(window_size);
2379 unsigned entries_shift = window_shift - page_shift;
2380 unsigned table_shift = entries_shift + 3;
2381 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2382 unsigned long direct_table_size;
2383
2384 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2385 (window_size > memory_hotplug_max()) ||
2386 !is_power_of_2(window_size))
2387 return 0;
2388
2389 /* Calculate a direct table size from window_size and levels */
2390 entries_shift = (entries_shift + levels - 1) / levels;
2391 table_shift = entries_shift + 3;
2392 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2393 direct_table_size = 1UL << table_shift;
2394
2395 for ( ; levels; --levels) {
2396 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2397
2398 tce_table_size /= direct_table_size;
2399 tce_table_size <<= 3;
2400 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2401 }
2402
2403 return bytes;
2404 }
2405
2406 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2407 {
2408 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2409 table_group);
2410 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2411 struct iommu_table *tbl = pe->table_group.tables[0];
2412
2413 pnv_pci_ioda2_set_bypass(pe, false);
2414 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2415 pnv_ioda2_table_free(tbl);
2416 }
2417
2418 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2419 {
2420 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2421 table_group);
2422
2423 pnv_pci_ioda2_setup_default_config(pe);
2424 }
2425
2426 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2427 .get_table_size = pnv_pci_ioda2_get_table_size,
2428 .create_table = pnv_pci_ioda2_create_table,
2429 .set_window = pnv_pci_ioda2_set_window,
2430 .unset_window = pnv_pci_ioda2_unset_window,
2431 .take_ownership = pnv_ioda2_take_ownership,
2432 .release_ownership = pnv_ioda2_release_ownership,
2433 };
2434
2435 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2436 {
2437 struct pci_controller *hose;
2438 struct pnv_phb *phb;
2439 struct pnv_ioda_pe **ptmppe = opaque;
2440 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2441 struct pci_dn *pdn = pci_get_pdn(pdev);
2442
2443 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2444 return 0;
2445
2446 hose = pci_bus_to_host(pdev->bus);
2447 phb = hose->private_data;
2448 if (phb->type != PNV_PHB_NPU)
2449 return 0;
2450
2451 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2452
2453 return 1;
2454 }
2455
2456 /*
2457 * This returns PE of associated NPU.
2458 * This assumes that NPU is in the same IOMMU group with GPU and there is
2459 * no other PEs.
2460 */
2461 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2462 struct iommu_table_group *table_group)
2463 {
2464 struct pnv_ioda_pe *npe = NULL;
2465 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2466 gpe_table_group_to_npe_cb);
2467
2468 BUG_ON(!ret || !npe);
2469
2470 return npe;
2471 }
2472
2473 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2474 int num, struct iommu_table *tbl)
2475 {
2476 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2477
2478 if (ret)
2479 return ret;
2480
2481 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2482 if (ret)
2483 pnv_pci_ioda2_unset_window(table_group, num);
2484
2485 return ret;
2486 }
2487
2488 static long pnv_pci_ioda2_npu_unset_window(
2489 struct iommu_table_group *table_group,
2490 int num)
2491 {
2492 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2493
2494 if (ret)
2495 return ret;
2496
2497 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2498 }
2499
2500 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2501 {
2502 /*
2503 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2504 * the iommu_table if 32bit DMA is enabled.
2505 */
2506 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2507 pnv_ioda2_take_ownership(table_group);
2508 }
2509
2510 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2511 .get_table_size = pnv_pci_ioda2_get_table_size,
2512 .create_table = pnv_pci_ioda2_create_table,
2513 .set_window = pnv_pci_ioda2_npu_set_window,
2514 .unset_window = pnv_pci_ioda2_npu_unset_window,
2515 .take_ownership = pnv_ioda2_npu_take_ownership,
2516 .release_ownership = pnv_ioda2_release_ownership,
2517 };
2518
2519 static void pnv_pci_ioda_setup_iommu_api(void)
2520 {
2521 struct pci_controller *hose, *tmp;
2522 struct pnv_phb *phb;
2523 struct pnv_ioda_pe *pe, *gpe;
2524
2525 /*
2526 * Now we have all PHBs discovered, time to add NPU devices to
2527 * the corresponding IOMMU groups.
2528 */
2529 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2530 phb = hose->private_data;
2531
2532 if (phb->type != PNV_PHB_NPU)
2533 continue;
2534
2535 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2536 gpe = pnv_pci_npu_setup_iommu(pe);
2537 if (gpe)
2538 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2539 }
2540 }
2541 }
2542 #else /* !CONFIG_IOMMU_API */
2543 static void pnv_pci_ioda_setup_iommu_api(void) { };
2544 #endif
2545
2546 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2547 unsigned levels, unsigned long limit,
2548 unsigned long *current_offset, unsigned long *total_allocated)
2549 {
2550 struct page *tce_mem = NULL;
2551 __be64 *addr, *tmp;
2552 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2553 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2554 unsigned entries = 1UL << (shift - 3);
2555 long i;
2556
2557 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2558 if (!tce_mem) {
2559 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2560 return NULL;
2561 }
2562 addr = page_address(tce_mem);
2563 memset(addr, 0, allocated);
2564 *total_allocated += allocated;
2565
2566 --levels;
2567 if (!levels) {
2568 *current_offset += allocated;
2569 return addr;
2570 }
2571
2572 for (i = 0; i < entries; ++i) {
2573 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2574 levels, limit, current_offset, total_allocated);
2575 if (!tmp)
2576 break;
2577
2578 addr[i] = cpu_to_be64(__pa(tmp) |
2579 TCE_PCI_READ | TCE_PCI_WRITE);
2580
2581 if (*current_offset >= limit)
2582 break;
2583 }
2584
2585 return addr;
2586 }
2587
2588 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2589 unsigned long size, unsigned level);
2590
2591 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2592 __u32 page_shift, __u64 window_size, __u32 levels,
2593 struct iommu_table *tbl)
2594 {
2595 void *addr;
2596 unsigned long offset = 0, level_shift, total_allocated = 0;
2597 const unsigned window_shift = ilog2(window_size);
2598 unsigned entries_shift = window_shift - page_shift;
2599 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2600 const unsigned long tce_table_size = 1UL << table_shift;
2601
2602 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2603 return -EINVAL;
2604
2605 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2606 return -EINVAL;
2607
2608 /* Adjust direct table size from window_size and levels */
2609 entries_shift = (entries_shift + levels - 1) / levels;
2610 level_shift = entries_shift + 3;
2611 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2612
2613 /* Allocate TCE table */
2614 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2615 levels, tce_table_size, &offset, &total_allocated);
2616
2617 /* addr==NULL means that the first level allocation failed */
2618 if (!addr)
2619 return -ENOMEM;
2620
2621 /*
2622 * First level was allocated but some lower level failed as
2623 * we did not allocate as much as we wanted,
2624 * release partially allocated table.
2625 */
2626 if (offset < tce_table_size) {
2627 pnv_pci_ioda2_table_do_free_pages(addr,
2628 1ULL << (level_shift - 3), levels - 1);
2629 return -ENOMEM;
2630 }
2631
2632 /* Setup linux iommu table */
2633 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2634 page_shift);
2635 tbl->it_level_size = 1ULL << (level_shift - 3);
2636 tbl->it_indirect_levels = levels - 1;
2637 tbl->it_allocated_size = total_allocated;
2638
2639 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2640 window_size, tce_table_size, bus_offset);
2641
2642 return 0;
2643 }
2644
2645 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2646 unsigned long size, unsigned level)
2647 {
2648 const unsigned long addr_ul = (unsigned long) addr &
2649 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2650
2651 if (level) {
2652 long i;
2653 u64 *tmp = (u64 *) addr_ul;
2654
2655 for (i = 0; i < size; ++i) {
2656 unsigned long hpa = be64_to_cpu(tmp[i]);
2657
2658 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2659 continue;
2660
2661 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2662 level - 1);
2663 }
2664 }
2665
2666 free_pages(addr_ul, get_order(size << 3));
2667 }
2668
2669 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2670 {
2671 const unsigned long size = tbl->it_indirect_levels ?
2672 tbl->it_level_size : tbl->it_size;
2673
2674 if (!tbl->it_size)
2675 return;
2676
2677 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2678 tbl->it_indirect_levels);
2679 }
2680
2681 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2682 struct pnv_ioda_pe *pe)
2683 {
2684 int64_t rc;
2685
2686 if (!pnv_pci_ioda_pe_dma_weight(pe))
2687 return;
2688
2689 /* TVE #1 is selected by PCI address bit 59 */
2690 pe->tce_bypass_base = 1ull << 59;
2691
2692 iommu_register_group(&pe->table_group, phb->hose->global_number,
2693 pe->pe_number);
2694
2695 /* The PE will reserve all possible 32-bits space */
2696 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2697 phb->ioda.m32_pci_base);
2698
2699 /* Setup linux iommu table */
2700 pe->table_group.tce32_start = 0;
2701 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2702 pe->table_group.max_dynamic_windows_supported =
2703 IOMMU_TABLE_GROUP_MAX_TABLES;
2704 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2705 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2706 #ifdef CONFIG_IOMMU_API
2707 pe->table_group.ops = &pnv_pci_ioda2_ops;
2708 #endif
2709
2710 rc = pnv_pci_ioda2_setup_default_config(pe);
2711 if (rc)
2712 return;
2713
2714 if (pe->flags & PNV_IODA_PE_DEV)
2715 iommu_add_device(&pe->pdev->dev);
2716 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2717 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2718 }
2719
2720 #ifdef CONFIG_PCI_MSI
2721 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2722 {
2723 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2724 struct irq_chip *chip = irq_data_get_irq_chip(d);
2725 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2726 ioda.irq_chip);
2727 int64_t rc;
2728
2729 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2730 WARN_ON_ONCE(rc);
2731
2732 icp_native_eoi(d);
2733 }
2734
2735
2736 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2737 {
2738 struct irq_data *idata;
2739 struct irq_chip *ichip;
2740
2741 /* The MSI EOI OPAL call is only needed on PHB3 */
2742 if (phb->model != PNV_PHB_MODEL_PHB3)
2743 return;
2744
2745 if (!phb->ioda.irq_chip_init) {
2746 /*
2747 * First time we setup an MSI IRQ, we need to setup the
2748 * corresponding IRQ chip to route correctly.
2749 */
2750 idata = irq_get_irq_data(virq);
2751 ichip = irq_data_get_irq_chip(idata);
2752 phb->ioda.irq_chip_init = 1;
2753 phb->ioda.irq_chip = *ichip;
2754 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2755 }
2756 irq_set_chip(virq, &phb->ioda.irq_chip);
2757 }
2758
2759 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2760 unsigned int hwirq, unsigned int virq,
2761 unsigned int is_64, struct msi_msg *msg)
2762 {
2763 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2764 unsigned int xive_num = hwirq - phb->msi_base;
2765 __be32 data;
2766 int rc;
2767
2768 /* No PE assigned ? bail out ... no MSI for you ! */
2769 if (pe == NULL)
2770 return -ENXIO;
2771
2772 /* Check if we have an MVE */
2773 if (pe->mve_number < 0)
2774 return -ENXIO;
2775
2776 /* Force 32-bit MSI on some broken devices */
2777 if (dev->no_64bit_msi)
2778 is_64 = 0;
2779
2780 /* Assign XIVE to PE */
2781 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2782 if (rc) {
2783 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2784 pci_name(dev), rc, xive_num);
2785 return -EIO;
2786 }
2787
2788 if (is_64) {
2789 __be64 addr64;
2790
2791 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2792 &addr64, &data);
2793 if (rc) {
2794 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2795 pci_name(dev), rc);
2796 return -EIO;
2797 }
2798 msg->address_hi = be64_to_cpu(addr64) >> 32;
2799 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2800 } else {
2801 __be32 addr32;
2802
2803 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2804 &addr32, &data);
2805 if (rc) {
2806 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2807 pci_name(dev), rc);
2808 return -EIO;
2809 }
2810 msg->address_hi = 0;
2811 msg->address_lo = be32_to_cpu(addr32);
2812 }
2813 msg->data = be32_to_cpu(data);
2814
2815 pnv_set_msi_irq_chip(phb, virq);
2816
2817 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2818 " address=%x_%08x data=%x PE# %d\n",
2819 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2820 msg->address_hi, msg->address_lo, data, pe->pe_number);
2821
2822 return 0;
2823 }
2824
2825 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2826 {
2827 unsigned int count;
2828 const __be32 *prop = of_get_property(phb->hose->dn,
2829 "ibm,opal-msi-ranges", NULL);
2830 if (!prop) {
2831 /* BML Fallback */
2832 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2833 }
2834 if (!prop)
2835 return;
2836
2837 phb->msi_base = be32_to_cpup(prop);
2838 count = be32_to_cpup(prop + 1);
2839 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2840 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2841 phb->hose->global_number);
2842 return;
2843 }
2844
2845 phb->msi_setup = pnv_pci_ioda_msi_setup;
2846 phb->msi32_support = 1;
2847 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2848 count, phb->msi_base);
2849 }
2850 #else
2851 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2852 #endif /* CONFIG_PCI_MSI */
2853
2854 #ifdef CONFIG_PCI_IOV
2855 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2856 {
2857 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2858 struct pnv_phb *phb = hose->private_data;
2859 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2860 struct resource *res;
2861 int i;
2862 resource_size_t size, total_vf_bar_sz;
2863 struct pci_dn *pdn;
2864 int mul, total_vfs;
2865
2866 if (!pdev->is_physfn || pdev->is_added)
2867 return;
2868
2869 pdn = pci_get_pdn(pdev);
2870 pdn->vfs_expanded = 0;
2871 pdn->m64_single_mode = false;
2872
2873 total_vfs = pci_sriov_get_totalvfs(pdev);
2874 mul = phb->ioda.total_pe_num;
2875 total_vf_bar_sz = 0;
2876
2877 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2878 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2879 if (!res->flags || res->parent)
2880 continue;
2881 if (!pnv_pci_is_m64_flags(res->flags)) {
2882 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2883 " non M64 VF BAR%d: %pR. \n",
2884 i, res);
2885 goto truncate_iov;
2886 }
2887
2888 total_vf_bar_sz += pci_iov_resource_size(pdev,
2889 i + PCI_IOV_RESOURCES);
2890
2891 /*
2892 * If bigger than quarter of M64 segment size, just round up
2893 * power of two.
2894 *
2895 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2896 * with other devices, IOV BAR size is expanded to be
2897 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2898 * segment size , the expanded size would equal to half of the
2899 * whole M64 space size, which will exhaust the M64 Space and
2900 * limit the system flexibility. This is a design decision to
2901 * set the boundary to quarter of the M64 segment size.
2902 */
2903 if (total_vf_bar_sz > gate) {
2904 mul = roundup_pow_of_two(total_vfs);
2905 dev_info(&pdev->dev,
2906 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2907 total_vf_bar_sz, gate, mul);
2908 pdn->m64_single_mode = true;
2909 break;
2910 }
2911 }
2912
2913 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2914 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2915 if (!res->flags || res->parent)
2916 continue;
2917
2918 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2919 /*
2920 * On PHB3, the minimum size alignment of M64 BAR in single
2921 * mode is 32MB.
2922 */
2923 if (pdn->m64_single_mode && (size < SZ_32M))
2924 goto truncate_iov;
2925 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2926 res->end = res->start + size * mul - 1;
2927 dev_dbg(&pdev->dev, " %pR\n", res);
2928 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2929 i, res, mul);
2930 }
2931 pdn->vfs_expanded = mul;
2932
2933 return;
2934
2935 truncate_iov:
2936 /* To save MMIO space, IOV BAR is truncated. */
2937 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2938 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2939 res->flags = 0;
2940 res->end = res->start - 1;
2941 }
2942 }
2943 #endif /* CONFIG_PCI_IOV */
2944
2945 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2946 struct resource *res)
2947 {
2948 struct pnv_phb *phb = pe->phb;
2949 struct pci_bus_region region;
2950 int index;
2951 int64_t rc;
2952
2953 if (!res || !res->flags || res->start > res->end)
2954 return;
2955
2956 if (res->flags & IORESOURCE_IO) {
2957 region.start = res->start - phb->ioda.io_pci_base;
2958 region.end = res->end - phb->ioda.io_pci_base;
2959 index = region.start / phb->ioda.io_segsize;
2960
2961 while (index < phb->ioda.total_pe_num &&
2962 region.start <= region.end) {
2963 phb->ioda.io_segmap[index] = pe->pe_number;
2964 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2965 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2966 if (rc != OPAL_SUCCESS) {
2967 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
2968 __func__, rc, index, pe->pe_number);
2969 break;
2970 }
2971
2972 region.start += phb->ioda.io_segsize;
2973 index++;
2974 }
2975 } else if ((res->flags & IORESOURCE_MEM) &&
2976 !pnv_pci_is_m64(phb, res)) {
2977 region.start = res->start -
2978 phb->hose->mem_offset[0] -
2979 phb->ioda.m32_pci_base;
2980 region.end = res->end -
2981 phb->hose->mem_offset[0] -
2982 phb->ioda.m32_pci_base;
2983 index = region.start / phb->ioda.m32_segsize;
2984
2985 while (index < phb->ioda.total_pe_num &&
2986 region.start <= region.end) {
2987 phb->ioda.m32_segmap[index] = pe->pe_number;
2988 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2989 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2990 if (rc != OPAL_SUCCESS) {
2991 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
2992 __func__, rc, index, pe->pe_number);
2993 break;
2994 }
2995
2996 region.start += phb->ioda.m32_segsize;
2997 index++;
2998 }
2999 }
3000 }
3001
3002 /*
3003 * This function is supposed to be called on basis of PE from top
3004 * to bottom style. So the the I/O or MMIO segment assigned to
3005 * parent PE could be overrided by its child PEs if necessary.
3006 */
3007 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3008 {
3009 struct pci_dev *pdev;
3010 int i;
3011
3012 /*
3013 * NOTE: We only care PCI bus based PE for now. For PCI
3014 * device based PE, for example SRIOV sensitive VF should
3015 * be figured out later.
3016 */
3017 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3018
3019 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3020 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3021 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3022
3023 /*
3024 * If the PE contains all subordinate PCI buses, the
3025 * windows of the child bridges should be mapped to
3026 * the PE as well.
3027 */
3028 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3029 continue;
3030 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3031 pnv_ioda_setup_pe_res(pe,
3032 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3033 }
3034 }
3035
3036 static void pnv_pci_ioda_create_dbgfs(void)
3037 {
3038 #ifdef CONFIG_DEBUG_FS
3039 struct pci_controller *hose, *tmp;
3040 struct pnv_phb *phb;
3041 char name[16];
3042
3043 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3044 phb = hose->private_data;
3045
3046 /* Notify initialization of PHB done */
3047 phb->initialized = 1;
3048
3049 sprintf(name, "PCI%04x", hose->global_number);
3050 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3051 if (!phb->dbgfs)
3052 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3053 __func__, hose->global_number);
3054 }
3055 #endif /* CONFIG_DEBUG_FS */
3056 }
3057
3058 static void pnv_pci_ioda_fixup(void)
3059 {
3060 pnv_pci_ioda_setup_PEs();
3061 pnv_pci_ioda_setup_iommu_api();
3062 pnv_pci_ioda_create_dbgfs();
3063
3064 #ifdef CONFIG_EEH
3065 eeh_init();
3066 eeh_addr_cache_build();
3067 #endif
3068 }
3069
3070 /*
3071 * Returns the alignment for I/O or memory windows for P2P
3072 * bridges. That actually depends on how PEs are segmented.
3073 * For now, we return I/O or M32 segment size for PE sensitive
3074 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3075 * 1MiB for memory) will be returned.
3076 *
3077 * The current PCI bus might be put into one PE, which was
3078 * create against the parent PCI bridge. For that case, we
3079 * needn't enlarge the alignment so that we can save some
3080 * resources.
3081 */
3082 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3083 unsigned long type)
3084 {
3085 struct pci_dev *bridge;
3086 struct pci_controller *hose = pci_bus_to_host(bus);
3087 struct pnv_phb *phb = hose->private_data;
3088 int num_pci_bridges = 0;
3089
3090 bridge = bus->self;
3091 while (bridge) {
3092 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3093 num_pci_bridges++;
3094 if (num_pci_bridges >= 2)
3095 return 1;
3096 }
3097
3098 bridge = bridge->bus->self;
3099 }
3100
3101 /*
3102 * We fall back to M32 if M64 isn't supported. We enforce the M64
3103 * alignment for any 64-bit resource, PCIe doesn't care and
3104 * bridges only do 64-bit prefetchable anyway.
3105 */
3106 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3107 return phb->ioda.m64_segsize;
3108 if (type & IORESOURCE_MEM)
3109 return phb->ioda.m32_segsize;
3110
3111 return phb->ioda.io_segsize;
3112 }
3113
3114 /*
3115 * We are updating root port or the upstream port of the
3116 * bridge behind the root port with PHB's windows in order
3117 * to accommodate the changes on required resources during
3118 * PCI (slot) hotplug, which is connected to either root
3119 * port or the downstream ports of PCIe switch behind the
3120 * root port.
3121 */
3122 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3123 unsigned long type)
3124 {
3125 struct pci_controller *hose = pci_bus_to_host(bus);
3126 struct pnv_phb *phb = hose->private_data;
3127 struct pci_dev *bridge = bus->self;
3128 struct resource *r, *w;
3129 bool msi_region = false;
3130 int i;
3131
3132 /* Check if we need apply fixup to the bridge's windows */
3133 if (!pci_is_root_bus(bridge->bus) &&
3134 !pci_is_root_bus(bridge->bus->self->bus))
3135 return;
3136
3137 /* Fixup the resources */
3138 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3139 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3140 if (!r->flags || !r->parent)
3141 continue;
3142
3143 w = NULL;
3144 if (r->flags & type & IORESOURCE_IO)
3145 w = &hose->io_resource;
3146 else if (pnv_pci_is_m64(phb, r) &&
3147 (type & IORESOURCE_PREFETCH) &&
3148 phb->ioda.m64_segsize)
3149 w = &hose->mem_resources[1];
3150 else if (r->flags & type & IORESOURCE_MEM) {
3151 w = &hose->mem_resources[0];
3152 msi_region = true;
3153 }
3154
3155 r->start = w->start;
3156 r->end = w->end;
3157
3158 /* The 64KB 32-bits MSI region shouldn't be included in
3159 * the 32-bits bridge window. Otherwise, we can see strange
3160 * issues. One of them is EEH error observed on Garrison.
3161 *
3162 * Exclude top 1MB region which is the minimal alignment of
3163 * 32-bits bridge window.
3164 */
3165 if (msi_region) {
3166 r->end += 0x10000;
3167 r->end -= 0x100000;
3168 }
3169 }
3170 }
3171
3172 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3173 {
3174 struct pci_controller *hose = pci_bus_to_host(bus);
3175 struct pnv_phb *phb = hose->private_data;
3176 struct pci_dev *bridge = bus->self;
3177 struct pnv_ioda_pe *pe;
3178 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3179
3180 /* Extend bridge's windows if necessary */
3181 pnv_pci_fixup_bridge_resources(bus, type);
3182
3183 /* The PE for root bus should be realized before any one else */
3184 if (!phb->ioda.root_pe_populated) {
3185 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3186 if (pe) {
3187 phb->ioda.root_pe_idx = pe->pe_number;
3188 phb->ioda.root_pe_populated = true;
3189 }
3190 }
3191
3192 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3193 if (list_empty(&bus->devices))
3194 return;
3195
3196 /* Reserve PEs according to used M64 resources */
3197 if (phb->reserve_m64_pe)
3198 phb->reserve_m64_pe(bus, NULL, all);
3199
3200 /*
3201 * Assign PE. We might run here because of partial hotplug.
3202 * For the case, we just pick up the existing PE and should
3203 * not allocate resources again.
3204 */
3205 pe = pnv_ioda_setup_bus_PE(bus, all);
3206 if (!pe)
3207 return;
3208
3209 pnv_ioda_setup_pe_seg(pe);
3210 switch (phb->type) {
3211 case PNV_PHB_IODA1:
3212 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3213 break;
3214 case PNV_PHB_IODA2:
3215 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3216 break;
3217 default:
3218 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3219 __func__, phb->hose->global_number, phb->type);
3220 }
3221 }
3222
3223 #ifdef CONFIG_PCI_IOV
3224 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3225 int resno)
3226 {
3227 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3228 struct pnv_phb *phb = hose->private_data;
3229 struct pci_dn *pdn = pci_get_pdn(pdev);
3230 resource_size_t align;
3231
3232 /*
3233 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3234 * SR-IOV. While from hardware perspective, the range mapped by M64
3235 * BAR should be size aligned.
3236 *
3237 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3238 * powernv-specific hardware restriction is gone. But if just use the
3239 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3240 * in one segment of M64 #15, which introduces the PE conflict between
3241 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3242 * m64_segsize.
3243 *
3244 * This function returns the total IOV BAR size if M64 BAR is in
3245 * Shared PE mode or just VF BAR size if not.
3246 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3247 * M64 segment size if IOV BAR size is less.
3248 */
3249 align = pci_iov_resource_size(pdev, resno);
3250 if (!pdn->vfs_expanded)
3251 return align;
3252 if (pdn->m64_single_mode)
3253 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3254
3255 return pdn->vfs_expanded * align;
3256 }
3257 #endif /* CONFIG_PCI_IOV */
3258
3259 /* Prevent enabling devices for which we couldn't properly
3260 * assign a PE
3261 */
3262 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3263 {
3264 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3265 struct pnv_phb *phb = hose->private_data;
3266 struct pci_dn *pdn;
3267
3268 /* The function is probably called while the PEs have
3269 * not be created yet. For example, resource reassignment
3270 * during PCI probe period. We just skip the check if
3271 * PEs isn't ready.
3272 */
3273 if (!phb->initialized)
3274 return true;
3275
3276 pdn = pci_get_pdn(dev);
3277 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3278 return false;
3279
3280 return true;
3281 }
3282
3283 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3284 int num)
3285 {
3286 struct pnv_ioda_pe *pe = container_of(table_group,
3287 struct pnv_ioda_pe, table_group);
3288 struct pnv_phb *phb = pe->phb;
3289 unsigned int idx;
3290 long rc;
3291
3292 pe_info(pe, "Removing DMA window #%d\n", num);
3293 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3294 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3295 continue;
3296
3297 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3298 idx, 0, 0ul, 0ul, 0ul);
3299 if (rc != OPAL_SUCCESS) {
3300 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3301 rc, idx);
3302 return rc;
3303 }
3304
3305 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3306 }
3307
3308 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3309 return OPAL_SUCCESS;
3310 }
3311
3312 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3313 {
3314 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3315 struct iommu_table *tbl = pe->table_group.tables[0];
3316 int64_t rc;
3317
3318 if (!weight)
3319 return;
3320
3321 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3322 if (rc != OPAL_SUCCESS)
3323 return;
3324
3325 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3326 if (pe->table_group.group) {
3327 iommu_group_put(pe->table_group.group);
3328 WARN_ON(pe->table_group.group);
3329 }
3330
3331 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3332 iommu_free_table(tbl, "pnv");
3333 }
3334
3335 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3336 {
3337 struct iommu_table *tbl = pe->table_group.tables[0];
3338 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3339 #ifdef CONFIG_IOMMU_API
3340 int64_t rc;
3341 #endif
3342
3343 if (!weight)
3344 return;
3345
3346 #ifdef CONFIG_IOMMU_API
3347 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3348 if (rc)
3349 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3350 #endif
3351
3352 pnv_pci_ioda2_set_bypass(pe, false);
3353 if (pe->table_group.group) {
3354 iommu_group_put(pe->table_group.group);
3355 WARN_ON(pe->table_group.group);
3356 }
3357
3358 pnv_pci_ioda2_table_free_pages(tbl);
3359 iommu_free_table(tbl, "pnv");
3360 }
3361
3362 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3363 unsigned short win,
3364 unsigned int *map)
3365 {
3366 struct pnv_phb *phb = pe->phb;
3367 int idx;
3368 int64_t rc;
3369
3370 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3371 if (map[idx] != pe->pe_number)
3372 continue;
3373
3374 if (win == OPAL_M64_WINDOW_TYPE)
3375 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3376 phb->ioda.reserved_pe_idx, win,
3377 idx / PNV_IODA1_M64_SEGS,
3378 idx % PNV_IODA1_M64_SEGS);
3379 else
3380 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3381 phb->ioda.reserved_pe_idx, win, 0, idx);
3382
3383 if (rc != OPAL_SUCCESS)
3384 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3385 rc, win, idx);
3386
3387 map[idx] = IODA_INVALID_PE;
3388 }
3389 }
3390
3391 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3392 {
3393 struct pnv_phb *phb = pe->phb;
3394
3395 if (phb->type == PNV_PHB_IODA1) {
3396 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3397 phb->ioda.io_segmap);
3398 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3399 phb->ioda.m32_segmap);
3400 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3401 phb->ioda.m64_segmap);
3402 } else if (phb->type == PNV_PHB_IODA2) {
3403 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3404 phb->ioda.m32_segmap);
3405 }
3406 }
3407
3408 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3409 {
3410 struct pnv_phb *phb = pe->phb;
3411 struct pnv_ioda_pe *slave, *tmp;
3412
3413 list_del(&pe->list);
3414 switch (phb->type) {
3415 case PNV_PHB_IODA1:
3416 pnv_pci_ioda1_release_pe_dma(pe);
3417 break;
3418 case PNV_PHB_IODA2:
3419 pnv_pci_ioda2_release_pe_dma(pe);
3420 break;
3421 default:
3422 WARN_ON(1);
3423 }
3424
3425 pnv_ioda_release_pe_seg(pe);
3426 pnv_ioda_deconfigure_pe(pe->phb, pe);
3427
3428 /* Release slave PEs in the compound PE */
3429 if (pe->flags & PNV_IODA_PE_MASTER) {
3430 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3431 list_del(&slave->list);
3432 pnv_ioda_free_pe(slave);
3433 }
3434 }
3435
3436 /*
3437 * The PE for root bus can be removed because of hotplug in EEH
3438 * recovery for fenced PHB error. We need to mark the PE dead so
3439 * that it can be populated again in PCI hot add path. The PE
3440 * shouldn't be destroyed as it's the global reserved resource.
3441 */
3442 if (phb->ioda.root_pe_populated &&
3443 phb->ioda.root_pe_idx == pe->pe_number)
3444 phb->ioda.root_pe_populated = false;
3445 else
3446 pnv_ioda_free_pe(pe);
3447 }
3448
3449 static void pnv_pci_release_device(struct pci_dev *pdev)
3450 {
3451 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3452 struct pnv_phb *phb = hose->private_data;
3453 struct pci_dn *pdn = pci_get_pdn(pdev);
3454 struct pnv_ioda_pe *pe;
3455
3456 if (pdev->is_virtfn)
3457 return;
3458
3459 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3460 return;
3461
3462 /*
3463 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3464 * isn't removed and added afterwards in this scenario. We should
3465 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3466 * device count is decreased on removing devices while failing to
3467 * be increased on adding devices. It leads to unbalanced PE's device
3468 * count and eventually make normal PCI hotplug path broken.
3469 */
3470 pe = &phb->ioda.pe_array[pdn->pe_number];
3471 pdn->pe_number = IODA_INVALID_PE;
3472
3473 WARN_ON(--pe->device_count < 0);
3474 if (pe->device_count == 0)
3475 pnv_ioda_release_pe(pe);
3476 }
3477
3478 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3479 {
3480 struct pnv_phb *phb = hose->private_data;
3481
3482 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3483 OPAL_ASSERT_RESET);
3484 }
3485
3486 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3487 .dma_dev_setup = pnv_pci_dma_dev_setup,
3488 .dma_bus_setup = pnv_pci_dma_bus_setup,
3489 #ifdef CONFIG_PCI_MSI
3490 .setup_msi_irqs = pnv_setup_msi_irqs,
3491 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3492 #endif
3493 .enable_device_hook = pnv_pci_enable_device_hook,
3494 .release_device = pnv_pci_release_device,
3495 .window_alignment = pnv_pci_window_alignment,
3496 .setup_bridge = pnv_pci_setup_bridge,
3497 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3498 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3499 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3500 .shutdown = pnv_pci_ioda_shutdown,
3501 };
3502
3503 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3504 {
3505 dev_err_once(&npdev->dev,
3506 "%s operation unsupported for NVLink devices\n",
3507 __func__);
3508 return -EPERM;
3509 }
3510
3511 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3512 .dma_dev_setup = pnv_pci_dma_dev_setup,
3513 #ifdef CONFIG_PCI_MSI
3514 .setup_msi_irqs = pnv_setup_msi_irqs,
3515 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3516 #endif
3517 .enable_device_hook = pnv_pci_enable_device_hook,
3518 .window_alignment = pnv_pci_window_alignment,
3519 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3520 .dma_set_mask = pnv_npu_dma_set_mask,
3521 .shutdown = pnv_pci_ioda_shutdown,
3522 };
3523
3524 #ifdef CONFIG_CXL_BASE
3525 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3526 .dma_dev_setup = pnv_pci_dma_dev_setup,
3527 .dma_bus_setup = pnv_pci_dma_bus_setup,
3528 #ifdef CONFIG_PCI_MSI
3529 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
3530 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
3531 #endif
3532 .enable_device_hook = pnv_cxl_enable_device_hook,
3533 .disable_device = pnv_cxl_disable_device,
3534 .release_device = pnv_pci_release_device,
3535 .window_alignment = pnv_pci_window_alignment,
3536 .setup_bridge = pnv_pci_setup_bridge,
3537 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3538 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3539 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3540 .shutdown = pnv_pci_ioda_shutdown,
3541 };
3542 #endif
3543
3544 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3545 u64 hub_id, int ioda_type)
3546 {
3547 struct pci_controller *hose;
3548 struct pnv_phb *phb;
3549 unsigned long size, m64map_off, m32map_off, pemap_off;
3550 unsigned long iomap_off = 0, dma32map_off = 0;
3551 struct resource r;
3552 const __be64 *prop64;
3553 const __be32 *prop32;
3554 int len;
3555 unsigned int segno;
3556 u64 phb_id;
3557 void *aux;
3558 long rc;
3559
3560 if (!of_device_is_available(np))
3561 return;
3562
3563 pr_info("Initializing %s PHB (%s)\n",
3564 pnv_phb_names[ioda_type], of_node_full_name(np));
3565
3566 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3567 if (!prop64) {
3568 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3569 return;
3570 }
3571 phb_id = be64_to_cpup(prop64);
3572 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3573
3574 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3575
3576 /* Allocate PCI controller */
3577 phb->hose = hose = pcibios_alloc_controller(np);
3578 if (!phb->hose) {
3579 pr_err(" Can't allocate PCI controller for %s\n",
3580 np->full_name);
3581 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3582 return;
3583 }
3584
3585 spin_lock_init(&phb->lock);
3586 prop32 = of_get_property(np, "bus-range", &len);
3587 if (prop32 && len == 8) {
3588 hose->first_busno = be32_to_cpu(prop32[0]);
3589 hose->last_busno = be32_to_cpu(prop32[1]);
3590 } else {
3591 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3592 hose->first_busno = 0;
3593 hose->last_busno = 0xff;
3594 }
3595 hose->private_data = phb;
3596 phb->hub_id = hub_id;
3597 phb->opal_id = phb_id;
3598 phb->type = ioda_type;
3599 mutex_init(&phb->ioda.pe_alloc_mutex);
3600
3601 /* Detect specific models for error handling */
3602 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3603 phb->model = PNV_PHB_MODEL_P7IOC;
3604 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3605 phb->model = PNV_PHB_MODEL_PHB3;
3606 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3607 phb->model = PNV_PHB_MODEL_NPU;
3608 else
3609 phb->model = PNV_PHB_MODEL_UNKNOWN;
3610
3611 /* Parse 32-bit and IO ranges (if any) */
3612 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3613
3614 /* Get registers */
3615 if (!of_address_to_resource(np, 0, &r)) {
3616 phb->regs_phys = r.start;
3617 phb->regs = ioremap(r.start, resource_size(&r));
3618 if (phb->regs == NULL)
3619 pr_err(" Failed to map registers !\n");
3620 }
3621
3622 /* Initialize more IODA stuff */
3623 phb->ioda.total_pe_num = 1;
3624 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3625 if (prop32)
3626 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3627 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3628 if (prop32)
3629 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3630
3631 /* Invalidate RID to PE# mapping */
3632 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3633 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3634
3635 /* Parse 64-bit MMIO range */
3636 pnv_ioda_parse_m64_window(phb);
3637
3638 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3639 /* FW Has already off top 64k of M32 space (MSI space) */
3640 phb->ioda.m32_size += 0x10000;
3641
3642 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3643 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3644 phb->ioda.io_size = hose->pci_io_size;
3645 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3646 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3647
3648 /* Calculate how many 32-bit TCE segments we have */
3649 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3650 PNV_IODA1_DMA32_SEGSIZE;
3651
3652 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3653 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3654 sizeof(unsigned long));
3655 m64map_off = size;
3656 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3657 m32map_off = size;
3658 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3659 if (phb->type == PNV_PHB_IODA1) {
3660 iomap_off = size;
3661 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3662 dma32map_off = size;
3663 size += phb->ioda.dma32_count *
3664 sizeof(phb->ioda.dma32_segmap[0]);
3665 }
3666 pemap_off = size;
3667 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3668 aux = memblock_virt_alloc(size, 0);
3669 phb->ioda.pe_alloc = aux;
3670 phb->ioda.m64_segmap = aux + m64map_off;
3671 phb->ioda.m32_segmap = aux + m32map_off;
3672 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3673 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3674 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3675 }
3676 if (phb->type == PNV_PHB_IODA1) {
3677 phb->ioda.io_segmap = aux + iomap_off;
3678 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3679 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3680
3681 phb->ioda.dma32_segmap = aux + dma32map_off;
3682 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3683 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3684 }
3685 phb->ioda.pe_array = aux + pemap_off;
3686
3687 /*
3688 * Choose PE number for root bus, which shouldn't have
3689 * M64 resources consumed by its child devices. To pick
3690 * the PE number adjacent to the reserved one if possible.
3691 */
3692 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3693 if (phb->ioda.reserved_pe_idx == 0) {
3694 phb->ioda.root_pe_idx = 1;
3695 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3696 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3697 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3698 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3699 } else {
3700 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3701 }
3702
3703 INIT_LIST_HEAD(&phb->ioda.pe_list);
3704 mutex_init(&phb->ioda.pe_list_mutex);
3705
3706 /* Calculate how many 32-bit TCE segments we have */
3707 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3708 PNV_IODA1_DMA32_SEGSIZE;
3709
3710 #if 0 /* We should really do that ... */
3711 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3712 window_type,
3713 window_num,
3714 starting_real_address,
3715 starting_pci_address,
3716 segment_size);
3717 #endif
3718
3719 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3720 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3721 phb->ioda.m32_size, phb->ioda.m32_segsize);
3722 if (phb->ioda.m64_size)
3723 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3724 phb->ioda.m64_size, phb->ioda.m64_segsize);
3725 if (phb->ioda.io_size)
3726 pr_info(" IO: 0x%x [segment=0x%x]\n",
3727 phb->ioda.io_size, phb->ioda.io_segsize);
3728
3729
3730 phb->hose->ops = &pnv_pci_ops;
3731 phb->get_pe_state = pnv_ioda_get_pe_state;
3732 phb->freeze_pe = pnv_ioda_freeze_pe;
3733 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3734
3735 /* Setup MSI support */
3736 pnv_pci_init_ioda_msis(phb);
3737
3738 /*
3739 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3740 * to let the PCI core do resource assignment. It's supposed
3741 * that the PCI core will do correct I/O and MMIO alignment
3742 * for the P2P bridge bars so that each PCI bus (excluding
3743 * the child P2P bridges) can form individual PE.
3744 */
3745 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3746
3747 if (phb->type == PNV_PHB_NPU) {
3748 hose->controller_ops = pnv_npu_ioda_controller_ops;
3749 } else {
3750 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3751 hose->controller_ops = pnv_pci_ioda_controller_ops;
3752 }
3753
3754 #ifdef CONFIG_PCI_IOV
3755 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3756 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3757 #endif
3758
3759 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3760
3761 /* Reset IODA tables to a clean state */
3762 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3763 if (rc)
3764 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
3765
3766 /* If we're running in kdump kerenl, the previous kerenl never
3767 * shutdown PCI devices correctly. We already got IODA table
3768 * cleaned out. So we have to issue PHB reset to stop all PCI
3769 * transactions from previous kerenl.
3770 */
3771 if (is_kdump_kernel()) {
3772 pr_info(" Issue PHB reset ...\n");
3773 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3774 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3775 }
3776
3777 /* Remove M64 resource if we can't configure it successfully */
3778 if (!phb->init_m64 || phb->init_m64(phb))
3779 hose->mem_resources[1].flags = 0;
3780 }
3781
3782 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3783 {
3784 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3785 }
3786
3787 void __init pnv_pci_init_npu_phb(struct device_node *np)
3788 {
3789 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3790 }
3791
3792 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3793 {
3794 struct device_node *phbn;
3795 const __be64 *prop64;
3796 u64 hub_id;
3797
3798 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3799
3800 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3801 if (!prop64) {
3802 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3803 return;
3804 }
3805 hub_id = be64_to_cpup(prop64);
3806 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3807
3808 /* Count child PHBs */
3809 for_each_child_of_node(np, phbn) {
3810 /* Look for IODA1 PHBs */
3811 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3812 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3813 }
3814 }
3815
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