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Linux/arch/powerpc/platforms/powernv/pci-p5ioc2.c

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  1 /*
  2  * Support PCI/PCIe on PowerNV platforms
  3  *
  4  * Currently supports only P5IOC2
  5  *
  6  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * as published by the Free Software Foundation; either version
 11  * 2 of the License, or (at your option) any later version.
 12  */
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/pci.h>
 16 #include <linux/delay.h>
 17 #include <linux/string.h>
 18 #include <linux/init.h>
 19 #include <linux/bootmem.h>
 20 #include <linux/irq.h>
 21 #include <linux/io.h>
 22 #include <linux/msi.h>
 23 
 24 #include <asm/sections.h>
 25 #include <asm/io.h>
 26 #include <asm/prom.h>
 27 #include <asm/pci-bridge.h>
 28 #include <asm/machdep.h>
 29 #include <asm/msi_bitmap.h>
 30 #include <asm/ppc-pci.h>
 31 #include <asm/opal.h>
 32 #include <asm/iommu.h>
 33 #include <asm/tce.h>
 34 
 35 #include "powernv.h"
 36 #include "pci.h"
 37 
 38 /* For now, use a fixed amount of TCE memory for each p5ioc2
 39  * hub, 16M will do
 40  */
 41 #define P5IOC2_TCE_MEMORY       0x01000000
 42 
 43 #ifdef CONFIG_PCI_MSI
 44 static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 45                                     unsigned int hwirq, unsigned int virq,
 46                                     unsigned int is_64, struct msi_msg *msg)
 47 {
 48         if (WARN_ON(!is_64))
 49                 return -ENXIO;
 50         msg->data = hwirq - phb->msi_base;
 51         msg->address_hi = 0x10000000;
 52         msg->address_lo = 0;
 53 
 54         return 0;
 55 }
 56 
 57 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
 58 {
 59         unsigned int count;
 60         const __be32 *prop = of_get_property(phb->hose->dn,
 61                                              "ibm,opal-msi-ranges", NULL);
 62         if (!prop)
 63                 return;
 64 
 65         /* Don't do MSI's on p5ioc2 PCI-X are they are not properly
 66          * verified in HW
 67          */
 68         if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
 69                 return;
 70         phb->msi_base = be32_to_cpup(prop);
 71         count = be32_to_cpup(prop + 1);
 72         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
 73                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
 74                        phb->hose->global_number);
 75                 return;
 76         }
 77         phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
 78         phb->msi32_support = 0;
 79         pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
 80                 count, phb->msi_base);
 81 }
 82 #else
 83 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
 84 #endif /* CONFIG_PCI_MSI */
 85 
 86 static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
 87                                          struct pci_dev *pdev)
 88 {
 89         if (phb->p5ioc2.iommu_table.it_map == NULL) {
 90                 iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node);
 91                 iommu_register_group(&phb->p5ioc2.iommu_table,
 92                                 pci_domain_nr(phb->hose->bus), phb->opal_id);
 93         }
 94 
 95         set_iommu_table_base_and_group(&pdev->dev, &phb->p5ioc2.iommu_table);
 96 }
 97 
 98 static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
 99                                            void *tce_mem, u64 tce_size)
100 {
101         struct pnv_phb *phb;
102         const __be64 *prop64;
103         u64 phb_id;
104         int64_t rc;
105         static int primary = 1;
106 
107         pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
108 
109         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
110         if (!prop64) {
111                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
112                 return;
113         }
114         phb_id = be64_to_cpup(prop64);
115         pr_devel("  PHB-ID  : 0x%016llx\n", phb_id);
116         pr_devel("  TCE AT  : 0x%016lx\n", __pa(tce_mem));
117         pr_devel("  TCE SZ  : 0x%016llx\n", tce_size);
118 
119         rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size);
120         if (rc != OPAL_SUCCESS) {
121                 pr_err("  Failed to set TCE memory, OPAL error %lld\n", rc);
122                 return;
123         }
124 
125         phb = alloc_bootmem(sizeof(struct pnv_phb));
126         if (phb) {
127                 memset(phb, 0, sizeof(struct pnv_phb));
128                 phb->hose = pcibios_alloc_controller(np);
129         }
130         if (!phb || !phb->hose) {
131                 pr_err("  Failed to allocate PCI controller\n");
132                 return;
133         }
134 
135         spin_lock_init(&phb->lock);
136         phb->hose->first_busno = 0;
137         phb->hose->last_busno = 0xff;
138         phb->hose->private_data = phb;
139         phb->hub_id = hub_id;
140         phb->opal_id = phb_id;
141         phb->type = PNV_PHB_P5IOC2;
142         phb->model = PNV_PHB_MODEL_P5IOC2;
143 
144         phb->regs = of_iomap(np, 0);
145 
146         if (phb->regs == NULL)
147                 pr_err("  Failed to map registers !\n");
148         else {
149                 pr_devel("  P_BUID     = 0x%08x\n", in_be32(phb->regs + 0x100));
150                 pr_devel("  P_IOSZ     = 0x%08x\n", in_be32(phb->regs + 0x1b0));
151                 pr_devel("  P_IO_ST    = 0x%08x\n", in_be32(phb->regs + 0x1e0));
152                 pr_devel("  P_MEM1_H   = 0x%08x\n", in_be32(phb->regs + 0x1a0));
153                 pr_devel("  P_MEM1_L   = 0x%08x\n", in_be32(phb->regs + 0x190));
154                 pr_devel("  P_MSZ1_L   = 0x%08x\n", in_be32(phb->regs + 0x1c0));
155                 pr_devel("  P_MEM_ST   = 0x%08x\n", in_be32(phb->regs + 0x1d0));
156                 pr_devel("  P_MEM2_H   = 0x%08x\n", in_be32(phb->regs + 0x2c0));
157                 pr_devel("  P_MEM2_L   = 0x%08x\n", in_be32(phb->regs + 0x2b0));
158                 pr_devel("  P_MSZ2_H   = 0x%08x\n", in_be32(phb->regs + 0x2d0));
159                 pr_devel("  P_MSZ2_L   = 0x%08x\n", in_be32(phb->regs + 0x2e0));
160         }
161 
162         /* Interpret the "ranges" property */
163         /* This also maps the I/O region and sets isa_io/mem_base */
164         pci_process_bridge_OF_ranges(phb->hose, np, primary);
165         primary = 0;
166 
167         phb->hose->ops = &pnv_pci_ops;
168 
169         /* Setup MSI support */
170         pnv_pci_init_p5ioc2_msis(phb);
171 
172         /* Setup TCEs */
173         phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
174         pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
175                                   tce_mem, tce_size, 0);
176 }
177 
178 void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
179 {
180         struct device_node *phbn;
181         const __be64 *prop64;
182         u64 hub_id;
183         void *tce_mem;
184         uint64_t tce_per_phb;
185         int64_t rc;
186         int phb_count = 0;
187 
188         pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name);
189 
190         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
191         if (!prop64) {
192                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
193                 return;
194         }
195         hub_id = be64_to_cpup(prop64);
196         pr_info(" HUB-ID : 0x%016llx\n", hub_id);
197 
198         /* Currently allocate 16M of TCE memory for every Hub
199          *
200          * XXX TODO: Make it chip local if possible
201          */
202         tce_mem = __alloc_bootmem(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY,
203                                   __pa(MAX_DMA_ADDRESS));
204         if (!tce_mem) {
205                 pr_err(" Failed to allocate TCE Memory !\n");
206                 return;
207         }
208         pr_debug(" TCE    : 0x%016lx..0x%016lx\n",
209                 __pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1);
210         rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem),
211                                         P5IOC2_TCE_MEMORY);
212         if (rc != OPAL_SUCCESS) {
213                 pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc);
214                 return;
215         }
216 
217         /* Count child PHBs */
218         for_each_child_of_node(np, phbn) {
219                 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
220                     of_device_is_compatible(phbn, "ibm,p5ioc2-pciex"))
221                         phb_count++;
222         }
223 
224         /* Calculate how much TCE space we can give per PHB */
225         tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count);
226         pr_info(" Allocating %lld MB of TCE memory per PHB\n",
227                 tce_per_phb >> 20);
228 
229         /* Initialize PHBs */
230         for_each_child_of_node(np, phbn) {
231                 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
232                     of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
233                         pnv_pci_init_p5ioc2_phb(phbn, hub_id,
234                                         tce_mem, tce_per_phb);
235                         tce_mem += tce_per_phb;
236                 }
237         }
238 }
239 

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