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TOMOYO Linux Cross Reference
Linux/arch/powerpc/platforms/pseries/iommu.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  3  *
  4  * Rewrite, cleanup:
  5  *
  6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
  7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
  8  *
  9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
 10  *
 11  *
 12  * This program is free software; you can redistribute it and/or modify
 13  * it under the terms of the GNU General Public License as published by
 14  * the Free Software Foundation; either version 2 of the License, or
 15  * (at your option) any later version.
 16  *
 17  * This program is distributed in the hope that it will be useful,
 18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  * GNU General Public License for more details.
 21  *
 22  * You should have received a copy of the GNU General Public License
 23  * along with this program; if not, write to the Free Software
 24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 25  */
 26 
 27 #include <linux/init.h>
 28 #include <linux/types.h>
 29 #include <linux/slab.h>
 30 #include <linux/mm.h>
 31 #include <linux/memblock.h>
 32 #include <linux/spinlock.h>
 33 #include <linux/sched.h>        /* for show_stack */
 34 #include <linux/string.h>
 35 #include <linux/pci.h>
 36 #include <linux/dma-mapping.h>
 37 #include <linux/crash_dump.h>
 38 #include <linux/memory.h>
 39 #include <linux/of.h>
 40 #include <asm/io.h>
 41 #include <asm/prom.h>
 42 #include <asm/rtas.h>
 43 #include <asm/iommu.h>
 44 #include <asm/pci-bridge.h>
 45 #include <asm/machdep.h>
 46 #include <asm/firmware.h>
 47 #include <asm/tce.h>
 48 #include <asm/ppc-pci.h>
 49 #include <asm/udbg.h>
 50 #include <asm/mmzone.h>
 51 
 52 #include "plpar_wrappers.h"
 53 
 54 
 55 static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
 56                                       u64 *startp, u64 *endp)
 57 {
 58         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 59         unsigned long start, end, inc;
 60 
 61         start = __pa(startp);
 62         end = __pa(endp);
 63         inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
 64 
 65         /* If this is non-zero, change the format.  We shift the
 66          * address and or in the magic from the device tree. */
 67         if (tbl->it_busno) {
 68                 start <<= 12;
 69                 end <<= 12;
 70                 inc <<= 12;
 71                 start |= tbl->it_busno;
 72                 end |= tbl->it_busno;
 73         }
 74 
 75         end |= inc - 1; /* round up end to be different than start */
 76 
 77         mb(); /* Make sure TCEs in memory are written */
 78         while (start <= end) {
 79                 out_be64(invalidate, start);
 80                 start += inc;
 81         }
 82 }
 83 
 84 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 85                               long npages, unsigned long uaddr,
 86                               enum dma_data_direction direction,
 87                               struct dma_attrs *attrs)
 88 {
 89         u64 proto_tce;
 90         u64 *tcep, *tces;
 91         u64 rpn;
 92 
 93         proto_tce = TCE_PCI_READ; // Read allowed
 94 
 95         if (direction != DMA_TO_DEVICE)
 96                 proto_tce |= TCE_PCI_WRITE;
 97 
 98         tces = tcep = ((u64 *)tbl->it_base) + index;
 99 
100         while (npages--) {
101                 /* can't move this out since we might cross MEMBLOCK boundary */
102                 rpn = __pa(uaddr) >> TCE_SHIFT;
103                 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
104 
105                 uaddr += TCE_PAGE_SIZE;
106                 tcep++;
107         }
108 
109         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
110                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
111         return 0;
112 }
113 
114 
115 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
116 {
117         u64 *tcep, *tces;
118 
119         tces = tcep = ((u64 *)tbl->it_base) + index;
120 
121         while (npages--)
122                 *(tcep++) = 0;
123 
124         if (tbl->it_type & TCE_PCI_SWINV_FREE)
125                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
126 }
127 
128 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
129 {
130         u64 *tcep;
131 
132         tcep = ((u64 *)tbl->it_base) + index;
133 
134         return *tcep;
135 }
136 
137 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
138 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
139 
140 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
141                                 long npages, unsigned long uaddr,
142                                 enum dma_data_direction direction,
143                                 struct dma_attrs *attrs)
144 {
145         u64 rc = 0;
146         u64 proto_tce, tce;
147         u64 rpn;
148         int ret = 0;
149         long tcenum_start = tcenum, npages_start = npages;
150 
151         rpn = __pa(uaddr) >> TCE_SHIFT;
152         proto_tce = TCE_PCI_READ;
153         if (direction != DMA_TO_DEVICE)
154                 proto_tce |= TCE_PCI_WRITE;
155 
156         while (npages--) {
157                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
158                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
159 
160                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
161                         ret = (int)rc;
162                         tce_free_pSeriesLP(tbl, tcenum_start,
163                                            (npages_start - (npages + 1)));
164                         break;
165                 }
166 
167                 if (rc && printk_ratelimit()) {
168                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
169                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
170                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
171                         printk("\ttce val = 0x%llx\n", tce );
172                         show_stack(current, (unsigned long *)__get_SP());
173                 }
174 
175                 tcenum++;
176                 rpn++;
177         }
178         return ret;
179 }
180 
181 static DEFINE_PER_CPU(u64 *, tce_page);
182 
183 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
184                                      long npages, unsigned long uaddr,
185                                      enum dma_data_direction direction,
186                                      struct dma_attrs *attrs)
187 {
188         u64 rc = 0;
189         u64 proto_tce;
190         u64 *tcep;
191         u64 rpn;
192         long l, limit;
193         long tcenum_start = tcenum, npages_start = npages;
194         int ret = 0;
195         unsigned long flags;
196 
197         if (npages == 1) {
198                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
199                                            direction, attrs);
200         }
201 
202         local_irq_save(flags);  /* to protect tcep and the page behind it */
203 
204         tcep = __get_cpu_var(tce_page);
205 
206         /* This is safe to do since interrupts are off when we're called
207          * from iommu_alloc{,_sg}()
208          */
209         if (!tcep) {
210                 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
211                 /* If allocation fails, fall back to the loop implementation */
212                 if (!tcep) {
213                         local_irq_restore(flags);
214                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
215                                             direction, attrs);
216                 }
217                 __get_cpu_var(tce_page) = tcep;
218         }
219 
220         rpn = __pa(uaddr) >> TCE_SHIFT;
221         proto_tce = TCE_PCI_READ;
222         if (direction != DMA_TO_DEVICE)
223                 proto_tce |= TCE_PCI_WRITE;
224 
225         /* We can map max one pageful of TCEs at a time */
226         do {
227                 /*
228                  * Set up the page with TCE data, looping through and setting
229                  * the values.
230                  */
231                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
232 
233                 for (l = 0; l < limit; l++) {
234                         tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
235                         rpn++;
236                 }
237 
238                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
239                                             (u64)tcenum << 12,
240                                             (u64)__pa(tcep),
241                                             limit);
242 
243                 npages -= limit;
244                 tcenum += limit;
245         } while (npages > 0 && !rc);
246 
247         local_irq_restore(flags);
248 
249         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
250                 ret = (int)rc;
251                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
252                                         (npages_start - (npages + limit)));
253                 return ret;
254         }
255 
256         if (rc && printk_ratelimit()) {
257                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
258                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
259                 printk("\tnpages  = 0x%llx\n", (u64)npages);
260                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
261                 show_stack(current, (unsigned long *)__get_SP());
262         }
263         return ret;
264 }
265 
266 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
267 {
268         u64 rc;
269 
270         while (npages--) {
271                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
272 
273                 if (rc && printk_ratelimit()) {
274                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
275                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
276                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
277                         show_stack(current, (unsigned long *)__get_SP());
278                 }
279 
280                 tcenum++;
281         }
282 }
283 
284 
285 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
286 {
287         u64 rc;
288 
289         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
290 
291         if (rc && printk_ratelimit()) {
292                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
293                 printk("\trc      = %lld\n", rc);
294                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
295                 printk("\tnpages  = 0x%llx\n", (u64)npages);
296                 show_stack(current, (unsigned long *)__get_SP());
297         }
298 }
299 
300 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
301 {
302         u64 rc;
303         unsigned long tce_ret;
304 
305         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
306 
307         if (rc && printk_ratelimit()) {
308                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
309                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
310                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
311                 show_stack(current, (unsigned long *)__get_SP());
312         }
313 
314         return tce_ret;
315 }
316 
317 /* this is compatible with cells for the device tree property */
318 struct dynamic_dma_window_prop {
319         __be32  liobn;          /* tce table number */
320         __be64  dma_base;       /* address hi,lo */
321         __be32  tce_shift;      /* ilog2(tce_page_size) */
322         __be32  window_shift;   /* ilog2(tce_window_size) */
323 };
324 
325 struct direct_window {
326         struct device_node *device;
327         const struct dynamic_dma_window_prop *prop;
328         struct list_head list;
329 };
330 
331 /* Dynamic DMA Window support */
332 struct ddw_query_response {
333         u32 windows_available;
334         u32 largest_available_block;
335         u32 page_size;
336         u32 migration_capable;
337 };
338 
339 struct ddw_create_response {
340         u32 liobn;
341         u32 addr_hi;
342         u32 addr_lo;
343 };
344 
345 static LIST_HEAD(direct_window_list);
346 /* prevents races between memory on/offline and window creation */
347 static DEFINE_SPINLOCK(direct_window_list_lock);
348 /* protects initializing window twice for same device */
349 static DEFINE_MUTEX(direct_window_init_mutex);
350 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
351 
352 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
353                                         unsigned long num_pfn, const void *arg)
354 {
355         const struct dynamic_dma_window_prop *maprange = arg;
356         int rc;
357         u64 tce_size, num_tce, dma_offset, next;
358         u32 tce_shift;
359         long limit;
360 
361         tce_shift = be32_to_cpu(maprange->tce_shift);
362         tce_size = 1ULL << tce_shift;
363         next = start_pfn << PAGE_SHIFT;
364         num_tce = num_pfn << PAGE_SHIFT;
365 
366         /* round back to the beginning of the tce page size */
367         num_tce += next & (tce_size - 1);
368         next &= ~(tce_size - 1);
369 
370         /* covert to number of tces */
371         num_tce |= tce_size - 1;
372         num_tce >>= tce_shift;
373 
374         do {
375                 /*
376                  * Set up the page with TCE data, looping through and setting
377                  * the values.
378                  */
379                 limit = min_t(long, num_tce, 512);
380                 dma_offset = next + be64_to_cpu(maprange->dma_base);
381 
382                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
383                                              dma_offset,
384                                              0, limit);
385                 next += limit * tce_size;
386                 num_tce -= limit;
387         } while (num_tce > 0 && !rc);
388 
389         return rc;
390 }
391 
392 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
393                                         unsigned long num_pfn, const void *arg)
394 {
395         const struct dynamic_dma_window_prop *maprange = arg;
396         u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
397         u32 tce_shift;
398         u64 rc = 0;
399         long l, limit;
400 
401         local_irq_disable();    /* to protect tcep and the page behind it */
402         tcep = __get_cpu_var(tce_page);
403 
404         if (!tcep) {
405                 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
406                 if (!tcep) {
407                         local_irq_enable();
408                         return -ENOMEM;
409                 }
410                 __get_cpu_var(tce_page) = tcep;
411         }
412 
413         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
414 
415         liobn = (u64)be32_to_cpu(maprange->liobn);
416         tce_shift = be32_to_cpu(maprange->tce_shift);
417         tce_size = 1ULL << tce_shift;
418         next = start_pfn << PAGE_SHIFT;
419         num_tce = num_pfn << PAGE_SHIFT;
420 
421         /* round back to the beginning of the tce page size */
422         num_tce += next & (tce_size - 1);
423         next &= ~(tce_size - 1);
424 
425         /* covert to number of tces */
426         num_tce |= tce_size - 1;
427         num_tce >>= tce_shift;
428 
429         /* We can map max one pageful of TCEs at a time */
430         do {
431                 /*
432                  * Set up the page with TCE data, looping through and setting
433                  * the values.
434                  */
435                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
436                 dma_offset = next + be64_to_cpu(maprange->dma_base);
437 
438                 for (l = 0; l < limit; l++) {
439                         tcep[l] = proto_tce | next;
440                         next += tce_size;
441                 }
442 
443                 rc = plpar_tce_put_indirect(liobn,
444                                             dma_offset,
445                                             (u64)__pa(tcep),
446                                             limit);
447 
448                 num_tce -= limit;
449         } while (num_tce > 0 && !rc);
450 
451         /* error cleanup: caller will clear whole range */
452 
453         local_irq_enable();
454         return rc;
455 }
456 
457 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
458                 unsigned long num_pfn, void *arg)
459 {
460         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
461 }
462 
463 
464 #ifdef CONFIG_PCI
465 static void iommu_table_setparms(struct pci_controller *phb,
466                                  struct device_node *dn,
467                                  struct iommu_table *tbl)
468 {
469         struct device_node *node;
470         const unsigned long *basep, *sw_inval;
471         const u32 *sizep;
472 
473         node = phb->dn;
474 
475         basep = of_get_property(node, "linux,tce-base", NULL);
476         sizep = of_get_property(node, "linux,tce-size", NULL);
477         if (basep == NULL || sizep == NULL) {
478                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
479                                 "missing tce entries !\n", dn->full_name);
480                 return;
481         }
482 
483         tbl->it_base = (unsigned long)__va(*basep);
484 
485         if (!is_kdump_kernel())
486                 memset((void *)tbl->it_base, 0, *sizep);
487 
488         tbl->it_busno = phb->bus->number;
489 
490         /* Units of tce entries */
491         tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
492 
493         /* Test if we are going over 2GB of DMA space */
494         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
495                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
496                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
497         }
498 
499         phb->dma_window_base_cur += phb->dma_window_size;
500 
501         /* Set the tce table size - measured in entries */
502         tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
503 
504         tbl->it_index = 0;
505         tbl->it_blocksize = 16;
506         tbl->it_type = TCE_PCI;
507 
508         sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
509         if (sw_inval) {
510                 /*
511                  * This property contains information on how to
512                  * invalidate the TCE entry.  The first property is
513                  * the base MMIO address used to invalidate entries.
514                  * The second property tells us the format of the TCE
515                  * invalidate (whether it needs to be shifted) and
516                  * some magic routing info to add to our invalidate
517                  * command.
518                  */
519                 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
520                 tbl->it_busno = sw_inval[1]; /* overload this with magic */
521                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
522         }
523 }
524 
525 /*
526  * iommu_table_setparms_lpar
527  *
528  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
529  */
530 static void iommu_table_setparms_lpar(struct pci_controller *phb,
531                                       struct device_node *dn,
532                                       struct iommu_table *tbl,
533                                       const void *dma_window)
534 {
535         unsigned long offset, size;
536 
537         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
538 
539         tbl->it_busno = phb->bus->number;
540         tbl->it_base   = 0;
541         tbl->it_blocksize  = 16;
542         tbl->it_type = TCE_PCI;
543         tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
544         tbl->it_size = size >> IOMMU_PAGE_SHIFT;
545 }
546 
547 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
548 {
549         struct device_node *dn;
550         struct iommu_table *tbl;
551         struct device_node *isa_dn, *isa_dn_orig;
552         struct device_node *tmp;
553         struct pci_dn *pci;
554         int children;
555 
556         dn = pci_bus_to_OF_node(bus);
557 
558         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
559 
560         if (bus->self) {
561                 /* This is not a root bus, any setup will be done for the
562                  * device-side of the bridge in iommu_dev_setup_pSeries().
563                  */
564                 return;
565         }
566         pci = PCI_DN(dn);
567 
568         /* Check if the ISA bus on the system is under
569          * this PHB.
570          */
571         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
572 
573         while (isa_dn && isa_dn != dn)
574                 isa_dn = isa_dn->parent;
575 
576         if (isa_dn_orig)
577                 of_node_put(isa_dn_orig);
578 
579         /* Count number of direct PCI children of the PHB. */
580         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
581                 children++;
582 
583         pr_debug("Children: %d\n", children);
584 
585         /* Calculate amount of DMA window per slot. Each window must be
586          * a power of two (due to pci_alloc_consistent requirements).
587          *
588          * Keep 256MB aside for PHBs with ISA.
589          */
590 
591         if (!isa_dn) {
592                 /* No ISA/IDE - just set window size and return */
593                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
594 
595                 while (pci->phb->dma_window_size * children > 0x80000000ul)
596                         pci->phb->dma_window_size >>= 1;
597                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
598                          pci->phb->dma_window_size);
599                 pci->phb->dma_window_base_cur = 0;
600 
601                 return;
602         }
603 
604         /* If we have ISA, then we probably have an IDE
605          * controller too. Allocate a 128MB table but
606          * skip the first 128MB to avoid stepping on ISA
607          * space.
608          */
609         pci->phb->dma_window_size = 0x8000000ul;
610         pci->phb->dma_window_base_cur = 0x8000000ul;
611 
612         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
613                            pci->phb->node);
614 
615         iommu_table_setparms(pci->phb, dn, tbl);
616         pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
617 
618         /* Divide the rest (1.75GB) among the children */
619         pci->phb->dma_window_size = 0x80000000ul;
620         while (pci->phb->dma_window_size * children > 0x70000000ul)
621                 pci->phb->dma_window_size >>= 1;
622 
623         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
624 }
625 
626 
627 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
628 {
629         struct iommu_table *tbl;
630         struct device_node *dn, *pdn;
631         struct pci_dn *ppci;
632         const void *dma_window = NULL;
633 
634         dn = pci_bus_to_OF_node(bus);
635 
636         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
637                  dn->full_name);
638 
639         /* Find nearest ibm,dma-window, walking up the device tree */
640         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
641                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
642                 if (dma_window != NULL)
643                         break;
644         }
645 
646         if (dma_window == NULL) {
647                 pr_debug("  no ibm,dma-window property !\n");
648                 return;
649         }
650 
651         ppci = PCI_DN(pdn);
652 
653         pr_debug("  parent is %s, iommu_table: 0x%p\n",
654                  pdn->full_name, ppci->iommu_table);
655 
656         if (!ppci->iommu_table) {
657                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
658                                    ppci->phb->node);
659                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
660                 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
661                 pr_debug("  created table: %p\n", ppci->iommu_table);
662         }
663 }
664 
665 
666 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
667 {
668         struct device_node *dn;
669         struct iommu_table *tbl;
670 
671         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
672 
673         dn = dev->dev.of_node;
674 
675         /* If we're the direct child of a root bus, then we need to allocate
676          * an iommu table ourselves. The bus setup code should have setup
677          * the window sizes already.
678          */
679         if (!dev->bus->self) {
680                 struct pci_controller *phb = PCI_DN(dn)->phb;
681 
682                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
683                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
684                                    phb->node);
685                 iommu_table_setparms(phb, dn, tbl);
686                 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
687                 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
688                 return;
689         }
690 
691         /* If this device is further down the bus tree, search upwards until
692          * an already allocated iommu table is found and use that.
693          */
694 
695         while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
696                 dn = dn->parent;
697 
698         if (dn && PCI_DN(dn))
699                 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
700         else
701                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
702                        pci_name(dev));
703 }
704 
705 static int __read_mostly disable_ddw;
706 
707 static int __init disable_ddw_setup(char *str)
708 {
709         disable_ddw = 1;
710         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
711 
712         return 0;
713 }
714 
715 early_param("disable_ddw", disable_ddw_setup);
716 
717 static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn)
718 {
719         int ret;
720 
721         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
722         if (ret)
723                 pr_warning("%s: failed to remove DMA window: rtas returned "
724                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
725                         np->full_name, ret, ddw_avail[2], liobn);
726         else
727                 pr_debug("%s: successfully removed DMA window: rtas returned "
728                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
729                         np->full_name, ret, ddw_avail[2], liobn);
730 }
731 
732 static void remove_ddw(struct device_node *np)
733 {
734         struct dynamic_dma_window_prop *dwp;
735         struct property *win64;
736         const u32 *ddw_avail;
737         u64 liobn;
738         int len, ret;
739 
740         ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len);
741         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
742         if (!win64)
743                 return;
744 
745         if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp))
746                 goto delprop;
747 
748         dwp = win64->value;
749         liobn = (u64)be32_to_cpu(dwp->liobn);
750 
751         /* clear the whole window, note the arg is in kernel pages */
752         ret = tce_clearrange_multi_pSeriesLP(0,
753                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
754         if (ret)
755                 pr_warning("%s failed to clear tces in window.\n",
756                          np->full_name);
757         else
758                 pr_debug("%s successfully cleared tces in window.\n",
759                          np->full_name);
760 
761         __remove_ddw(np, ddw_avail, liobn);
762 
763 delprop:
764         ret = of_remove_property(np, win64);
765         if (ret)
766                 pr_warning("%s: failed to remove direct window property: %d\n",
767                         np->full_name, ret);
768 }
769 
770 static u64 find_existing_ddw(struct device_node *pdn)
771 {
772         struct direct_window *window;
773         const struct dynamic_dma_window_prop *direct64;
774         u64 dma_addr = 0;
775 
776         spin_lock(&direct_window_list_lock);
777         /* check if we already created a window and dupe that config if so */
778         list_for_each_entry(window, &direct_window_list, list) {
779                 if (window->device == pdn) {
780                         direct64 = window->prop;
781                         dma_addr = direct64->dma_base;
782                         break;
783                 }
784         }
785         spin_unlock(&direct_window_list_lock);
786 
787         return dma_addr;
788 }
789 
790 static void __restore_default_window(struct eeh_dev *edev,
791                                                 u32 ddw_restore_token)
792 {
793         u32 cfg_addr;
794         u64 buid;
795         int ret;
796 
797         /*
798          * Get the config address and phb buid of the PE window.
799          * Rely on eeh to retrieve this for us.
800          * Retrieve them from the pci device, not the node with the
801          * dma-window property
802          */
803         cfg_addr = edev->config_addr;
804         if (edev->pe_config_addr)
805                 cfg_addr = edev->pe_config_addr;
806         buid = edev->phb->buid;
807 
808         do {
809                 ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr,
810                                         BUID_HI(buid), BUID_LO(buid));
811         } while (rtas_busy_delay(ret));
812         pr_info("ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n",
813                  ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret);
814 }
815 
816 static int find_existing_ddw_windows(void)
817 {
818         struct device_node *pdn;
819         const struct dynamic_dma_window_prop *direct64;
820         const u32 *ddw_extensions;
821 
822         if (!firmware_has_feature(FW_FEATURE_LPAR))
823                 return 0;
824 
825         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
826                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, NULL);
827                 if (!direct64)
828                         continue;
829 
830                 /*
831                  * We need to ensure the IOMMU table is active when we
832                  * return from the IOMMU setup so that the common code
833                  * can clear the table or find the holes. To that end,
834                  * first, remove any existing DDW configuration.
835                  */
836                 remove_ddw(pdn);
837 
838                 /*
839                  * Second, if we are running on a new enough level of
840                  * firmware where the restore API is present, use it to
841                  * restore the 32-bit window, which was removed in
842                  * create_ddw.
843                  * If the API is not present, then create_ddw couldn't
844                  * have removed the 32-bit window in the first place, so
845                  * removing the DDW configuration should be sufficient.
846                  */
847                 ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions",
848                                                                         NULL);
849                 if (ddw_extensions && ddw_extensions[0] > 0)
850                         __restore_default_window(of_node_to_eeh_dev(pdn),
851                                                         ddw_extensions[1]);
852         }
853 
854         return 0;
855 }
856 machine_arch_initcall(pseries, find_existing_ddw_windows);
857 
858 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
859                         struct ddw_query_response *query)
860 {
861         struct device_node *dn;
862         struct pci_dn *pdn;
863         u32 cfg_addr;
864         u64 buid;
865         int ret;
866 
867         /*
868          * Get the config address and phb buid of the PE window.
869          * Rely on eeh to retrieve this for us.
870          * Retrieve them from the pci device, not the node with the
871          * dma-window property
872          */
873         dn = pci_device_to_OF_node(dev);
874         pdn = PCI_DN(dn);
875         buid = pdn->phb->buid;
876         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
877 
878         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
879                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
880         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
881                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
882                 BUID_LO(buid), ret);
883         return ret;
884 }
885 
886 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
887                         struct ddw_create_response *create, int page_shift,
888                         int window_shift)
889 {
890         struct device_node *dn;
891         struct pci_dn *pdn;
892         u32 cfg_addr;
893         u64 buid;
894         int ret;
895 
896         /*
897          * Get the config address and phb buid of the PE window.
898          * Rely on eeh to retrieve this for us.
899          * Retrieve them from the pci device, not the node with the
900          * dma-window property
901          */
902         dn = pci_device_to_OF_node(dev);
903         pdn = PCI_DN(dn);
904         buid = pdn->phb->buid;
905         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
906 
907         do {
908                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
909                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr,
910                                 BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
911         } while (rtas_busy_delay(ret));
912         dev_info(&dev->dev,
913                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
914                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
915                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
916                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
917 
918         return ret;
919 }
920 
921 static void restore_default_window(struct pci_dev *dev,
922                                         u32 ddw_restore_token)
923 {
924         __restore_default_window(pci_dev_to_eeh_dev(dev), ddw_restore_token);
925 }
926 
927 struct failed_ddw_pdn {
928         struct device_node *pdn;
929         struct list_head list;
930 };
931 
932 static LIST_HEAD(failed_ddw_pdn_list);
933 
934 /*
935  * If the PE supports dynamic dma windows, and there is space for a table
936  * that can map all pages in a linear offset, then setup such a table,
937  * and record the dma-offset in the struct device.
938  *
939  * dev: the pci device we are checking
940  * pdn: the parent pe node with the ibm,dma_window property
941  * Future: also check if we can remap the base window for our base page size
942  *
943  * returns the dma offset for use by dma_set_mask
944  */
945 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
946 {
947         int len, ret;
948         struct ddw_query_response query;
949         struct ddw_create_response create;
950         int page_shift;
951         u64 dma_addr, max_addr;
952         struct device_node *dn;
953         const u32 *uninitialized_var(ddw_avail);
954         const u32 *uninitialized_var(ddw_extensions);
955         u32 ddw_restore_token = 0;
956         struct direct_window *window;
957         struct property *win64;
958         struct dynamic_dma_window_prop *ddwprop;
959         const void *dma_window = NULL;
960         unsigned long liobn, offset, size;
961         struct failed_ddw_pdn *fpdn;
962 
963         mutex_lock(&direct_window_init_mutex);
964 
965         dma_addr = find_existing_ddw(pdn);
966         if (dma_addr != 0)
967                 goto out_unlock;
968 
969         /*
970          * If we already went through this for a previous function of
971          * the same device and failed, we don't want to muck with the
972          * DMA window again, as it will race with in-flight operations
973          * and can lead to EEHs. The above mutex protects access to the
974          * list.
975          */
976         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
977                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
978                         goto out_unlock;
979         }
980 
981         /*
982          * the ibm,ddw-applicable property holds the tokens for:
983          * ibm,query-pe-dma-window
984          * ibm,create-pe-dma-window
985          * ibm,remove-pe-dma-window
986          * for the given node in that order.
987          * the property is actually in the parent, not the PE
988          */
989         ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
990         if (!ddw_avail || len < 3 * sizeof(u32))
991                 goto out_unlock;
992 
993         /*
994          * the extensions property is only required to exist in certain
995          * levels of firmware and later
996          * the ibm,ddw-extensions property is a list with the first
997          * element containing the number of extensions and each
998          * subsequent entry is a value corresponding to that extension
999          */
1000         ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len);
1001         if (ddw_extensions) {
1002                 /*
1003                  * each new defined extension length should be added to
1004                  * the top of the switch so the "earlier" entries also
1005                  * get picked up
1006                  */
1007                 switch (ddw_extensions[0]) {
1008                         /* ibm,reset-pe-dma-windows */
1009                         case 1:
1010                                 ddw_restore_token = ddw_extensions[1];
1011                                 break;
1012                 }
1013         }
1014 
1015         /*
1016          * Only remove the existing DMA window if we can restore back to
1017          * the default state. Removing the existing window maximizes the
1018          * resources available to firmware for dynamic window creation.
1019          */
1020         if (ddw_restore_token) {
1021                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1022                 of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size);
1023                 __remove_ddw(pdn, ddw_avail, liobn);
1024         }
1025 
1026         /*
1027          * Query if there is a second window of size to map the
1028          * whole partition.  Query returns number of windows, largest
1029          * block assigned to PE (partition endpoint), and two bitmasks
1030          * of page sizes: supported and supported for migrate-dma.
1031          */
1032         dn = pci_device_to_OF_node(dev);
1033         ret = query_ddw(dev, ddw_avail, &query);
1034         if (ret != 0)
1035                 goto out_restore_window;
1036 
1037         if (query.windows_available == 0) {
1038                 /*
1039                  * no additional windows are available for this device.
1040                  * We might be able to reallocate the existing window,
1041                  * trading in for a larger page size.
1042                  */
1043                 dev_dbg(&dev->dev, "no free dynamic windows");
1044                 goto out_restore_window;
1045         }
1046         if (query.page_size & 4) {
1047                 page_shift = 24; /* 16MB */
1048         } else if (query.page_size & 2) {
1049                 page_shift = 16; /* 64kB */
1050         } else if (query.page_size & 1) {
1051                 page_shift = 12; /* 4kB */
1052         } else {
1053                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1054                           query.page_size);
1055                 goto out_restore_window;
1056         }
1057         /* verify the window * number of ptes will map the partition */
1058         /* check largest block * page size > max memory hotplug addr */
1059         max_addr = memory_hotplug_max();
1060         if (query.largest_available_block < (max_addr >> page_shift)) {
1061                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1062                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1063                           1ULL << page_shift);
1064                 goto out_restore_window;
1065         }
1066         len = order_base_2(max_addr);
1067         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1068         if (!win64) {
1069                 dev_info(&dev->dev,
1070                         "couldn't allocate property for 64bit dma window\n");
1071                 goto out_restore_window;
1072         }
1073         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1074         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1075         win64->length = sizeof(*ddwprop);
1076         if (!win64->name || !win64->value) {
1077                 dev_info(&dev->dev,
1078                         "couldn't allocate property name and value\n");
1079                 goto out_free_prop;
1080         }
1081 
1082         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1083         if (ret != 0)
1084                 goto out_free_prop;
1085 
1086         ddwprop->liobn = cpu_to_be32(create.liobn);
1087         ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
1088         ddwprop->tce_shift = cpu_to_be32(page_shift);
1089         ddwprop->window_shift = cpu_to_be32(len);
1090 
1091         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1092                   create.liobn, dn->full_name);
1093 
1094         window = kzalloc(sizeof(*window), GFP_KERNEL);
1095         if (!window)
1096                 goto out_clear_window;
1097 
1098         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1099                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1100         if (ret) {
1101                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1102                          dn->full_name, ret);
1103                 goto out_free_window;
1104         }
1105 
1106         ret = of_add_property(pdn, win64);
1107         if (ret) {
1108                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1109                          pdn->full_name, ret);
1110                 goto out_free_window;
1111         }
1112 
1113         window->device = pdn;
1114         window->prop = ddwprop;
1115         spin_lock(&direct_window_list_lock);
1116         list_add(&window->list, &direct_window_list);
1117         spin_unlock(&direct_window_list_lock);
1118 
1119         dma_addr = of_read_number(&create.addr_hi, 2);
1120         goto out_unlock;
1121 
1122 out_free_window:
1123         kfree(window);
1124 
1125 out_clear_window:
1126         remove_ddw(pdn);
1127 
1128 out_free_prop:
1129         kfree(win64->name);
1130         kfree(win64->value);
1131         kfree(win64);
1132 
1133 out_restore_window:
1134         if (ddw_restore_token)
1135                 restore_default_window(dev, ddw_restore_token);
1136 
1137         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1138         if (!fpdn)
1139                 goto out_unlock;
1140         fpdn->pdn = pdn;
1141         list_add(&fpdn->list, &failed_ddw_pdn_list);
1142 
1143 out_unlock:
1144         mutex_unlock(&direct_window_init_mutex);
1145         return dma_addr;
1146 }
1147 
1148 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1149 {
1150         struct device_node *pdn, *dn;
1151         struct iommu_table *tbl;
1152         const void *dma_window = NULL;
1153         struct pci_dn *pci;
1154 
1155         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1156 
1157         /* dev setup for LPAR is a little tricky, since the device tree might
1158          * contain the dma-window properties per-device and not necessarily
1159          * for the bus. So we need to search upwards in the tree until we
1160          * either hit a dma-window property, OR find a parent with a table
1161          * already allocated.
1162          */
1163         dn = pci_device_to_OF_node(dev);
1164         pr_debug("  node is %s\n", dn->full_name);
1165 
1166         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1167              pdn = pdn->parent) {
1168                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1169                 if (dma_window)
1170                         break;
1171         }
1172 
1173         if (!pdn || !PCI_DN(pdn)) {
1174                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1175                        "no DMA window found for pci dev=%s dn=%s\n",
1176                                  pci_name(dev), of_node_full_name(dn));
1177                 return;
1178         }
1179         pr_debug("  parent is %s\n", pdn->full_name);
1180 
1181         pci = PCI_DN(pdn);
1182         if (!pci->iommu_table) {
1183                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
1184                                    pci->phb->node);
1185                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1186                 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
1187                 pr_debug("  created table: %p\n", pci->iommu_table);
1188         } else {
1189                 pr_debug("  found DMA window, table: %p\n", pci->iommu_table);
1190         }
1191 
1192         set_iommu_table_base(&dev->dev, pci->iommu_table);
1193 }
1194 
1195 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1196 {
1197         bool ddw_enabled = false;
1198         struct device_node *pdn, *dn;
1199         struct pci_dev *pdev;
1200         const void *dma_window = NULL;
1201         u64 dma_offset;
1202 
1203         if (!dev->dma_mask)
1204                 return -EIO;
1205 
1206         if (!dev_is_pci(dev))
1207                 goto check_mask;
1208 
1209         pdev = to_pci_dev(dev);
1210 
1211         /* only attempt to use a new window if 64-bit DMA is requested */
1212         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1213                 dn = pci_device_to_OF_node(pdev);
1214                 dev_dbg(dev, "node is %s\n", dn->full_name);
1215 
1216                 /*
1217                  * the device tree might contain the dma-window properties
1218                  * per-device and not necessarily for the bus. So we need to
1219                  * search upwards in the tree until we either hit a dma-window
1220                  * property, OR find a parent with a table already allocated.
1221                  */
1222                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1223                                 pdn = pdn->parent) {
1224                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1225                         if (dma_window)
1226                                 break;
1227                 }
1228                 if (pdn && PCI_DN(pdn)) {
1229                         dma_offset = enable_ddw(pdev, pdn);
1230                         if (dma_offset != 0) {
1231                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1232                                 set_dma_offset(dev, dma_offset);
1233                                 set_dma_ops(dev, &dma_direct_ops);
1234                                 ddw_enabled = true;
1235                         }
1236                 }
1237         }
1238 
1239         /* fall back on iommu ops, restore table pointer with ops */
1240         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1241                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1242                 set_dma_ops(dev, &dma_iommu_ops);
1243                 pci_dma_dev_setup_pSeriesLP(pdev);
1244         }
1245 
1246 check_mask:
1247         if (!dma_supported(dev, dma_mask))
1248                 return -EIO;
1249 
1250         *dev->dma_mask = dma_mask;
1251         return 0;
1252 }
1253 
1254 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1255 {
1256         if (!dev->dma_mask)
1257                 return 0;
1258 
1259         if (!disable_ddw && dev_is_pci(dev)) {
1260                 struct pci_dev *pdev = to_pci_dev(dev);
1261                 struct device_node *dn;
1262 
1263                 dn = pci_device_to_OF_node(pdev);
1264 
1265                 /* search upwards for ibm,dma-window */
1266                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
1267                                 dn = dn->parent)
1268                         if (of_get_property(dn, "ibm,dma-window", NULL))
1269                                 break;
1270                 /* if there is a ibm,ddw-applicable property require 64 bits */
1271                 if (dn && PCI_DN(dn) &&
1272                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1273                         return DMA_BIT_MASK(64);
1274         }
1275 
1276         return dma_iommu_ops.get_required_mask(dev);
1277 }
1278 
1279 #else  /* CONFIG_PCI */
1280 #define pci_dma_bus_setup_pSeries       NULL
1281 #define pci_dma_dev_setup_pSeries       NULL
1282 #define pci_dma_bus_setup_pSeriesLP     NULL
1283 #define pci_dma_dev_setup_pSeriesLP     NULL
1284 #define dma_set_mask_pSeriesLP          NULL
1285 #define dma_get_required_mask_pSeriesLP NULL
1286 #endif /* !CONFIG_PCI */
1287 
1288 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1289                 void *data)
1290 {
1291         struct direct_window *window;
1292         struct memory_notify *arg = data;
1293         int ret = 0;
1294 
1295         switch (action) {
1296         case MEM_GOING_ONLINE:
1297                 spin_lock(&direct_window_list_lock);
1298                 list_for_each_entry(window, &direct_window_list, list) {
1299                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1300                                         arg->nr_pages, window->prop);
1301                         /* XXX log error */
1302                 }
1303                 spin_unlock(&direct_window_list_lock);
1304                 break;
1305         case MEM_CANCEL_ONLINE:
1306         case MEM_OFFLINE:
1307                 spin_lock(&direct_window_list_lock);
1308                 list_for_each_entry(window, &direct_window_list, list) {
1309                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1310                                         arg->nr_pages, window->prop);
1311                         /* XXX log error */
1312                 }
1313                 spin_unlock(&direct_window_list_lock);
1314                 break;
1315         default:
1316                 break;
1317         }
1318         if (ret && action != MEM_CANCEL_ONLINE)
1319                 return NOTIFY_BAD;
1320 
1321         return NOTIFY_OK;
1322 }
1323 
1324 static struct notifier_block iommu_mem_nb = {
1325         .notifier_call = iommu_mem_notifier,
1326 };
1327 
1328 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
1329 {
1330         int err = NOTIFY_OK;
1331         struct device_node *np = node;
1332         struct pci_dn *pci = PCI_DN(np);
1333         struct direct_window *window;
1334 
1335         switch (action) {
1336         case OF_RECONFIG_DETACH_NODE:
1337                 remove_ddw(np);
1338                 if (pci && pci->iommu_table)
1339                         iommu_free_table(pci->iommu_table, np->full_name);
1340 
1341                 spin_lock(&direct_window_list_lock);
1342                 list_for_each_entry(window, &direct_window_list, list) {
1343                         if (window->device == np) {
1344                                 list_del(&window->list);
1345                                 kfree(window);
1346                                 break;
1347                         }
1348                 }
1349                 spin_unlock(&direct_window_list_lock);
1350                 break;
1351         default:
1352                 err = NOTIFY_DONE;
1353                 break;
1354         }
1355         return err;
1356 }
1357 
1358 static struct notifier_block iommu_reconfig_nb = {
1359         .notifier_call = iommu_reconfig_notifier,
1360 };
1361 
1362 /* These are called very early. */
1363 void iommu_init_early_pSeries(void)
1364 {
1365         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1366                 return;
1367 
1368         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1369                 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
1370                         ppc_md.tce_build = tce_buildmulti_pSeriesLP;
1371                         ppc_md.tce_free  = tce_freemulti_pSeriesLP;
1372                 } else {
1373                         ppc_md.tce_build = tce_build_pSeriesLP;
1374                         ppc_md.tce_free  = tce_free_pSeriesLP;
1375                 }
1376                 ppc_md.tce_get   = tce_get_pSeriesLP;
1377                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1378                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1379                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1380                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1381         } else {
1382                 ppc_md.tce_build = tce_build_pSeries;
1383                 ppc_md.tce_free  = tce_free_pSeries;
1384                 ppc_md.tce_get   = tce_get_pseries;
1385                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
1386                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
1387         }
1388 
1389 
1390         of_reconfig_notifier_register(&iommu_reconfig_nb);
1391         register_memory_notifier(&iommu_mem_nb);
1392 
1393         set_pci_dma_ops(&dma_iommu_ops);
1394 }
1395 
1396 static int __init disable_multitce(char *str)
1397 {
1398         if (strcmp(str, "off") == 0 &&
1399             firmware_has_feature(FW_FEATURE_LPAR) &&
1400             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1401                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1402                 ppc_md.tce_build = tce_build_pSeriesLP;
1403                 ppc_md.tce_free  = tce_free_pSeriesLP;
1404                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1405         }
1406         return 1;
1407 }
1408 
1409 __setup("multitce=", disable_multitce);
1410 

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