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Linux/arch/powerpc/sysdev/fsl_lbc.c

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  1 /*
  2  * Freescale LBC and UPM routines.
  3  *
  4  * Copyright © 2007-2008  MontaVista Software, Inc.
  5  * Copyright © 2010 Freescale Semiconductor
  6  *
  7  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  8  * Author: Jack Lan <Jack.Lan@freescale.com>
  9  * Author: Roy Zang <tie-fei.zang@freescale.com>
 10  *
 11  * This program is free software; you can redistribute it and/or modify
 12  * it under the terms of the GNU General Public License as published by
 13  * the Free Software Foundation; either version 2 of the License, or
 14  * (at your option) any later version.
 15  */
 16 
 17 #include <linux/init.h>
 18 #include <linux/export.h>
 19 #include <linux/kernel.h>
 20 #include <linux/compiler.h>
 21 #include <linux/spinlock.h>
 22 #include <linux/types.h>
 23 #include <linux/io.h>
 24 #include <linux/of.h>
 25 #include <linux/slab.h>
 26 #include <linux/sched.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/mod_devicetable.h>
 30 #include <asm/prom.h>
 31 #include <asm/fsl_lbc.h>
 32 
 33 static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
 34 struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
 35 EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
 36 
 37 /**
 38  * fsl_lbc_addr - convert the base address
 39  * @addr_base:  base address of the memory bank
 40  *
 41  * This function converts a base address of lbc into the right format for the
 42  * BR register. If the SOC has eLBC then it returns 32bit physical address
 43  * else it convers a 34bit local bus physical address to correct format of
 44  * 32bit address for BR register (Example: MPC8641).
 45  */
 46 u32 fsl_lbc_addr(phys_addr_t addr_base)
 47 {
 48         struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
 49         u32 addr = addr_base & 0xffff8000;
 50 
 51         if (of_device_is_compatible(np, "fsl,elbc"))
 52                 return addr;
 53 
 54         return addr | ((addr_base & 0x300000000ull) >> 19);
 55 }
 56 EXPORT_SYMBOL(fsl_lbc_addr);
 57 
 58 /**
 59  * fsl_lbc_find - find Localbus bank
 60  * @addr_base:  base address of the memory bank
 61  *
 62  * This function walks LBC banks comparing "Base address" field of the BR
 63  * registers with the supplied addr_base argument. When bases match this
 64  * function returns bank number (starting with 0), otherwise it returns
 65  * appropriate errno value.
 66  */
 67 int fsl_lbc_find(phys_addr_t addr_base)
 68 {
 69         int i;
 70         struct fsl_lbc_regs __iomem *lbc;
 71 
 72         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
 73                 return -ENODEV;
 74 
 75         lbc = fsl_lbc_ctrl_dev->regs;
 76         for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
 77                 u32 br = in_be32(&lbc->bank[i].br);
 78                 u32 or = in_be32(&lbc->bank[i].or);
 79 
 80                 if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
 81                         return i;
 82         }
 83 
 84         return -ENOENT;
 85 }
 86 EXPORT_SYMBOL(fsl_lbc_find);
 87 
 88 /**
 89  * fsl_upm_find - find pre-programmed UPM via base address
 90  * @addr_base:  base address of the memory bank controlled by the UPM
 91  * @upm:        pointer to the allocated fsl_upm structure
 92  *
 93  * This function fills fsl_upm structure so you can use it with the rest of
 94  * UPM API. On success this function returns 0, otherwise it returns
 95  * appropriate errno value.
 96  */
 97 int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
 98 {
 99         int bank;
100         u32 br;
101         struct fsl_lbc_regs __iomem *lbc;
102 
103         bank = fsl_lbc_find(addr_base);
104         if (bank < 0)
105                 return bank;
106 
107         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
108                 return -ENODEV;
109 
110         lbc = fsl_lbc_ctrl_dev->regs;
111         br = in_be32(&lbc->bank[bank].br);
112 
113         switch (br & BR_MSEL) {
114         case BR_MS_UPMA:
115                 upm->mxmr = &lbc->mamr;
116                 break;
117         case BR_MS_UPMB:
118                 upm->mxmr = &lbc->mbmr;
119                 break;
120         case BR_MS_UPMC:
121                 upm->mxmr = &lbc->mcmr;
122                 break;
123         default:
124                 return -EINVAL;
125         }
126 
127         switch (br & BR_PS) {
128         case BR_PS_8:
129                 upm->width = 8;
130                 break;
131         case BR_PS_16:
132                 upm->width = 16;
133                 break;
134         case BR_PS_32:
135                 upm->width = 32;
136                 break;
137         default:
138                 return -EINVAL;
139         }
140 
141         return 0;
142 }
143 EXPORT_SYMBOL(fsl_upm_find);
144 
145 /**
146  * fsl_upm_run_pattern - actually run an UPM pattern
147  * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
148  * @io_base:    remapped pointer to where memory access should happen
149  * @mar:        MAR register content during pattern execution
150  *
151  * This function triggers dummy write to the memory specified by the io_base,
152  * thus UPM pattern actually executed. Note that mar usage depends on the
153  * pre-programmed AMX bits in the UPM RAM.
154  */
155 int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
156 {
157         int ret = 0;
158         unsigned long flags;
159 
160         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
161                 return -ENODEV;
162 
163         spin_lock_irqsave(&fsl_lbc_lock, flags);
164 
165         out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
166 
167         switch (upm->width) {
168         case 8:
169                 out_8(io_base, 0x0);
170                 break;
171         case 16:
172                 out_be16(io_base, 0x0);
173                 break;
174         case 32:
175                 out_be32(io_base, 0x0);
176                 break;
177         default:
178                 ret = -EINVAL;
179                 break;
180         }
181 
182         spin_unlock_irqrestore(&fsl_lbc_lock, flags);
183 
184         return ret;
185 }
186 EXPORT_SYMBOL(fsl_upm_run_pattern);
187 
188 static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
189                              struct device_node *node)
190 {
191         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
192 
193         /* clear event registers */
194         setbits32(&lbc->ltesr, LTESR_CLEAR);
195         out_be32(&lbc->lteatr, 0);
196         out_be32(&lbc->ltear, 0);
197         out_be32(&lbc->lteccr, LTECCR_CLEAR);
198         out_be32(&lbc->ltedr, LTEDR_ENABLE);
199 
200         /* Set the monitor timeout value to the maximum for erratum A001 */
201         if (of_device_is_compatible(node, "fsl,elbc"))
202                 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
203 
204         return 0;
205 }
206 
207 /*
208  * NOTE: This interrupt is used to report localbus events of various kinds,
209  * such as transaction errors on the chipselects.
210  */
211 
212 static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
213 {
214         struct fsl_lbc_ctrl *ctrl = data;
215         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
216         u32 status;
217 
218         status = in_be32(&lbc->ltesr);
219         if (!status)
220                 return IRQ_NONE;
221 
222         out_be32(&lbc->ltesr, LTESR_CLEAR);
223         out_be32(&lbc->lteatr, 0);
224         out_be32(&lbc->ltear, 0);
225         ctrl->irq_status = status;
226 
227         if (status & LTESR_BM)
228                 dev_err(ctrl->dev, "Local bus monitor time-out: "
229                         "LTESR 0x%08X\n", status);
230         if (status & LTESR_WP)
231                 dev_err(ctrl->dev, "Write protect error: "
232                         "LTESR 0x%08X\n", status);
233         if (status & LTESR_ATMW)
234                 dev_err(ctrl->dev, "Atomic write error: "
235                         "LTESR 0x%08X\n", status);
236         if (status & LTESR_ATMR)
237                 dev_err(ctrl->dev, "Atomic read error: "
238                         "LTESR 0x%08X\n", status);
239         if (status & LTESR_CS)
240                 dev_err(ctrl->dev, "Chip select error: "
241                         "LTESR 0x%08X\n", status);
242         if (status & LTESR_UPM)
243                 ;
244         if (status & LTESR_FCT) {
245                 dev_err(ctrl->dev, "FCM command time-out: "
246                         "LTESR 0x%08X\n", status);
247                 smp_wmb();
248                 wake_up(&ctrl->irq_wait);
249         }
250         if (status & LTESR_PAR) {
251                 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
252                         "LTESR 0x%08X\n", status);
253                 smp_wmb();
254                 wake_up(&ctrl->irq_wait);
255         }
256         if (status & LTESR_CC) {
257                 smp_wmb();
258                 wake_up(&ctrl->irq_wait);
259         }
260         if (status & ~LTESR_MASK)
261                 dev_err(ctrl->dev, "Unknown error: "
262                         "LTESR 0x%08X\n", status);
263         return IRQ_HANDLED;
264 }
265 
266 /*
267  * fsl_lbc_ctrl_probe
268  *
269  * called by device layer when it finds a device matching
270  * one our driver can handled. This code allocates all of
271  * the resources needed for the controller only.  The
272  * resources for the NAND banks themselves are allocated
273  * in the chip probe function.
274 */
275 
276 static int fsl_lbc_ctrl_probe(struct platform_device *dev)
277 {
278         int ret;
279 
280         if (!dev->dev.of_node) {
281                 dev_err(&dev->dev, "Device OF-Node is NULL");
282                 return -EFAULT;
283         }
284 
285         fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
286         if (!fsl_lbc_ctrl_dev)
287                 return -ENOMEM;
288 
289         dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
290 
291         spin_lock_init(&fsl_lbc_ctrl_dev->lock);
292         init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
293 
294         fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
295         if (!fsl_lbc_ctrl_dev->regs) {
296                 dev_err(&dev->dev, "failed to get memory region\n");
297                 ret = -ENODEV;
298                 goto err;
299         }
300 
301         fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
302         if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
303                 dev_err(&dev->dev, "failed to get irq resource\n");
304                 ret = -ENODEV;
305                 goto err;
306         }
307 
308         fsl_lbc_ctrl_dev->dev = &dev->dev;
309 
310         ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
311         if (ret < 0)
312                 goto err;
313 
314         ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
315                                 "fsl-lbc", fsl_lbc_ctrl_dev);
316         if (ret != 0) {
317                 dev_err(&dev->dev, "failed to install irq (%d)\n",
318                         fsl_lbc_ctrl_dev->irq);
319                 ret = fsl_lbc_ctrl_dev->irq;
320                 goto err;
321         }
322 
323         /* Enable interrupts for any detected events */
324         out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
325 
326         return 0;
327 
328 err:
329         iounmap(fsl_lbc_ctrl_dev->regs);
330         kfree(fsl_lbc_ctrl_dev);
331         fsl_lbc_ctrl_dev = NULL;
332         return ret;
333 }
334 
335 #ifdef CONFIG_SUSPEND
336 
337 /* save lbc registers */
338 static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state)
339 {
340         struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
341         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
342 
343         ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
344         if (!ctrl->saved_regs)
345                 return -ENOMEM;
346 
347         _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
348         return 0;
349 }
350 
351 /* restore lbc registers */
352 static int fsl_lbc_resume(struct platform_device *pdev)
353 {
354         struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
355         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
356 
357         if (ctrl->saved_regs) {
358                 _memcpy_toio(lbc, ctrl->saved_regs,
359                                 sizeof(struct fsl_lbc_regs));
360                 kfree(ctrl->saved_regs);
361                 ctrl->saved_regs = NULL;
362         }
363         return 0;
364 }
365 #endif /* CONFIG_SUSPEND */
366 
367 static const struct of_device_id fsl_lbc_match[] = {
368         { .compatible = "fsl,elbc", },
369         { .compatible = "fsl,pq3-localbus", },
370         { .compatible = "fsl,pq2-localbus", },
371         { .compatible = "fsl,pq2pro-localbus", },
372         {},
373 };
374 
375 static struct platform_driver fsl_lbc_ctrl_driver = {
376         .driver = {
377                 .name = "fsl-lbc",
378                 .of_match_table = fsl_lbc_match,
379         },
380         .probe = fsl_lbc_ctrl_probe,
381 #ifdef CONFIG_SUSPEND
382         .suspend     = fsl_lbc_suspend,
383         .resume      = fsl_lbc_resume,
384 #endif
385 };
386 
387 static int __init fsl_lbc_init(void)
388 {
389         return platform_driver_register(&fsl_lbc_ctrl_driver);
390 }
391 module_init(fsl_lbc_init);
392 

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