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TOMOYO Linux Cross Reference
Linux/arch/powerpc/sysdev/fsl_pci.c

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  1 /*
  2  * MPC83xx/85xx/86xx PCI/PCIE support routing.
  3  *
  4  * Copyright 2007-2011 Freescale Semiconductor, Inc.
  5  * Copyright 2008-2009 MontaVista Software, Inc.
  6  *
  7  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
  8  * Recode: ZHANG WEI <wei.zhang@freescale.com>
  9  * Rewrite the routing for Frescale PCI and PCI Express
 10  *      Roy Zang <tie-fei.zang@freescale.com>
 11  * MPC83xx PCI-Express support:
 12  *      Tony Li <tony.li@freescale.com>
 13  *      Anton Vorontsov <avorontsov@ru.mvista.com>
 14  *
 15  * This program is free software; you can redistribute  it and/or modify it
 16  * under  the terms of  the GNU General  Public License as published by the
 17  * Free Software Foundation;  either version 2 of the  License, or (at your
 18  * option) any later version.
 19  */
 20 #include <linux/kernel.h>
 21 #include <linux/pci.h>
 22 #include <linux/delay.h>
 23 #include <linux/string.h>
 24 #include <linux/init.h>
 25 #include <linux/bootmem.h>
 26 #include <linux/memblock.h>
 27 #include <linux/log2.h>
 28 #include <linux/slab.h>
 29 
 30 #include <asm/io.h>
 31 #include <asm/prom.h>
 32 #include <asm/pci-bridge.h>
 33 #include <asm/machdep.h>
 34 #include <sysdev/fsl_soc.h>
 35 #include <sysdev/fsl_pci.h>
 36 
 37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
 38 
 39 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
 40 {
 41         u8 progif;
 42 
 43         /* if we aren't a PCIe don't bother */
 44         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
 45                 return;
 46 
 47         /* if we aren't in host mode don't bother */
 48         pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
 49         if (progif & 0x1)
 50                 return;
 51 
 52         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 53         fsl_pcie_bus_fixup = 1;
 54         return;
 55 }
 56 
 57 static int __init fsl_pcie_check_link(struct pci_controller *hose)
 58 {
 59         u32 val;
 60 
 61         early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
 62         if (val < PCIE_LTSSM_L0)
 63                 return 1;
 64         return 0;
 65 }
 66 
 67 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 68 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
 69         unsigned int index, const struct resource *res,
 70         resource_size_t offset)
 71 {
 72         resource_size_t pci_addr = res->start - offset;
 73         resource_size_t phys_addr = res->start;
 74         resource_size_t size = resource_size(res);
 75         u32 flags = 0x80044000; /* enable & mem R/W */
 76         unsigned int i;
 77 
 78         pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
 79                 (u64)res->start, (u64)size);
 80 
 81         if (res->flags & IORESOURCE_PREFETCH)
 82                 flags |= 0x10000000; /* enable relaxed ordering */
 83 
 84         for (i = 0; size > 0; i++) {
 85                 unsigned int bits = min(__ilog2(size),
 86                                         __ffs(pci_addr | phys_addr));
 87 
 88                 if (index + i >= 5)
 89                         return -1;
 90 
 91                 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
 92                 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
 93                 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
 94                 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
 95 
 96                 pci_addr += (resource_size_t)1U << bits;
 97                 phys_addr += (resource_size_t)1U << bits;
 98                 size -= (resource_size_t)1U << bits;
 99         }
100 
101         return i;
102 }
103 
104 /* atmu setup for fsl pci/pcie controller */
105 static void __init setup_pci_atmu(struct pci_controller *hose,
106                                   struct resource *rsrc)
107 {
108         struct ccsr_pci __iomem *pci;
109         int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
110         u64 mem, sz, paddr_hi = 0;
111         u64 paddr_lo = ULLONG_MAX;
112         u32 pcicsrbar = 0, pcicsrbar_sz;
113         u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
114                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
115         char *name = hose->dn->full_name;
116 
117         pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
118                  (u64)rsrc->start, (u64)resource_size(rsrc));
119 
120         if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
121                 win_idx = 2;
122                 start_idx = 0;
123                 end_idx = 3;
124         }
125 
126         pci = ioremap(rsrc->start, resource_size(rsrc));
127         if (!pci) {
128             dev_err(hose->parent, "Unable to map ATMU registers\n");
129             return;
130         }
131 
132         /* Disable all windows (except powar0 since it's ignored) */
133         for(i = 1; i < 5; i++)
134                 out_be32(&pci->pow[i].powar, 0);
135         for (i = start_idx; i < end_idx; i++)
136                 out_be32(&pci->piw[i].piwar, 0);
137 
138         /* Setup outbound MEM window */
139         for(i = 0, j = 1; i < 3; i++) {
140                 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
141                         continue;
142 
143                 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
144                 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
145 
146                 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
147                                    hose->pci_mem_offset);
148 
149                 if (n < 0 || j >= 5) {
150                         pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
151                         hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
152                 } else
153                         j += n;
154         }
155 
156         /* Setup outbound IO window */
157         if (hose->io_resource.flags & IORESOURCE_IO) {
158                 if (j >= 5) {
159                         pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
160                 } else {
161                         pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
162                                  "phy base 0x%016llx.\n",
163                                  (u64)hose->io_resource.start,
164                                  (u64)resource_size(&hose->io_resource),
165                                  (u64)hose->io_base_phys);
166                         out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
167                         out_be32(&pci->pow[j].potear, 0);
168                         out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
169                         /* Enable, IO R/W */
170                         out_be32(&pci->pow[j].powar, 0x80088000
171                                 | (__ilog2(hose->io_resource.end
172                                 - hose->io_resource.start + 1) - 1));
173                 }
174         }
175 
176         /* convert to pci address space */
177         paddr_hi -= hose->pci_mem_offset;
178         paddr_lo -= hose->pci_mem_offset;
179 
180         if (paddr_hi == paddr_lo) {
181                 pr_err("%s: No outbound window space\n", name);
182                 return ;
183         }
184 
185         if (paddr_lo == 0) {
186                 pr_err("%s: No space for inbound window\n", name);
187                 return ;
188         }
189 
190         /* setup PCSRBAR/PEXCSRBAR */
191         early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
192         early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
193         pcicsrbar_sz = ~pcicsrbar_sz + 1;
194 
195         if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
196                 (paddr_lo > 0x100000000ull))
197                 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
198         else
199                 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
200         early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
201 
202         paddr_lo = min(paddr_lo, (u64)pcicsrbar);
203 
204         pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
205 
206         /* Setup inbound mem window */
207         mem = memblock_end_of_DRAM();
208         sz = min(mem, paddr_lo);
209         mem_log = __ilog2_u64(sz);
210 
211         /* PCIe can overmap inbound & outbound since RX & TX are separated */
212         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
213                 /* Size window to exact size if power-of-two or one size up */
214                 if ((1ull << mem_log) != mem) {
215                         if ((1ull << mem_log) > mem)
216                                 pr_info("%s: Setting PCI inbound window "
217                                         "greater than memory size\n", name);
218                         mem_log++;
219                 }
220 
221                 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
222 
223                 /* Setup inbound memory window */
224                 out_be32(&pci->piw[win_idx].pitar,  0x00000000);
225                 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
226                 out_be32(&pci->piw[win_idx].piwar,  piwar);
227                 win_idx--;
228 
229                 hose->dma_window_base_cur = 0x00000000;
230                 hose->dma_window_size = (resource_size_t)sz;
231         } else {
232                 u64 paddr = 0;
233 
234                 /* Setup inbound memory window */
235                 out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
236                 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
237                 out_be32(&pci->piw[win_idx].piwar,  (piwar | (mem_log - 1)));
238                 win_idx--;
239 
240                 paddr += 1ull << mem_log;
241                 sz -= 1ull << mem_log;
242 
243                 if (sz) {
244                         mem_log = __ilog2_u64(sz);
245                         piwar |= (mem_log - 1);
246 
247                         out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
248                         out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
249                         out_be32(&pci->piw[win_idx].piwar,  piwar);
250                         win_idx--;
251 
252                         paddr += 1ull << mem_log;
253                 }
254 
255                 hose->dma_window_base_cur = 0x00000000;
256                 hose->dma_window_size = (resource_size_t)paddr;
257         }
258 
259         if (hose->dma_window_size < mem) {
260 #ifndef CONFIG_SWIOTLB
261                 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
262                         "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
263                          name);
264 #endif
265                 /* adjusting outbound windows could reclaim space in mem map */
266                 if (paddr_hi < 0xffffffffull)
267                         pr_warning("%s: WARNING: Outbound window cfg leaves "
268                                 "gaps in memory map. Adjusting the memory map "
269                                 "could reduce unnecessary bounce buffering.\n",
270                                 name);
271 
272                 pr_info("%s: DMA window size is 0x%llx\n", name,
273                         (u64)hose->dma_window_size);
274         }
275 
276         iounmap(pci);
277 }
278 
279 static void __init setup_pci_cmd(struct pci_controller *hose)
280 {
281         u16 cmd;
282         int cap_x;
283 
284         early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
285         cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
286                 | PCI_COMMAND_IO;
287         early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
288 
289         cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
290         if (cap_x) {
291                 int pci_x_cmd = cap_x + PCI_X_CMD;
292                 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
293                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
294                 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
295         } else {
296                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
297         }
298 }
299 
300 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
301 {
302         struct pci_controller *hose = pci_bus_to_host(bus);
303         int i;
304 
305         if ((bus->parent == hose->bus) &&
306             ((fsl_pcie_bus_fixup &&
307               early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
308              (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
309         {
310                 for (i = 0; i < 4; ++i) {
311                         struct resource *res = bus->resource[i];
312                         struct resource *par = bus->parent->resource[i];
313                         if (res) {
314                                 res->start = 0;
315                                 res->end   = 0;
316                                 res->flags = 0;
317                         }
318                         if (res && par) {
319                                 res->start = par->start;
320                                 res->end   = par->end;
321                                 res->flags = par->flags;
322                         }
323                 }
324         }
325 }
326 
327 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
328 {
329         int len;
330         struct pci_controller *hose;
331         struct resource rsrc;
332         const int *bus_range;
333         u8 progif;
334 
335         if (!of_device_is_available(dev)) {
336                 pr_warning("%s: disabled\n", dev->full_name);
337                 return -ENODEV;
338         }
339 
340         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
341 
342         /* Fetch host bridge registers address */
343         if (of_address_to_resource(dev, 0, &rsrc)) {
344                 printk(KERN_WARNING "Can't get pci register base!");
345                 return -ENOMEM;
346         }
347 
348         /* Get bus range if any */
349         bus_range = of_get_property(dev, "bus-range", &len);
350         if (bus_range == NULL || len < 2 * sizeof(int))
351                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
352                         " bus 0\n", dev->full_name);
353 
354         pci_add_flags(PCI_REASSIGN_ALL_BUS);
355         hose = pcibios_alloc_controller(dev);
356         if (!hose)
357                 return -ENOMEM;
358 
359         hose->first_busno = bus_range ? bus_range[0] : 0x0;
360         hose->last_busno = bus_range ? bus_range[1] : 0xff;
361 
362         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
363                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
364 
365         early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
366         if ((progif & 1) == 1) {
367                 /* unmap cfg_data & cfg_addr separately if not on same page */
368                 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
369                     ((unsigned long)hose->cfg_addr & PAGE_MASK))
370                         iounmap(hose->cfg_data);
371                 iounmap(hose->cfg_addr);
372                 pcibios_free_controller(hose);
373                 return 0;
374         }
375 
376         setup_pci_cmd(hose);
377 
378         /* check PCI express link status */
379         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
380                 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
381                         PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
382                 if (fsl_pcie_check_link(hose))
383                         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
384         }
385 
386         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
387                 "Firmware bus number: %d->%d\n",
388                 (unsigned long long)rsrc.start, hose->first_busno,
389                 hose->last_busno);
390 
391         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
392                 hose, hose->cfg_addr, hose->cfg_data);
393 
394         /* Interpret the "ranges" property */
395         /* This also maps the I/O region and sets isa_io/mem_base */
396         pci_process_bridge_OF_ranges(hose, dev, is_primary);
397 
398         /* Setup PEX window registers */
399         setup_pci_atmu(hose, &rsrc);
400 
401         return 0;
402 }
403 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
404 
405 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
406 
407 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
408 struct mpc83xx_pcie_priv {
409         void __iomem *cfg_type0;
410         void __iomem *cfg_type1;
411         u32 dev_base;
412 };
413 
414 struct pex_inbound_window {
415         u32 ar;
416         u32 tar;
417         u32 barl;
418         u32 barh;
419 };
420 
421 /*
422  * With the convention of u-boot, the PCIE outbound window 0 serves
423  * as configuration transactions outbound.
424  */
425 #define PEX_OUTWIN0_BAR         0xCA4
426 #define PEX_OUTWIN0_TAL         0xCA8
427 #define PEX_OUTWIN0_TAH         0xCAC
428 #define PEX_RC_INWIN_BASE       0xE60
429 #define PEX_RCIWARn_EN          0x1
430 
431 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
432 {
433         struct pci_controller *hose = pci_bus_to_host(bus);
434 
435         if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
436                 return PCIBIOS_DEVICE_NOT_FOUND;
437         /*
438          * Workaround for the HW bug: for Type 0 configure transactions the
439          * PCI-E controller does not check the device number bits and just
440          * assumes that the device number bits are 0.
441          */
442         if (bus->number == hose->first_busno ||
443                         bus->primary == hose->first_busno) {
444                 if (devfn & 0xf8)
445                         return PCIBIOS_DEVICE_NOT_FOUND;
446         }
447 
448         if (ppc_md.pci_exclude_device) {
449                 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
450                         return PCIBIOS_DEVICE_NOT_FOUND;
451         }
452 
453         return PCIBIOS_SUCCESSFUL;
454 }
455 
456 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
457                                             unsigned int devfn, int offset)
458 {
459         struct pci_controller *hose = pci_bus_to_host(bus);
460         struct mpc83xx_pcie_priv *pcie = hose->dn->data;
461         u32 dev_base = bus->number << 24 | devfn << 16;
462         int ret;
463 
464         ret = mpc83xx_pcie_exclude_device(bus, devfn);
465         if (ret)
466                 return NULL;
467 
468         offset &= 0xfff;
469 
470         /* Type 0 */
471         if (bus->number == hose->first_busno)
472                 return pcie->cfg_type0 + offset;
473 
474         if (pcie->dev_base == dev_base)
475                 goto mapped;
476 
477         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
478 
479         pcie->dev_base = dev_base;
480 mapped:
481         return pcie->cfg_type1 + offset;
482 }
483 
484 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
485                                     int offset, int len, u32 *val)
486 {
487         void __iomem *cfg_addr;
488 
489         cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
490         if (!cfg_addr)
491                 return PCIBIOS_DEVICE_NOT_FOUND;
492 
493         switch (len) {
494         case 1:
495                 *val = in_8(cfg_addr);
496                 break;
497         case 2:
498                 *val = in_le16(cfg_addr);
499                 break;
500         default:
501                 *val = in_le32(cfg_addr);
502                 break;
503         }
504 
505         return PCIBIOS_SUCCESSFUL;
506 }
507 
508 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
509                                      int offset, int len, u32 val)
510 {
511         struct pci_controller *hose = pci_bus_to_host(bus);
512         void __iomem *cfg_addr;
513 
514         cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
515         if (!cfg_addr)
516                 return PCIBIOS_DEVICE_NOT_FOUND;
517 
518         /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
519         if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
520                 val &= 0xffffff00;
521 
522         switch (len) {
523         case 1:
524                 out_8(cfg_addr, val);
525                 break;
526         case 2:
527                 out_le16(cfg_addr, val);
528                 break;
529         default:
530                 out_le32(cfg_addr, val);
531                 break;
532         }
533 
534         return PCIBIOS_SUCCESSFUL;
535 }
536 
537 static struct pci_ops mpc83xx_pcie_ops = {
538         .read = mpc83xx_pcie_read_config,
539         .write = mpc83xx_pcie_write_config,
540 };
541 
542 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
543                                      struct resource *reg)
544 {
545         struct mpc83xx_pcie_priv *pcie;
546         u32 cfg_bar;
547         int ret = -ENOMEM;
548 
549         pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
550         if (!pcie)
551                 return ret;
552 
553         pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
554         if (!pcie->cfg_type0)
555                 goto err0;
556 
557         cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
558         if (!cfg_bar) {
559                 /* PCI-E isn't configured. */
560                 ret = -ENODEV;
561                 goto err1;
562         }
563 
564         pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
565         if (!pcie->cfg_type1)
566                 goto err1;
567 
568         WARN_ON(hose->dn->data);
569         hose->dn->data = pcie;
570         hose->ops = &mpc83xx_pcie_ops;
571 
572         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
573         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
574 
575         if (fsl_pcie_check_link(hose))
576                 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
577 
578         return 0;
579 err1:
580         iounmap(pcie->cfg_type0);
581 err0:
582         kfree(pcie);
583         return ret;
584 
585 }
586 
587 int __init mpc83xx_add_bridge(struct device_node *dev)
588 {
589         int ret;
590         int len;
591         struct pci_controller *hose;
592         struct resource rsrc_reg;
593         struct resource rsrc_cfg;
594         const int *bus_range;
595         int primary;
596 
597         is_mpc83xx_pci = 1;
598 
599         if (!of_device_is_available(dev)) {
600                 pr_warning("%s: disabled by the firmware.\n",
601                            dev->full_name);
602                 return -ENODEV;
603         }
604         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
605 
606         /* Fetch host bridge registers address */
607         if (of_address_to_resource(dev, 0, &rsrc_reg)) {
608                 printk(KERN_WARNING "Can't get pci register base!\n");
609                 return -ENOMEM;
610         }
611 
612         memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
613 
614         if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
615                 printk(KERN_WARNING
616                         "No pci config register base in dev tree, "
617                         "using default\n");
618                 /*
619                  * MPC83xx supports up to two host controllers
620                  *      one at 0x8500 has config space registers at 0x8300
621                  *      one at 0x8600 has config space registers at 0x8380
622                  */
623                 if ((rsrc_reg.start & 0xfffff) == 0x8500)
624                         rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
625                 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
626                         rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
627         }
628         /*
629          * Controller at offset 0x8500 is primary
630          */
631         if ((rsrc_reg.start & 0xfffff) == 0x8500)
632                 primary = 1;
633         else
634                 primary = 0;
635 
636         /* Get bus range if any */
637         bus_range = of_get_property(dev, "bus-range", &len);
638         if (bus_range == NULL || len < 2 * sizeof(int)) {
639                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
640                        " bus 0\n", dev->full_name);
641         }
642 
643         pci_add_flags(PCI_REASSIGN_ALL_BUS);
644         hose = pcibios_alloc_controller(dev);
645         if (!hose)
646                 return -ENOMEM;
647 
648         hose->first_busno = bus_range ? bus_range[0] : 0;
649         hose->last_busno = bus_range ? bus_range[1] : 0xff;
650 
651         if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
652                 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
653                 if (ret)
654                         goto err0;
655         } else {
656                 setup_indirect_pci(hose, rsrc_cfg.start,
657                                    rsrc_cfg.start + 4, 0);
658         }
659 
660         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
661                "Firmware bus number: %d->%d\n",
662                (unsigned long long)rsrc_reg.start, hose->first_busno,
663                hose->last_busno);
664 
665         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
666             hose, hose->cfg_addr, hose->cfg_data);
667 
668         /* Interpret the "ranges" property */
669         /* This also maps the I/O region and sets isa_io/mem_base */
670         pci_process_bridge_OF_ranges(hose, dev, primary);
671 
672         return 0;
673 err0:
674         pcibios_free_controller(hose);
675         return ret;
676 }
677 #endif /* CONFIG_PPC_83xx */
678 
679 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
680 {
681 #ifdef CONFIG_PPC_83xx
682         if (is_mpc83xx_pci) {
683                 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
684                 struct pex_inbound_window *in;
685                 int i;
686 
687                 /* Walk the Root Complex Inbound windows to match IMMR base */
688                 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
689                 for (i = 0; i < 4; i++) {
690                         /* not enabled, skip */
691                         if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
692                                  continue;
693 
694                         if (get_immrbase() == in_le32(&in[i].tar))
695                                 return (u64)in_le32(&in[i].barh) << 32 |
696                                             in_le32(&in[i].barl);
697                 }
698 
699                 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
700         }
701 #endif
702 
703 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
704         if (!is_mpc83xx_pci) {
705                 u32 base;
706 
707                 pci_bus_read_config_dword(hose->bus,
708                         PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
709                 return base;
710         }
711 #endif
712 
713         return 0;
714 }
715 

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